mediatek: backport upstream mediatek patches
[openwrt/openwrt.git] / target / linux / mediatek / patches-4.14 / 0138-rtc-mediatek-add-driver-for-RTC-on-MT7622-SoC.patch
1 From 4cf0b74c175cb5cb751e449223c0baafc2f98499 Mon Sep 17 00:00:00 2001
2 From: Sean Wang <sean.wang@mediatek.com>
3 Date: Mon, 23 Oct 2017 15:16:45 +0800
4 Subject: [PATCH 138/224] rtc: mediatek: add driver for RTC on MT7622 SoC
5
6 This patch introduces the driver for the RTC on MT7622 SoC.
7
8 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
9 Reviewed-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
10 Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
11 ---
12 drivers/rtc/Kconfig | 10 ++
13 drivers/rtc/Makefile | 1 +
14 drivers/rtc/rtc-mt7622.c | 422 +++++++++++++++++++++++++++++++++++++++++++++++
15 3 files changed, 433 insertions(+)
16 create mode 100644 drivers/rtc/rtc-mt7622.c
17
18 diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
19 index e0e58f3b1420..322752ebc5a7 100644
20 --- a/drivers/rtc/Kconfig
21 +++ b/drivers/rtc/Kconfig
22 @@ -1715,6 +1715,16 @@ config RTC_DRV_MT6397
23
24 If you want to use Mediatek(R) RTC interface, select Y or M here.
25
26 +config RTC_DRV_MT7622
27 + tristate "MediaTek SoC based RTC"
28 + depends on ARCH_MEDIATEK || COMPILE_TEST
29 + help
30 + This enables support for the real time clock built in the MediaTek
31 + SoCs.
32 +
33 + This drive can also be built as a module. If so, the module
34 + will be called rtc-mt7622.
35 +
36 config RTC_DRV_XGENE
37 tristate "APM X-Gene RTC"
38 depends on HAS_IOMEM
39 diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
40 index 7230014c92af..5ec891a81f4f 100644
41 --- a/drivers/rtc/Makefile
42 +++ b/drivers/rtc/Makefile
43 @@ -102,6 +102,7 @@ obj-$(CONFIG_RTC_DRV_MPC5121) += rtc-mpc5121.o
44 obj-$(CONFIG_RTC_DRV_VRTC) += rtc-mrst.o
45 obj-$(CONFIG_RTC_DRV_MSM6242) += rtc-msm6242.o
46 obj-$(CONFIG_RTC_DRV_MT6397) += rtc-mt6397.o
47 +obj-$(CONFIG_RTC_DRV_MT7622) += rtc-mt7622.o
48 obj-$(CONFIG_RTC_DRV_MV) += rtc-mv.o
49 obj-$(CONFIG_RTC_DRV_MXC) += rtc-mxc.o
50 obj-$(CONFIG_RTC_DRV_NUC900) += rtc-nuc900.o
51 diff --git a/drivers/rtc/rtc-mt7622.c b/drivers/rtc/rtc-mt7622.c
52 new file mode 100644
53 index 000000000000..d79b9ae4d237
54 --- /dev/null
55 +++ b/drivers/rtc/rtc-mt7622.c
56 @@ -0,0 +1,422 @@
57 +/*
58 + * Driver for MediaTek SoC based RTC
59 + *
60 + * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
61 + *
62 + * This program is free software; you can redistribute it and/or
63 + * modify it under the terms of the GNU General Public License as
64 + * published by the Free Software Foundation; either version 2 of
65 + * the License, or (at your option) any later version.
66 + *
67 + * This program is distributed in the hope that it will be useful,
68 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
69 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
70 + * GNU General Public License for more details.
71 + */
72 +
73 +#include <linux/clk.h>
74 +#include <linux/interrupt.h>
75 +#include <linux/module.h>
76 +#include <linux/of_address.h>
77 +#include <linux/of_device.h>
78 +#include <linux/platform_device.h>
79 +#include <linux/rtc.h>
80 +
81 +#define MTK_RTC_DEV KBUILD_MODNAME
82 +
83 +#define MTK_RTC_PWRCHK1 0x4
84 +#define RTC_PWRCHK1_MAGIC 0xc6
85 +
86 +#define MTK_RTC_PWRCHK2 0x8
87 +#define RTC_PWRCHK2_MAGIC 0x9a
88 +
89 +#define MTK_RTC_KEY 0xc
90 +#define RTC_KEY_MAGIC 0x59
91 +
92 +#define MTK_RTC_PROT1 0x10
93 +#define RTC_PROT1_MAGIC 0xa3
94 +
95 +#define MTK_RTC_PROT2 0x14
96 +#define RTC_PROT2_MAGIC 0x57
97 +
98 +#define MTK_RTC_PROT3 0x18
99 +#define RTC_PROT3_MAGIC 0x67
100 +
101 +#define MTK_RTC_PROT4 0x1c
102 +#define RTC_PROT4_MAGIC 0xd2
103 +
104 +#define MTK_RTC_CTL 0x20
105 +#define RTC_RC_STOP BIT(0)
106 +
107 +#define MTK_RTC_DEBNCE 0x2c
108 +#define RTC_DEBNCE_MASK GENMASK(2, 0)
109 +
110 +#define MTK_RTC_INT 0x30
111 +#define RTC_INT_AL_STA BIT(4)
112 +
113 +/*
114 + * Ranges from 0x40 to 0x78 provide RTC time setup for year, month,
115 + * day of month, day of week, hour, minute and second.
116 + */
117 +#define MTK_RTC_TREG(_t, _f) (0x40 + (0x4 * (_f)) + ((_t) * 0x20))
118 +
119 +#define MTK_RTC_AL_CTL 0x7c
120 +#define RTC_AL_EN BIT(0)
121 +#define RTC_AL_ALL GENMASK(7, 0)
122 +
123 +/*
124 + * The offset is used in the translation for the year between in struct
125 + * rtc_time and in hardware register MTK_RTC_TREG(x,MTK_YEA)
126 + */
127 +#define MTK_RTC_TM_YR_OFFSET 100
128 +
129 +/*
130 + * The lowest value for the valid tm_year. RTC hardware would take incorrectly
131 + * tm_year 100 as not a leap year and thus it is also required being excluded
132 + * from the valid options.
133 + */
134 +#define MTK_RTC_TM_YR_L (MTK_RTC_TM_YR_OFFSET + 1)
135 +
136 +/*
137 + * The most year the RTC can hold is 99 and the next to 99 in year register
138 + * would be wraparound to 0, for MT7622.
139 + */
140 +#define MTK_RTC_HW_YR_LIMIT 99
141 +
142 +/* The highest value for the valid tm_year */
143 +#define MTK_RTC_TM_YR_H (MTK_RTC_TM_YR_OFFSET + MTK_RTC_HW_YR_LIMIT)
144 +
145 +/* Simple macro helps to check whether the hardware supports the tm_year */
146 +#define MTK_RTC_TM_YR_VALID(_y) ((_y) >= MTK_RTC_TM_YR_L && \
147 + (_y) <= MTK_RTC_TM_YR_H)
148 +
149 +/* Types of the function the RTC provides are time counter and alarm. */
150 +enum {
151 + MTK_TC,
152 + MTK_AL,
153 +};
154 +
155 +/* Indexes are used for the pointer to relevant registers in MTK_RTC_TREG */
156 +enum {
157 + MTK_YEA,
158 + MTK_MON,
159 + MTK_DOM,
160 + MTK_DOW,
161 + MTK_HOU,
162 + MTK_MIN,
163 + MTK_SEC
164 +};
165 +
166 +struct mtk_rtc {
167 + struct rtc_device *rtc;
168 + void __iomem *base;
169 + int irq;
170 + struct clk *clk;
171 +};
172 +
173 +static void mtk_w32(struct mtk_rtc *rtc, u32 reg, u32 val)
174 +{
175 + writel_relaxed(val, rtc->base + reg);
176 +}
177 +
178 +static u32 mtk_r32(struct mtk_rtc *rtc, u32 reg)
179 +{
180 + return readl_relaxed(rtc->base + reg);
181 +}
182 +
183 +static void mtk_rmw(struct mtk_rtc *rtc, u32 reg, u32 mask, u32 set)
184 +{
185 + u32 val;
186 +
187 + val = mtk_r32(rtc, reg);
188 + val &= ~mask;
189 + val |= set;
190 + mtk_w32(rtc, reg, val);
191 +}
192 +
193 +static void mtk_set(struct mtk_rtc *rtc, u32 reg, u32 val)
194 +{
195 + mtk_rmw(rtc, reg, 0, val);
196 +}
197 +
198 +static void mtk_clr(struct mtk_rtc *rtc, u32 reg, u32 val)
199 +{
200 + mtk_rmw(rtc, reg, val, 0);
201 +}
202 +
203 +static void mtk_rtc_hw_init(struct mtk_rtc *hw)
204 +{
205 + /* The setup of the init sequence is for allowing RTC got to work */
206 + mtk_w32(hw, MTK_RTC_PWRCHK1, RTC_PWRCHK1_MAGIC);
207 + mtk_w32(hw, MTK_RTC_PWRCHK2, RTC_PWRCHK2_MAGIC);
208 + mtk_w32(hw, MTK_RTC_KEY, RTC_KEY_MAGIC);
209 + mtk_w32(hw, MTK_RTC_PROT1, RTC_PROT1_MAGIC);
210 + mtk_w32(hw, MTK_RTC_PROT2, RTC_PROT2_MAGIC);
211 + mtk_w32(hw, MTK_RTC_PROT3, RTC_PROT3_MAGIC);
212 + mtk_w32(hw, MTK_RTC_PROT4, RTC_PROT4_MAGIC);
213 + mtk_rmw(hw, MTK_RTC_DEBNCE, RTC_DEBNCE_MASK, 0);
214 + mtk_clr(hw, MTK_RTC_CTL, RTC_RC_STOP);
215 +}
216 +
217 +static void mtk_rtc_get_alarm_or_time(struct mtk_rtc *hw, struct rtc_time *tm,
218 + int time_alarm)
219 +{
220 + u32 year, mon, mday, wday, hour, min, sec;
221 +
222 + /*
223 + * Read again until the field of the second is not changed which
224 + * ensures all fields in the consistent state. Note that MTK_SEC must
225 + * be read first. In this way, it guarantees the others remain not
226 + * changed when the results for two MTK_SEC consecutive reads are same.
227 + */
228 + do {
229 + sec = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_SEC));
230 + min = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_MIN));
231 + hour = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_HOU));
232 + wday = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_DOW));
233 + mday = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_DOM));
234 + mon = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_MON));
235 + year = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_YEA));
236 + } while (sec != mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_SEC)));
237 +
238 + tm->tm_sec = sec;
239 + tm->tm_min = min;
240 + tm->tm_hour = hour;
241 + tm->tm_wday = wday;
242 + tm->tm_mday = mday;
243 + tm->tm_mon = mon - 1;
244 +
245 + /* Rebase to the absolute year which userspace queries */
246 + tm->tm_year = year + MTK_RTC_TM_YR_OFFSET;
247 +}
248 +
249 +static void mtk_rtc_set_alarm_or_time(struct mtk_rtc *hw, struct rtc_time *tm,
250 + int time_alarm)
251 +{
252 + u32 year;
253 +
254 + /* Rebase to the relative year which RTC hardware requires */
255 + year = tm->tm_year - MTK_RTC_TM_YR_OFFSET;
256 +
257 + mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_YEA), year);
258 + mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_MON), tm->tm_mon + 1);
259 + mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_DOW), tm->tm_wday);
260 + mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_DOM), tm->tm_mday);
261 + mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_HOU), tm->tm_hour);
262 + mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_MIN), tm->tm_min);
263 + mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_SEC), tm->tm_sec);
264 +}
265 +
266 +static irqreturn_t mtk_rtc_alarmirq(int irq, void *id)
267 +{
268 + struct mtk_rtc *hw = (struct mtk_rtc *)id;
269 + u32 irq_sta;
270 +
271 + irq_sta = mtk_r32(hw, MTK_RTC_INT);
272 + if (irq_sta & RTC_INT_AL_STA) {
273 + /* Stop alarm also implicitly disables the alarm interrupt */
274 + mtk_w32(hw, MTK_RTC_AL_CTL, 0);
275 + rtc_update_irq(hw->rtc, 1, RTC_IRQF | RTC_AF);
276 +
277 + /* Ack alarm interrupt status */
278 + mtk_w32(hw, MTK_RTC_INT, RTC_INT_AL_STA);
279 + return IRQ_HANDLED;
280 + }
281 +
282 + return IRQ_NONE;
283 +}
284 +
285 +static int mtk_rtc_gettime(struct device *dev, struct rtc_time *tm)
286 +{
287 + struct mtk_rtc *hw = dev_get_drvdata(dev);
288 +
289 + mtk_rtc_get_alarm_or_time(hw, tm, MTK_TC);
290 +
291 + return rtc_valid_tm(tm);
292 +}
293 +
294 +static int mtk_rtc_settime(struct device *dev, struct rtc_time *tm)
295 +{
296 + struct mtk_rtc *hw = dev_get_drvdata(dev);
297 +
298 + if (!MTK_RTC_TM_YR_VALID(tm->tm_year))
299 + return -EINVAL;
300 +
301 + /* Stop time counter before setting a new one*/
302 + mtk_set(hw, MTK_RTC_CTL, RTC_RC_STOP);
303 +
304 + mtk_rtc_set_alarm_or_time(hw, tm, MTK_TC);
305 +
306 + /* Restart the time counter */
307 + mtk_clr(hw, MTK_RTC_CTL, RTC_RC_STOP);
308 +
309 + return 0;
310 +}
311 +
312 +static int mtk_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
313 +{
314 + struct mtk_rtc *hw = dev_get_drvdata(dev);
315 + struct rtc_time *alrm_tm = &wkalrm->time;
316 +
317 + mtk_rtc_get_alarm_or_time(hw, alrm_tm, MTK_AL);
318 +
319 + wkalrm->enabled = !!(mtk_r32(hw, MTK_RTC_AL_CTL) & RTC_AL_EN);
320 + wkalrm->pending = !!(mtk_r32(hw, MTK_RTC_INT) & RTC_INT_AL_STA);
321 +
322 + return 0;
323 +}
324 +
325 +static int mtk_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
326 +{
327 + struct mtk_rtc *hw = dev_get_drvdata(dev);
328 + struct rtc_time *alrm_tm = &wkalrm->time;
329 +
330 + if (!MTK_RTC_TM_YR_VALID(alrm_tm->tm_year))
331 + return -EINVAL;
332 +
333 + /*
334 + * Stop the alarm also implicitly including disables interrupt before
335 + * setting a new one.
336 + */
337 + mtk_clr(hw, MTK_RTC_AL_CTL, RTC_AL_EN);
338 +
339 + /*
340 + * Avoid contention between mtk_rtc_setalarm and IRQ handler so that
341 + * disabling the interrupt and awaiting for pending IRQ handler to
342 + * complete.
343 + */
344 + synchronize_irq(hw->irq);
345 +
346 + mtk_rtc_set_alarm_or_time(hw, alrm_tm, MTK_AL);
347 +
348 + /* Restart the alarm with the new setup */
349 + mtk_w32(hw, MTK_RTC_AL_CTL, RTC_AL_ALL);
350 +
351 + return 0;
352 +}
353 +
354 +static const struct rtc_class_ops mtk_rtc_ops = {
355 + .read_time = mtk_rtc_gettime,
356 + .set_time = mtk_rtc_settime,
357 + .read_alarm = mtk_rtc_getalarm,
358 + .set_alarm = mtk_rtc_setalarm,
359 +};
360 +
361 +static const struct of_device_id mtk_rtc_match[] = {
362 + { .compatible = "mediatek,mt7622-rtc" },
363 + { .compatible = "mediatek,soc-rtc" },
364 + {},
365 +};
366 +
367 +static int mtk_rtc_probe(struct platform_device *pdev)
368 +{
369 + struct mtk_rtc *hw;
370 + struct resource *res;
371 + int ret;
372 +
373 + hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL);
374 + if (!hw)
375 + return -ENOMEM;
376 +
377 + platform_set_drvdata(pdev, hw);
378 +
379 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
380 + hw->base = devm_ioremap_resource(&pdev->dev, res);
381 + if (IS_ERR(hw->base))
382 + return PTR_ERR(hw->base);
383 +
384 + hw->clk = devm_clk_get(&pdev->dev, "rtc");
385 + if (IS_ERR(hw->clk)) {
386 + dev_err(&pdev->dev, "No clock\n");
387 + return PTR_ERR(hw->clk);
388 + }
389 +
390 + ret = clk_prepare_enable(hw->clk);
391 + if (ret)
392 + return ret;
393 +
394 + hw->irq = platform_get_irq(pdev, 0);
395 + if (hw->irq < 0) {
396 + dev_err(&pdev->dev, "No IRQ resource\n");
397 + ret = hw->irq;
398 + goto err;
399 + }
400 +
401 + ret = devm_request_irq(&pdev->dev, hw->irq, mtk_rtc_alarmirq,
402 + 0, dev_name(&pdev->dev), hw);
403 + if (ret) {
404 + dev_err(&pdev->dev, "Can't request IRQ\n");
405 + goto err;
406 + }
407 +
408 + mtk_rtc_hw_init(hw);
409 +
410 + device_init_wakeup(&pdev->dev, true);
411 +
412 + hw->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
413 + &mtk_rtc_ops, THIS_MODULE);
414 + if (IS_ERR(hw->rtc)) {
415 + ret = PTR_ERR(hw->rtc);
416 + dev_err(&pdev->dev, "Unable to register device\n");
417 + goto err;
418 + }
419 +
420 + return 0;
421 +err:
422 + clk_disable_unprepare(hw->clk);
423 +
424 + return ret;
425 +}
426 +
427 +static int mtk_rtc_remove(struct platform_device *pdev)
428 +{
429 + struct mtk_rtc *hw = platform_get_drvdata(pdev);
430 +
431 + clk_disable_unprepare(hw->clk);
432 +
433 + return 0;
434 +}
435 +
436 +#ifdef CONFIG_PM_SLEEP
437 +static int mtk_rtc_suspend(struct device *dev)
438 +{
439 + struct mtk_rtc *hw = dev_get_drvdata(dev);
440 +
441 + if (device_may_wakeup(dev))
442 + enable_irq_wake(hw->irq);
443 +
444 + return 0;
445 +}
446 +
447 +static int mtk_rtc_resume(struct device *dev)
448 +{
449 + struct mtk_rtc *hw = dev_get_drvdata(dev);
450 +
451 + if (device_may_wakeup(dev))
452 + disable_irq_wake(hw->irq);
453 +
454 + return 0;
455 +}
456 +
457 +static SIMPLE_DEV_PM_OPS(mtk_rtc_pm_ops, mtk_rtc_suspend, mtk_rtc_resume);
458 +
459 +#define MTK_RTC_PM_OPS (&mtk_rtc_pm_ops)
460 +#else /* CONFIG_PM */
461 +#define MTK_RTC_PM_OPS NULL
462 +#endif /* CONFIG_PM */
463 +
464 +static struct platform_driver mtk_rtc_driver = {
465 + .probe = mtk_rtc_probe,
466 + .remove = mtk_rtc_remove,
467 + .driver = {
468 + .name = MTK_RTC_DEV,
469 + .of_match_table = mtk_rtc_match,
470 + .pm = MTK_RTC_PM_OPS,
471 + },
472 +};
473 +
474 +module_platform_driver(mtk_rtc_driver);
475 +
476 +MODULE_DESCRIPTION("MediaTek SoC based RTC Driver");
477 +MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
478 +MODULE_LICENSE("GPL");
479 --
480 2.11.0
481