ath79: modify device name of I-O DATA WN-AC1600DGR2
[openwrt/openwrt.git] / target / linux / mediatek / patches-4.14 / 0138-rtc-mediatek-add-driver-for-RTC-on-MT7622-SoC.patch
1 From 4cf0b74c175cb5cb751e449223c0baafc2f98499 Mon Sep 17 00:00:00 2001
2 From: Sean Wang <sean.wang@mediatek.com>
3 Date: Mon, 23 Oct 2017 15:16:45 +0800
4 Subject: [PATCH 138/224] rtc: mediatek: add driver for RTC on MT7622 SoC
5
6 This patch introduces the driver for the RTC on MT7622 SoC.
7
8 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
9 Reviewed-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
10 Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
11 ---
12 drivers/rtc/Kconfig | 10 ++
13 drivers/rtc/Makefile | 1 +
14 drivers/rtc/rtc-mt7622.c | 422 +++++++++++++++++++++++++++++++++++++++++++++++
15 3 files changed, 433 insertions(+)
16 create mode 100644 drivers/rtc/rtc-mt7622.c
17
18 --- a/drivers/rtc/Kconfig
19 +++ b/drivers/rtc/Kconfig
20 @@ -1715,6 +1715,16 @@ config RTC_DRV_MT6397
21
22 If you want to use Mediatek(R) RTC interface, select Y or M here.
23
24 +config RTC_DRV_MT7622
25 + tristate "MediaTek SoC based RTC"
26 + depends on ARCH_MEDIATEK || COMPILE_TEST
27 + help
28 + This enables support for the real time clock built in the MediaTek
29 + SoCs.
30 +
31 + This drive can also be built as a module. If so, the module
32 + will be called rtc-mt7622.
33 +
34 config RTC_DRV_XGENE
35 tristate "APM X-Gene RTC"
36 depends on HAS_IOMEM
37 --- a/drivers/rtc/Makefile
38 +++ b/drivers/rtc/Makefile
39 @@ -103,6 +103,7 @@ obj-$(CONFIG_RTC_DRV_MPC5121) += rtc-mpc
40 obj-$(CONFIG_RTC_DRV_VRTC) += rtc-mrst.o
41 obj-$(CONFIG_RTC_DRV_MSM6242) += rtc-msm6242.o
42 obj-$(CONFIG_RTC_DRV_MT6397) += rtc-mt6397.o
43 +obj-$(CONFIG_RTC_DRV_MT7622) += rtc-mt7622.o
44 obj-$(CONFIG_RTC_DRV_MV) += rtc-mv.o
45 obj-$(CONFIG_RTC_DRV_MXC) += rtc-mxc.o
46 obj-$(CONFIG_RTC_DRV_NUC900) += rtc-nuc900.o
47 --- /dev/null
48 +++ b/drivers/rtc/rtc-mt7622.c
49 @@ -0,0 +1,422 @@
50 +/*
51 + * Driver for MediaTek SoC based RTC
52 + *
53 + * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
54 + *
55 + * This program is free software; you can redistribute it and/or
56 + * modify it under the terms of the GNU General Public License as
57 + * published by the Free Software Foundation; either version 2 of
58 + * the License, or (at your option) any later version.
59 + *
60 + * This program is distributed in the hope that it will be useful,
61 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
62 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
63 + * GNU General Public License for more details.
64 + */
65 +
66 +#include <linux/clk.h>
67 +#include <linux/interrupt.h>
68 +#include <linux/module.h>
69 +#include <linux/of_address.h>
70 +#include <linux/of_device.h>
71 +#include <linux/platform_device.h>
72 +#include <linux/rtc.h>
73 +
74 +#define MTK_RTC_DEV KBUILD_MODNAME
75 +
76 +#define MTK_RTC_PWRCHK1 0x4
77 +#define RTC_PWRCHK1_MAGIC 0xc6
78 +
79 +#define MTK_RTC_PWRCHK2 0x8
80 +#define RTC_PWRCHK2_MAGIC 0x9a
81 +
82 +#define MTK_RTC_KEY 0xc
83 +#define RTC_KEY_MAGIC 0x59
84 +
85 +#define MTK_RTC_PROT1 0x10
86 +#define RTC_PROT1_MAGIC 0xa3
87 +
88 +#define MTK_RTC_PROT2 0x14
89 +#define RTC_PROT2_MAGIC 0x57
90 +
91 +#define MTK_RTC_PROT3 0x18
92 +#define RTC_PROT3_MAGIC 0x67
93 +
94 +#define MTK_RTC_PROT4 0x1c
95 +#define RTC_PROT4_MAGIC 0xd2
96 +
97 +#define MTK_RTC_CTL 0x20
98 +#define RTC_RC_STOP BIT(0)
99 +
100 +#define MTK_RTC_DEBNCE 0x2c
101 +#define RTC_DEBNCE_MASK GENMASK(2, 0)
102 +
103 +#define MTK_RTC_INT 0x30
104 +#define RTC_INT_AL_STA BIT(4)
105 +
106 +/*
107 + * Ranges from 0x40 to 0x78 provide RTC time setup for year, month,
108 + * day of month, day of week, hour, minute and second.
109 + */
110 +#define MTK_RTC_TREG(_t, _f) (0x40 + (0x4 * (_f)) + ((_t) * 0x20))
111 +
112 +#define MTK_RTC_AL_CTL 0x7c
113 +#define RTC_AL_EN BIT(0)
114 +#define RTC_AL_ALL GENMASK(7, 0)
115 +
116 +/*
117 + * The offset is used in the translation for the year between in struct
118 + * rtc_time and in hardware register MTK_RTC_TREG(x,MTK_YEA)
119 + */
120 +#define MTK_RTC_TM_YR_OFFSET 100
121 +
122 +/*
123 + * The lowest value for the valid tm_year. RTC hardware would take incorrectly
124 + * tm_year 100 as not a leap year and thus it is also required being excluded
125 + * from the valid options.
126 + */
127 +#define MTK_RTC_TM_YR_L (MTK_RTC_TM_YR_OFFSET + 1)
128 +
129 +/*
130 + * The most year the RTC can hold is 99 and the next to 99 in year register
131 + * would be wraparound to 0, for MT7622.
132 + */
133 +#define MTK_RTC_HW_YR_LIMIT 99
134 +
135 +/* The highest value for the valid tm_year */
136 +#define MTK_RTC_TM_YR_H (MTK_RTC_TM_YR_OFFSET + MTK_RTC_HW_YR_LIMIT)
137 +
138 +/* Simple macro helps to check whether the hardware supports the tm_year */
139 +#define MTK_RTC_TM_YR_VALID(_y) ((_y) >= MTK_RTC_TM_YR_L && \
140 + (_y) <= MTK_RTC_TM_YR_H)
141 +
142 +/* Types of the function the RTC provides are time counter and alarm. */
143 +enum {
144 + MTK_TC,
145 + MTK_AL,
146 +};
147 +
148 +/* Indexes are used for the pointer to relevant registers in MTK_RTC_TREG */
149 +enum {
150 + MTK_YEA,
151 + MTK_MON,
152 + MTK_DOM,
153 + MTK_DOW,
154 + MTK_HOU,
155 + MTK_MIN,
156 + MTK_SEC
157 +};
158 +
159 +struct mtk_rtc {
160 + struct rtc_device *rtc;
161 + void __iomem *base;
162 + int irq;
163 + struct clk *clk;
164 +};
165 +
166 +static void mtk_w32(struct mtk_rtc *rtc, u32 reg, u32 val)
167 +{
168 + writel_relaxed(val, rtc->base + reg);
169 +}
170 +
171 +static u32 mtk_r32(struct mtk_rtc *rtc, u32 reg)
172 +{
173 + return readl_relaxed(rtc->base + reg);
174 +}
175 +
176 +static void mtk_rmw(struct mtk_rtc *rtc, u32 reg, u32 mask, u32 set)
177 +{
178 + u32 val;
179 +
180 + val = mtk_r32(rtc, reg);
181 + val &= ~mask;
182 + val |= set;
183 + mtk_w32(rtc, reg, val);
184 +}
185 +
186 +static void mtk_set(struct mtk_rtc *rtc, u32 reg, u32 val)
187 +{
188 + mtk_rmw(rtc, reg, 0, val);
189 +}
190 +
191 +static void mtk_clr(struct mtk_rtc *rtc, u32 reg, u32 val)
192 +{
193 + mtk_rmw(rtc, reg, val, 0);
194 +}
195 +
196 +static void mtk_rtc_hw_init(struct mtk_rtc *hw)
197 +{
198 + /* The setup of the init sequence is for allowing RTC got to work */
199 + mtk_w32(hw, MTK_RTC_PWRCHK1, RTC_PWRCHK1_MAGIC);
200 + mtk_w32(hw, MTK_RTC_PWRCHK2, RTC_PWRCHK2_MAGIC);
201 + mtk_w32(hw, MTK_RTC_KEY, RTC_KEY_MAGIC);
202 + mtk_w32(hw, MTK_RTC_PROT1, RTC_PROT1_MAGIC);
203 + mtk_w32(hw, MTK_RTC_PROT2, RTC_PROT2_MAGIC);
204 + mtk_w32(hw, MTK_RTC_PROT3, RTC_PROT3_MAGIC);
205 + mtk_w32(hw, MTK_RTC_PROT4, RTC_PROT4_MAGIC);
206 + mtk_rmw(hw, MTK_RTC_DEBNCE, RTC_DEBNCE_MASK, 0);
207 + mtk_clr(hw, MTK_RTC_CTL, RTC_RC_STOP);
208 +}
209 +
210 +static void mtk_rtc_get_alarm_or_time(struct mtk_rtc *hw, struct rtc_time *tm,
211 + int time_alarm)
212 +{
213 + u32 year, mon, mday, wday, hour, min, sec;
214 +
215 + /*
216 + * Read again until the field of the second is not changed which
217 + * ensures all fields in the consistent state. Note that MTK_SEC must
218 + * be read first. In this way, it guarantees the others remain not
219 + * changed when the results for two MTK_SEC consecutive reads are same.
220 + */
221 + do {
222 + sec = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_SEC));
223 + min = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_MIN));
224 + hour = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_HOU));
225 + wday = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_DOW));
226 + mday = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_DOM));
227 + mon = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_MON));
228 + year = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_YEA));
229 + } while (sec != mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_SEC)));
230 +
231 + tm->tm_sec = sec;
232 + tm->tm_min = min;
233 + tm->tm_hour = hour;
234 + tm->tm_wday = wday;
235 + tm->tm_mday = mday;
236 + tm->tm_mon = mon - 1;
237 +
238 + /* Rebase to the absolute year which userspace queries */
239 + tm->tm_year = year + MTK_RTC_TM_YR_OFFSET;
240 +}
241 +
242 +static void mtk_rtc_set_alarm_or_time(struct mtk_rtc *hw, struct rtc_time *tm,
243 + int time_alarm)
244 +{
245 + u32 year;
246 +
247 + /* Rebase to the relative year which RTC hardware requires */
248 + year = tm->tm_year - MTK_RTC_TM_YR_OFFSET;
249 +
250 + mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_YEA), year);
251 + mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_MON), tm->tm_mon + 1);
252 + mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_DOW), tm->tm_wday);
253 + mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_DOM), tm->tm_mday);
254 + mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_HOU), tm->tm_hour);
255 + mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_MIN), tm->tm_min);
256 + mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_SEC), tm->tm_sec);
257 +}
258 +
259 +static irqreturn_t mtk_rtc_alarmirq(int irq, void *id)
260 +{
261 + struct mtk_rtc *hw = (struct mtk_rtc *)id;
262 + u32 irq_sta;
263 +
264 + irq_sta = mtk_r32(hw, MTK_RTC_INT);
265 + if (irq_sta & RTC_INT_AL_STA) {
266 + /* Stop alarm also implicitly disables the alarm interrupt */
267 + mtk_w32(hw, MTK_RTC_AL_CTL, 0);
268 + rtc_update_irq(hw->rtc, 1, RTC_IRQF | RTC_AF);
269 +
270 + /* Ack alarm interrupt status */
271 + mtk_w32(hw, MTK_RTC_INT, RTC_INT_AL_STA);
272 + return IRQ_HANDLED;
273 + }
274 +
275 + return IRQ_NONE;
276 +}
277 +
278 +static int mtk_rtc_gettime(struct device *dev, struct rtc_time *tm)
279 +{
280 + struct mtk_rtc *hw = dev_get_drvdata(dev);
281 +
282 + mtk_rtc_get_alarm_or_time(hw, tm, MTK_TC);
283 +
284 + return rtc_valid_tm(tm);
285 +}
286 +
287 +static int mtk_rtc_settime(struct device *dev, struct rtc_time *tm)
288 +{
289 + struct mtk_rtc *hw = dev_get_drvdata(dev);
290 +
291 + if (!MTK_RTC_TM_YR_VALID(tm->tm_year))
292 + return -EINVAL;
293 +
294 + /* Stop time counter before setting a new one*/
295 + mtk_set(hw, MTK_RTC_CTL, RTC_RC_STOP);
296 +
297 + mtk_rtc_set_alarm_or_time(hw, tm, MTK_TC);
298 +
299 + /* Restart the time counter */
300 + mtk_clr(hw, MTK_RTC_CTL, RTC_RC_STOP);
301 +
302 + return 0;
303 +}
304 +
305 +static int mtk_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
306 +{
307 + struct mtk_rtc *hw = dev_get_drvdata(dev);
308 + struct rtc_time *alrm_tm = &wkalrm->time;
309 +
310 + mtk_rtc_get_alarm_or_time(hw, alrm_tm, MTK_AL);
311 +
312 + wkalrm->enabled = !!(mtk_r32(hw, MTK_RTC_AL_CTL) & RTC_AL_EN);
313 + wkalrm->pending = !!(mtk_r32(hw, MTK_RTC_INT) & RTC_INT_AL_STA);
314 +
315 + return 0;
316 +}
317 +
318 +static int mtk_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
319 +{
320 + struct mtk_rtc *hw = dev_get_drvdata(dev);
321 + struct rtc_time *alrm_tm = &wkalrm->time;
322 +
323 + if (!MTK_RTC_TM_YR_VALID(alrm_tm->tm_year))
324 + return -EINVAL;
325 +
326 + /*
327 + * Stop the alarm also implicitly including disables interrupt before
328 + * setting a new one.
329 + */
330 + mtk_clr(hw, MTK_RTC_AL_CTL, RTC_AL_EN);
331 +
332 + /*
333 + * Avoid contention between mtk_rtc_setalarm and IRQ handler so that
334 + * disabling the interrupt and awaiting for pending IRQ handler to
335 + * complete.
336 + */
337 + synchronize_irq(hw->irq);
338 +
339 + mtk_rtc_set_alarm_or_time(hw, alrm_tm, MTK_AL);
340 +
341 + /* Restart the alarm with the new setup */
342 + mtk_w32(hw, MTK_RTC_AL_CTL, RTC_AL_ALL);
343 +
344 + return 0;
345 +}
346 +
347 +static const struct rtc_class_ops mtk_rtc_ops = {
348 + .read_time = mtk_rtc_gettime,
349 + .set_time = mtk_rtc_settime,
350 + .read_alarm = mtk_rtc_getalarm,
351 + .set_alarm = mtk_rtc_setalarm,
352 +};
353 +
354 +static const struct of_device_id mtk_rtc_match[] = {
355 + { .compatible = "mediatek,mt7622-rtc" },
356 + { .compatible = "mediatek,soc-rtc" },
357 + {},
358 +};
359 +
360 +static int mtk_rtc_probe(struct platform_device *pdev)
361 +{
362 + struct mtk_rtc *hw;
363 + struct resource *res;
364 + int ret;
365 +
366 + hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL);
367 + if (!hw)
368 + return -ENOMEM;
369 +
370 + platform_set_drvdata(pdev, hw);
371 +
372 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
373 + hw->base = devm_ioremap_resource(&pdev->dev, res);
374 + if (IS_ERR(hw->base))
375 + return PTR_ERR(hw->base);
376 +
377 + hw->clk = devm_clk_get(&pdev->dev, "rtc");
378 + if (IS_ERR(hw->clk)) {
379 + dev_err(&pdev->dev, "No clock\n");
380 + return PTR_ERR(hw->clk);
381 + }
382 +
383 + ret = clk_prepare_enable(hw->clk);
384 + if (ret)
385 + return ret;
386 +
387 + hw->irq = platform_get_irq(pdev, 0);
388 + if (hw->irq < 0) {
389 + dev_err(&pdev->dev, "No IRQ resource\n");
390 + ret = hw->irq;
391 + goto err;
392 + }
393 +
394 + ret = devm_request_irq(&pdev->dev, hw->irq, mtk_rtc_alarmirq,
395 + 0, dev_name(&pdev->dev), hw);
396 + if (ret) {
397 + dev_err(&pdev->dev, "Can't request IRQ\n");
398 + goto err;
399 + }
400 +
401 + mtk_rtc_hw_init(hw);
402 +
403 + device_init_wakeup(&pdev->dev, true);
404 +
405 + hw->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
406 + &mtk_rtc_ops, THIS_MODULE);
407 + if (IS_ERR(hw->rtc)) {
408 + ret = PTR_ERR(hw->rtc);
409 + dev_err(&pdev->dev, "Unable to register device\n");
410 + goto err;
411 + }
412 +
413 + return 0;
414 +err:
415 + clk_disable_unprepare(hw->clk);
416 +
417 + return ret;
418 +}
419 +
420 +static int mtk_rtc_remove(struct platform_device *pdev)
421 +{
422 + struct mtk_rtc *hw = platform_get_drvdata(pdev);
423 +
424 + clk_disable_unprepare(hw->clk);
425 +
426 + return 0;
427 +}
428 +
429 +#ifdef CONFIG_PM_SLEEP
430 +static int mtk_rtc_suspend(struct device *dev)
431 +{
432 + struct mtk_rtc *hw = dev_get_drvdata(dev);
433 +
434 + if (device_may_wakeup(dev))
435 + enable_irq_wake(hw->irq);
436 +
437 + return 0;
438 +}
439 +
440 +static int mtk_rtc_resume(struct device *dev)
441 +{
442 + struct mtk_rtc *hw = dev_get_drvdata(dev);
443 +
444 + if (device_may_wakeup(dev))
445 + disable_irq_wake(hw->irq);
446 +
447 + return 0;
448 +}
449 +
450 +static SIMPLE_DEV_PM_OPS(mtk_rtc_pm_ops, mtk_rtc_suspend, mtk_rtc_resume);
451 +
452 +#define MTK_RTC_PM_OPS (&mtk_rtc_pm_ops)
453 +#else /* CONFIG_PM */
454 +#define MTK_RTC_PM_OPS NULL
455 +#endif /* CONFIG_PM */
456 +
457 +static struct platform_driver mtk_rtc_driver = {
458 + .probe = mtk_rtc_probe,
459 + .remove = mtk_rtc_remove,
460 + .driver = {
461 + .name = MTK_RTC_DEV,
462 + .of_match_table = mtk_rtc_match,
463 + .pm = MTK_RTC_PM_OPS,
464 + },
465 +};
466 +
467 +module_platform_driver(mtk_rtc_driver);
468 +
469 +MODULE_DESCRIPTION("MediaTek SoC based RTC Driver");
470 +MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
471 +MODULE_LICENSE("GPL");