mediatek: backport upstream mediatek patches
[openwrt/openwrt.git] / target / linux / mediatek / patches-4.14 / 0143-mmc-mediatek-add-support-of-mt2701-mt2712.patch
1 From 8119f3e147deaf97a66e953fecf3d2b0edbb07fd Mon Sep 17 00:00:00 2001
2 From: Chaotian Jing <chaotian.jing@mediatek.com>
3 Date: Mon, 16 Oct 2017 09:46:29 +0800
4 Subject: [PATCH 143/224] mmc: mediatek: add support of mt2701/mt2712
5
6 mt2701/mt2712 has 12bit clock div, which is not compatible with
7 mt8135/mt8173. and, some additional features will be added in
8 mt2701/mt2712, so that need distinguish it by comatibale name.
9
10 Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
11 Tested-by: Sean Wang <sean.wang@mediatek.com>
12 Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
13 ---
14 drivers/mmc/host/mtk-sd.c | 82 +++++++++++++++++++++++++++++++++++++++--------
15 1 file changed, 69 insertions(+), 13 deletions(-)
16
17 diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
18 index 267f7ab08420..643c795f1bdd 100644
19 --- a/drivers/mmc/host/mtk-sd.c
20 +++ b/drivers/mmc/host/mtk-sd.c
21 @@ -95,6 +95,9 @@
22 #define MSDC_CFG_CKDIV (0xff << 8) /* RW */
23 #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */
24 #define MSDC_CFG_HS400_CK_MODE (0x1 << 18) /* RW */
25 +#define MSDC_CFG_HS400_CK_MODE_EXTRA (0x1 << 22) /* RW */
26 +#define MSDC_CFG_CKDIV_EXTRA (0xfff << 8) /* RW */
27 +#define MSDC_CFG_CKMOD_EXTRA (0x3 << 20) /* RW */
28
29 /* MSDC_IOCON mask */
30 #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */
31 @@ -295,6 +298,10 @@ struct msdc_save_para {
32 u32 emmc50_cfg0;
33 };
34
35 +struct mtk_mmc_compatible {
36 + u8 clk_div_bits;
37 +};
38 +
39 struct msdc_tune_para {
40 u32 iocon;
41 u32 pad_tune;
42 @@ -309,6 +316,7 @@ struct msdc_delay_phase {
43
44 struct msdc_host {
45 struct device *dev;
46 + const struct mtk_mmc_compatible *dev_comp;
47 struct mmc_host *mmc; /* mmc structure */
48 int cmd_rsp;
49
50 @@ -350,6 +358,31 @@ struct msdc_host {
51 struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
52 };
53
54 +static const struct mtk_mmc_compatible mt8135_compat = {
55 + .clk_div_bits = 8,
56 +};
57 +
58 +static const struct mtk_mmc_compatible mt8173_compat = {
59 + .clk_div_bits = 8,
60 +};
61 +
62 +static const struct mtk_mmc_compatible mt2701_compat = {
63 + .clk_div_bits = 12,
64 +};
65 +
66 +static const struct mtk_mmc_compatible mt2712_compat = {
67 + .clk_div_bits = 12,
68 +};
69 +
70 +static const struct of_device_id msdc_of_ids[] = {
71 + { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
72 + { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
73 + { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
74 + { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
75 + {}
76 +};
77 +MODULE_DEVICE_TABLE(of, msdc_of_ids);
78 +
79 static void sdr_set_bits(void __iomem *reg, u32 bs)
80 {
81 u32 val = readl(reg);
82 @@ -509,7 +542,12 @@ static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
83 timeout = (ns + clk_ns - 1) / clk_ns + clks;
84 /* in 1048576 sclk cycle unit */
85 timeout = (timeout + (0x1 << 20) - 1) >> 20;
86 - sdr_get_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD, &mode);
87 + if (host->dev_comp->clk_div_bits == 8)
88 + sdr_get_field(host->base + MSDC_CFG,
89 + MSDC_CFG_CKMOD, &mode);
90 + else
91 + sdr_get_field(host->base + MSDC_CFG,
92 + MSDC_CFG_CKMOD_EXTRA, &mode);
93 /*DDR mode will double the clk cycles for data timeout */
94 timeout = mode >= 2 ? timeout * 2 : timeout;
95 timeout = timeout > 1 ? timeout - 1 : 0;
96 @@ -548,7 +586,11 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
97
98 flags = readl(host->base + MSDC_INTEN);
99 sdr_clr_bits(host->base + MSDC_INTEN, flags);
100 - sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
101 + if (host->dev_comp->clk_div_bits == 8)
102 + sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
103 + else
104 + sdr_clr_bits(host->base + MSDC_CFG,
105 + MSDC_CFG_HS400_CK_MODE_EXTRA);
106 if (timing == MMC_TIMING_UHS_DDR50 ||
107 timing == MMC_TIMING_MMC_DDR52 ||
108 timing == MMC_TIMING_MMC_HS400) {
109 @@ -568,8 +610,12 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
110
111 if (timing == MMC_TIMING_MMC_HS400 &&
112 hz >= (host->src_clk_freq >> 1)) {
113 - sdr_set_bits(host->base + MSDC_CFG,
114 - MSDC_CFG_HS400_CK_MODE);
115 + if (host->dev_comp->clk_div_bits == 8)
116 + sdr_set_bits(host->base + MSDC_CFG,
117 + MSDC_CFG_HS400_CK_MODE);
118 + else
119 + sdr_set_bits(host->base + MSDC_CFG,
120 + MSDC_CFG_HS400_CK_MODE_EXTRA);
121 sclk = host->src_clk_freq >> 1;
122 div = 0; /* div is ignore when bit18 is set */
123 }
124 @@ -587,8 +633,15 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
125 sclk = (host->src_clk_freq >> 2) / div;
126 }
127 }
128 - sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
129 - (mode << 8) | div);
130 + if (host->dev_comp->clk_div_bits == 8)
131 + sdr_set_field(host->base + MSDC_CFG,
132 + MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
133 + (mode << 8) | div);
134 + else
135 + sdr_set_field(host->base + MSDC_CFG,
136 + MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA,
137 + (mode << 12) | div);
138 +
139 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
140 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
141 cpu_relax();
142 @@ -1617,12 +1670,17 @@ static int msdc_drv_probe(struct platform_device *pdev)
143 struct mmc_host *mmc;
144 struct msdc_host *host;
145 struct resource *res;
146 + const struct of_device_id *of_id;
147 int ret;
148
149 if (!pdev->dev.of_node) {
150 dev_err(&pdev->dev, "No DT found\n");
151 return -EINVAL;
152 }
153 +
154 + of_id = of_match_node(msdc_of_ids, pdev->dev.of_node);
155 + if (!of_id)
156 + return -EINVAL;
157 /* Allocate MMC host for this device */
158 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
159 if (!mmc)
160 @@ -1686,11 +1744,15 @@ static int msdc_drv_probe(struct platform_device *pdev)
161 msdc_of_property_parse(pdev, host);
162
163 host->dev = &pdev->dev;
164 + host->dev_comp = of_id->data;
165 host->mmc = mmc;
166 host->src_clk_freq = clk_get_rate(host->src_clk);
167 /* Set host parameters to mmc */
168 mmc->ops = &mt_msdc_ops;
169 - mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
170 + if (host->dev_comp->clk_div_bits == 8)
171 + mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
172 + else
173 + mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095);
174
175 mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23;
176 /* MMC core transfer sizes tunable parameters */
177 @@ -1839,12 +1901,6 @@ static const struct dev_pm_ops msdc_dev_pm_ops = {
178 SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL)
179 };
180
181 -static const struct of_device_id msdc_of_ids[] = {
182 - { .compatible = "mediatek,mt8135-mmc", },
183 - {}
184 -};
185 -MODULE_DEVICE_TABLE(of, msdc_of_ids);
186 -
187 static struct platform_driver mt_msdc_driver = {
188 .probe = msdc_drv_probe,
189 .remove = msdc_drv_remove,
190 --
191 2.11.0
192