kernel: bump 4.14 to 4.14.161
[openwrt/openwrt.git] / target / linux / mediatek / patches-4.14 / 0153-mmc-mediatek-add-pad_tune0-support.patch
1 From a10349f1710a11239c58da3a7e5b353c6b2070c2 Mon Sep 17 00:00:00 2001
2 From: Chaotian Jing <chaotian.jing@mediatek.com>
3 Date: Mon, 16 Oct 2017 09:46:32 +0800
4 Subject: [PATCH 153/224] mmc: mediatek: add pad_tune0 support
5
6 from mt2701, the register of PAD_TUNE has been phased out,
7 while there is a new register of PAD_TUNE0
8
9 Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
10 Tested-by: Sean Wang <sean.wang@mediatek.com>
11 Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
12 ---
13 drivers/mmc/host/mtk-sd.c | 51 ++++++++++++++++++++++++++++++-----------------
14 1 file changed, 33 insertions(+), 18 deletions(-)
15
16 --- a/drivers/mmc/host/mtk-sd.c
17 +++ b/drivers/mmc/host/mtk-sd.c
18 @@ -75,6 +75,7 @@
19 #define MSDC_PATCH_BIT 0xb0
20 #define MSDC_PATCH_BIT1 0xb4
21 #define MSDC_PAD_TUNE 0xec
22 +#define MSDC_PAD_TUNE0 0xf0
23 #define PAD_DS_TUNE 0x188
24 #define PAD_CMD_TUNE 0x18c
25 #define EMMC50_CFG0 0x208
26 @@ -303,6 +304,7 @@ struct msdc_save_para {
27 struct mtk_mmc_compatible {
28 u8 clk_div_bits;
29 bool hs400_tune; /* only used for MT8173 */
30 + u32 pad_tune_reg;
31 };
32
33 struct msdc_tune_para {
34 @@ -364,21 +366,25 @@ struct msdc_host {
35 static const struct mtk_mmc_compatible mt8135_compat = {
36 .clk_div_bits = 8,
37 .hs400_tune = false,
38 + .pad_tune_reg = MSDC_PAD_TUNE,
39 };
40
41 static const struct mtk_mmc_compatible mt8173_compat = {
42 .clk_div_bits = 8,
43 .hs400_tune = true,
44 + .pad_tune_reg = MSDC_PAD_TUNE,
45 };
46
47 static const struct mtk_mmc_compatible mt2701_compat = {
48 .clk_div_bits = 12,
49 .hs400_tune = false,
50 + .pad_tune_reg = MSDC_PAD_TUNE0,
51 };
52
53 static const struct mtk_mmc_compatible mt2712_compat = {
54 .clk_div_bits = 12,
55 .hs400_tune = false,
56 + .pad_tune_reg = MSDC_PAD_TUNE0,
57 };
58
59 static const struct of_device_id msdc_of_ids[] = {
60 @@ -583,6 +589,7 @@ static void msdc_set_mclk(struct msdc_ho
61 u32 flags;
62 u32 div;
63 u32 sclk;
64 + u32 tune_reg = host->dev_comp->pad_tune_reg;
65
66 if (!hz) {
67 dev_dbg(host->dev, "set mclk to 0\n");
68 @@ -665,10 +672,10 @@ static void msdc_set_mclk(struct msdc_ho
69 */
70 if (host->sclk <= 52000000) {
71 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
72 - writel(host->def_tune_para.pad_tune, host->base + MSDC_PAD_TUNE);
73 + writel(host->def_tune_para.pad_tune, host->base + tune_reg);
74 } else {
75 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON);
76 - writel(host->saved_tune_para.pad_tune, host->base + MSDC_PAD_TUNE);
77 + writel(host->saved_tune_para.pad_tune, host->base + tune_reg);
78 writel(host->saved_tune_para.pad_cmd_tune,
79 host->base + PAD_CMD_TUNE);
80 }
81 @@ -1226,6 +1233,7 @@ static irqreturn_t msdc_irq(int irq, voi
82 static void msdc_init_hw(struct msdc_host *host)
83 {
84 u32 val;
85 + u32 tune_reg = host->dev_comp->pad_tune_reg;
86
87 /* Configure to MMC/SD mode, clock free running */
88 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN);
89 @@ -1241,7 +1249,7 @@ static void msdc_init_hw(struct msdc_hos
90 val = readl(host->base + MSDC_INT);
91 writel(val, host->base + MSDC_INT);
92
93 - writel(0, host->base + MSDC_PAD_TUNE);
94 + writel(0, host->base + tune_reg);
95 writel(0, host->base + MSDC_IOCON);
96 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
97 writel(0x403c0046, host->base + MSDC_PATCH_BIT);
98 @@ -1261,7 +1269,7 @@ static void msdc_init_hw(struct msdc_hos
99 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
100
101 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
102 - host->def_tune_para.pad_tune = readl(host->base + MSDC_PAD_TUNE);
103 + host->def_tune_para.pad_tune = readl(host->base + tune_reg);
104 dev_dbg(host->dev, "init hardware done!");
105 }
106
107 @@ -1404,18 +1412,19 @@ static int msdc_tune_response(struct mmc
108 struct msdc_delay_phase internal_delay_phase;
109 u8 final_delay, final_maxlen;
110 u32 internal_delay = 0;
111 + u32 tune_reg = host->dev_comp->pad_tune_reg;
112 int cmd_err;
113 int i, j;
114
115 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
116 mmc->ios.timing == MMC_TIMING_UHS_SDR104)
117 - sdr_set_field(host->base + MSDC_PAD_TUNE,
118 + sdr_set_field(host->base + tune_reg,
119 MSDC_PAD_TUNE_CMDRRDLY,
120 host->hs200_cmd_int_delay);
121
122 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
123 for (i = 0 ; i < PAD_DELAY_MAX; i++) {
124 - sdr_set_field(host->base + MSDC_PAD_TUNE,
125 + sdr_set_field(host->base + tune_reg,
126 MSDC_PAD_TUNE_CMDRDLY, i);
127 /*
128 * Using the same parameters, it may sometimes pass the test,
129 @@ -1439,7 +1448,7 @@ static int msdc_tune_response(struct mmc
130
131 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
132 for (i = 0; i < PAD_DELAY_MAX; i++) {
133 - sdr_set_field(host->base + MSDC_PAD_TUNE,
134 + sdr_set_field(host->base + tune_reg,
135 MSDC_PAD_TUNE_CMDRDLY, i);
136 /*
137 * Using the same parameters, it may sometimes pass the test,
138 @@ -1464,12 +1473,12 @@ skip_fall:
139 final_maxlen = final_fall_delay.maxlen;
140 if (final_maxlen == final_rise_delay.maxlen) {
141 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
142 - sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRDLY,
143 + sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
144 final_rise_delay.final_phase);
145 final_delay = final_rise_delay.final_phase;
146 } else {
147 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
148 - sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRDLY,
149 + sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
150 final_fall_delay.final_phase);
151 final_delay = final_fall_delay.final_phase;
152 }
153 @@ -1477,7 +1486,7 @@ skip_fall:
154 goto skip_internal;
155
156 for (i = 0; i < PAD_DELAY_MAX; i++) {
157 - sdr_set_field(host->base + MSDC_PAD_TUNE,
158 + sdr_set_field(host->base + tune_reg,
159 MSDC_PAD_TUNE_CMDRRDLY, i);
160 mmc_send_tuning(mmc, opcode, &cmd_err);
161 if (!cmd_err)
162 @@ -1485,7 +1494,7 @@ skip_fall:
163 }
164 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay);
165 internal_delay_phase = get_best_delay(host, internal_delay);
166 - sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY,
167 + sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY,
168 internal_delay_phase.final_phase);
169 skip_internal:
170 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
171 @@ -1548,12 +1557,13 @@ static int msdc_tune_data(struct mmc_hos
172 u32 rise_delay = 0, fall_delay = 0;
173 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
174 u8 final_delay, final_maxlen;
175 + u32 tune_reg = host->dev_comp->pad_tune_reg;
176 int i, ret;
177
178 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
179 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
180 for (i = 0 ; i < PAD_DELAY_MAX; i++) {
181 - sdr_set_field(host->base + MSDC_PAD_TUNE,
182 + sdr_set_field(host->base + tune_reg,
183 MSDC_PAD_TUNE_DATRRDLY, i);
184 ret = mmc_send_tuning(mmc, opcode, NULL);
185 if (!ret)
186 @@ -1568,7 +1578,7 @@ static int msdc_tune_data(struct mmc_hos
187 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
188 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
189 for (i = 0; i < PAD_DELAY_MAX; i++) {
190 - sdr_set_field(host->base + MSDC_PAD_TUNE,
191 + sdr_set_field(host->base + tune_reg,
192 MSDC_PAD_TUNE_DATRRDLY, i);
193 ret = mmc_send_tuning(mmc, opcode, NULL);
194 if (!ret)
195 @@ -1581,14 +1591,14 @@ skip_fall:
196 if (final_maxlen == final_rise_delay.maxlen) {
197 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
198 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
199 - sdr_set_field(host->base + MSDC_PAD_TUNE,
200 + sdr_set_field(host->base + tune_reg,
201 MSDC_PAD_TUNE_DATRRDLY,
202 final_rise_delay.final_phase);
203 final_delay = final_rise_delay.final_phase;
204 } else {
205 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
206 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
207 - sdr_set_field(host->base + MSDC_PAD_TUNE,
208 + sdr_set_field(host->base + tune_reg,
209 MSDC_PAD_TUNE_DATRRDLY,
210 final_fall_delay.final_phase);
211 final_delay = final_fall_delay.final_phase;
212 @@ -1602,6 +1612,7 @@ static int msdc_execute_tuning(struct mm
213 {
214 struct msdc_host *host = mmc_priv(mmc);
215 int ret;
216 + u32 tune_reg = host->dev_comp->pad_tune_reg;
217
218 if (host->hs400_mode &&
219 host->dev_comp->hs400_tune)
220 @@ -1619,7 +1630,7 @@ static int msdc_execute_tuning(struct mm
221 }
222
223 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
224 - host->saved_tune_para.pad_tune = readl(host->base + MSDC_PAD_TUNE);
225 + host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
226 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
227 return ret;
228 }
229 @@ -1860,10 +1871,12 @@ static int msdc_drv_remove(struct platfo
230 #ifdef CONFIG_PM
231 static void msdc_save_reg(struct msdc_host *host)
232 {
233 + u32 tune_reg = host->dev_comp->pad_tune_reg;
234 +
235 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG);
236 host->save_para.iocon = readl(host->base + MSDC_IOCON);
237 host->save_para.sdc_cfg = readl(host->base + SDC_CFG);
238 - host->save_para.pad_tune = readl(host->base + MSDC_PAD_TUNE);
239 + host->save_para.pad_tune = readl(host->base + tune_reg);
240 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
241 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
242 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
243 @@ -1873,10 +1886,12 @@ static void msdc_save_reg(struct msdc_ho
244
245 static void msdc_restore_reg(struct msdc_host *host)
246 {
247 + u32 tune_reg = host->dev_comp->pad_tune_reg;
248 +
249 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
250 writel(host->save_para.iocon, host->base + MSDC_IOCON);
251 writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
252 - writel(host->save_para.pad_tune, host->base + MSDC_PAD_TUNE);
253 + writel(host->save_para.pad_tune, host->base + tune_reg);
254 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
255 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
256 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);