abb263b7129f54ec4fa7a59201137687f80807eb
[openwrt/openwrt.git] / target / linux / mediatek / patches-4.14 / 0154-mmc-mediatek-add-async-fifo-and-data-tune-support.patch
1 From 830574225e621809600902b69bbdd563e67ef4eb Mon Sep 17 00:00:00 2001
2 From: Chaotian Jing <chaotian.jing@mediatek.com>
3 Date: Mon, 16 Oct 2017 09:46:33 +0800
4 Subject: [PATCH 154/224] mmc: mediatek: add async fifo and data tune support
5
6 mt2701/mt2712 supports async fifo & data tune, which can improve
7 host stability.
8
9 Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
10 Tested-by: Sean Wang <sean.wang@mediatek.com>
11 Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
12 ---
13 drivers/mmc/host/mtk-sd.c | 52 +++++++++++++++++++++++++++++++++++++++++++++--
14 1 file changed, 50 insertions(+), 2 deletions(-)
15
16 --- a/drivers/mmc/host/mtk-sd.c
17 +++ b/drivers/mmc/host/mtk-sd.c
18 @@ -74,6 +74,7 @@
19 #define MSDC_DMA_CFG 0x9c
20 #define MSDC_PATCH_BIT 0xb0
21 #define MSDC_PATCH_BIT1 0xb4
22 +#define MSDC_PATCH_BIT2 0xb8
23 #define MSDC_PAD_TUNE 0xec
24 #define MSDC_PAD_TUNE0 0xf0
25 #define PAD_DS_TUNE 0x188
26 @@ -216,11 +217,20 @@
27 #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */
28 #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */
29
30 +#define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */
31 +#define MSDC_PATCH_BIT2_CFGCRCSTS (0x1 << 28) /* RW */
32 +#define MSDC_PB2_RESPWAIT (0x3 << 2) /* RW */
33 +#define MSDC_PB2_RESPSTSENSEL (0x7 << 16) /* RW */
34 +#define MSDC_PB2_CRCSTSENSEL (0x7 << 29) /* RW */
35 +
36 #define MSDC_PAD_TUNE_DATWRDLY (0x1f << 0) /* RW */
37 #define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */
38 #define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */
39 #define MSDC_PAD_TUNE_CMDRRDLY (0x1f << 22) /* RW */
40 #define MSDC_PAD_TUNE_CLKTDLY (0x1f << 27) /* RW */
41 +#define MSDC_PAD_TUNE_RXDLYSEL (0x1 << 15) /* RW */
42 +#define MSDC_PAD_TUNE_RD_SEL (0x1 << 13) /* RW */
43 +#define MSDC_PAD_TUNE_CMD_SEL (0x1 << 21) /* RW */
44
45 #define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */
46 #define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */
47 @@ -294,6 +304,7 @@ struct msdc_save_para {
48 u32 pad_tune;
49 u32 patch_bit0;
50 u32 patch_bit1;
51 + u32 patch_bit2;
52 u32 pad_ds_tune;
53 u32 pad_cmd_tune;
54 u32 emmc50_cfg0;
55 @@ -303,6 +314,8 @@ struct mtk_mmc_compatible {
56 u8 clk_div_bits;
57 bool hs400_tune; /* only used for MT8173 */
58 u32 pad_tune_reg;
59 + bool async_fifo;
60 + bool data_tune;
61 };
62
63 struct msdc_tune_para {
64 @@ -365,24 +378,32 @@ static const struct mtk_mmc_compatible m
65 .clk_div_bits = 8,
66 .hs400_tune = false,
67 .pad_tune_reg = MSDC_PAD_TUNE,
68 + .async_fifo = false,
69 + .data_tune = false,
70 };
71
72 static const struct mtk_mmc_compatible mt8173_compat = {
73 .clk_div_bits = 8,
74 .hs400_tune = true,
75 .pad_tune_reg = MSDC_PAD_TUNE,
76 + .async_fifo = false,
77 + .data_tune = false,
78 };
79
80 static const struct mtk_mmc_compatible mt2701_compat = {
81 .clk_div_bits = 12,
82 .hs400_tune = false,
83 .pad_tune_reg = MSDC_PAD_TUNE0,
84 + .async_fifo = true,
85 + .data_tune = true,
86 };
87
88 static const struct mtk_mmc_compatible mt2712_compat = {
89 .clk_div_bits = 12,
90 .hs400_tune = false,
91 .pad_tune_reg = MSDC_PAD_TUNE0,
92 + .async_fifo = true,
93 + .data_tune = true,
94 };
95
96 static const struct of_device_id msdc_of_ids[] = {
97 @@ -1252,8 +1273,29 @@ static void msdc_init_hw(struct msdc_hos
98 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
99 writel(0x403c0046, host->base + MSDC_PATCH_BIT);
100 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
101 - writel(0xffff0089, host->base + MSDC_PATCH_BIT1);
102 + writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
103 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
104 + if (host->dev_comp->async_fifo) {
105 + sdr_set_field(host->base + MSDC_PATCH_BIT2,
106 + MSDC_PB2_RESPWAIT, 3);
107 + sdr_set_field(host->base + MSDC_PATCH_BIT2,
108 + MSDC_PB2_RESPSTSENSEL, 2);
109 + sdr_set_field(host->base + MSDC_PATCH_BIT2,
110 + MSDC_PB2_CRCSTSENSEL, 2);
111 + /* use async fifo, then no need tune internal delay */
112 + sdr_clr_bits(host->base + MSDC_PATCH_BIT2,
113 + MSDC_PATCH_BIT2_CFGRESP);
114 + sdr_set_bits(host->base + MSDC_PATCH_BIT2,
115 + MSDC_PATCH_BIT2_CFGCRCSTS);
116 + }
117 +
118 + if (host->dev_comp->data_tune) {
119 + sdr_set_bits(host->base + tune_reg,
120 + MSDC_PAD_TUNE_RD_SEL | MSDC_PAD_TUNE_CMD_SEL);
121 + } else {
122 + /* choose clock tune */
123 + sdr_set_bits(host->base + tune_reg, MSDC_PAD_TUNE_RXDLYSEL);
124 + }
125
126 /* Configure to enable SDIO mode.
127 * it's must otherwise sdio cmd5 failed
128 @@ -1268,6 +1310,8 @@ static void msdc_init_hw(struct msdc_hos
129
130 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
131 host->def_tune_para.pad_tune = readl(host->base + tune_reg);
132 + host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
133 + host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
134 dev_dbg(host->dev, "init hardware done!");
135 }
136
137 @@ -1480,7 +1524,7 @@ skip_fall:
138 final_fall_delay.final_phase);
139 final_delay = final_fall_delay.final_phase;
140 }
141 - if (host->hs200_cmd_int_delay)
142 + if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
143 goto skip_internal;
144
145 for (i = 0; i < PAD_DELAY_MAX; i++) {
146 @@ -1638,6 +1682,8 @@ static int msdc_prepare_hs400_tuning(str
147 host->hs400_mode = true;
148
149 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
150 + /* hs400 mode must set it to 0 */
151 + sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS);
152 return 0;
153 }
154
155 @@ -1876,6 +1922,7 @@ static void msdc_save_reg(struct msdc_ho
156 host->save_para.pad_tune = readl(host->base + tune_reg);
157 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
158 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
159 + host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2);
160 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
161 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
162 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
163 @@ -1891,6 +1938,7 @@ static void msdc_restore_reg(struct msdc
164 writel(host->save_para.pad_tune, host->base + tune_reg);
165 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
166 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
167 + writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2);
168 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
169 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
170 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);