kernel: bump 4.14 to 4.14.161
[openwrt/openwrt.git] / target / linux / mediatek / patches-4.14 / 0156-mmc-mediatek-add-stop_clk-fix-and-enhance_rx-support.patch
1 From 9257240bcaf8f9ee6878357e00e7ab511ad6d325 Mon Sep 17 00:00:00 2001
2 From: Chaotian Jing <chaotian.jing@mediatek.com>
3 Date: Mon, 16 Oct 2017 09:46:35 +0800
4 Subject: [PATCH 156/224] mmc: mediatek: add stop_clk fix and enhance_rx
5 support
6
7 mt2712 supports stop_clk fix and enhance_rx, which can improve
8 host stability.
9
10 Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
11 Tested-by: Sean Wang <sean.wang@mediatek.com>
12 Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
13 ---
14 drivers/mmc/host/mtk-sd.c | 47 +++++++++++++++++++++++++++++++++++++++++++----
15 1 file changed, 43 insertions(+), 4 deletions(-)
16
17 --- a/drivers/mmc/host/mtk-sd.c
18 +++ b/drivers/mmc/host/mtk-sd.c
19 @@ -67,6 +67,7 @@
20 #define SDC_RESP2 0x48
21 #define SDC_RESP3 0x4c
22 #define SDC_BLK_NUM 0x50
23 +#define SDC_ADV_CFG0 0x64
24 #define EMMC_IOCON 0x7c
25 #define SDC_ACMD_RESP 0x80
26 #define MSDC_DMA_SA 0x90
27 @@ -80,6 +81,7 @@
28 #define PAD_DS_TUNE 0x188
29 #define PAD_CMD_TUNE 0x18c
30 #define EMMC50_CFG0 0x208
31 +#define SDC_FIFO_CFG 0x228
32
33 /*--------------------------------------------------------------------------*/
34 /* Register Mask */
35 @@ -188,6 +190,9 @@
36 #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */
37 #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */
38
39 +/* SDC_ADV_CFG0 mask */
40 +#define SDC_RX_ENHANCE_EN (0x1 << 20) /* RW */
41 +
42 /* MSDC_DMA_CTRL mask */
43 #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */
44 #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */
45 @@ -219,6 +224,8 @@
46
47 #define MSDC_PATCH_BIT1_CMDTA (0x7 << 3) /* RW */
48
49 +#define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */
50 +
51 #define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */
52 #define MSDC_PATCH_BIT2_CFGCRCSTS (0x1 << 28) /* RW */
53 #define MSDC_PB2_RESPWAIT (0x3 << 2) /* RW */
54 @@ -244,6 +251,9 @@
55 #define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */
56 #define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */
57
58 +#define SDC_FIFO_CFG_WRVALIDSEL (0x1 << 24) /* RW */
59 +#define SDC_FIFO_CFG_RDVALIDSEL (0x1 << 25) /* RW */
60 +
61 #define REQ_CMD_EIO (0x1 << 0)
62 #define REQ_CMD_TMO (0x1 << 1)
63 #define REQ_DAT_ERR (0x1 << 2)
64 @@ -310,6 +320,7 @@ struct msdc_save_para {
65 u32 pad_ds_tune;
66 u32 pad_cmd_tune;
67 u32 emmc50_cfg0;
68 + u32 sdc_fifo_cfg;
69 };
70
71 struct mtk_mmc_compatible {
72 @@ -319,6 +330,8 @@ struct mtk_mmc_compatible {
73 bool async_fifo;
74 bool data_tune;
75 bool busy_check;
76 + bool stop_clk_fix;
77 + bool enhance_rx;
78 };
79
80 struct msdc_tune_para {
81 @@ -384,6 +397,8 @@ static const struct mtk_mmc_compatible m
82 .async_fifo = false,
83 .data_tune = false,
84 .busy_check = false,
85 + .stop_clk_fix = false,
86 + .enhance_rx = false,
87 };
88
89 static const struct mtk_mmc_compatible mt8173_compat = {
90 @@ -393,6 +408,8 @@ static const struct mtk_mmc_compatible m
91 .async_fifo = false,
92 .data_tune = false,
93 .busy_check = false,
94 + .stop_clk_fix = false,
95 + .enhance_rx = false,
96 };
97
98 static const struct mtk_mmc_compatible mt2701_compat = {
99 @@ -402,6 +419,8 @@ static const struct mtk_mmc_compatible m
100 .async_fifo = true,
101 .data_tune = true,
102 .busy_check = false,
103 + .stop_clk_fix = false,
104 + .enhance_rx = false,
105 };
106
107 static const struct mtk_mmc_compatible mt2712_compat = {
108 @@ -411,6 +430,8 @@ static const struct mtk_mmc_compatible m
109 .async_fifo = true,
110 .data_tune = true,
111 .busy_check = true,
112 + .stop_clk_fix = true,
113 + .enhance_rx = true,
114 };
115
116 static const struct of_device_id msdc_of_ids[] = {
117 @@ -1282,15 +1303,31 @@ static void msdc_init_hw(struct msdc_hos
118 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
119 writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
120 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
121 +
122 + if (host->dev_comp->stop_clk_fix) {
123 + sdr_set_field(host->base + MSDC_PATCH_BIT1,
124 + MSDC_PATCH_BIT1_STOP_DLY, 3);
125 + sdr_clr_bits(host->base + SDC_FIFO_CFG,
126 + SDC_FIFO_CFG_WRVALIDSEL);
127 + sdr_clr_bits(host->base + SDC_FIFO_CFG,
128 + SDC_FIFO_CFG_RDVALIDSEL);
129 + }
130 +
131 if (host->dev_comp->busy_check)
132 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7));
133 +
134 if (host->dev_comp->async_fifo) {
135 sdr_set_field(host->base + MSDC_PATCH_BIT2,
136 MSDC_PB2_RESPWAIT, 3);
137 - sdr_set_field(host->base + MSDC_PATCH_BIT2,
138 - MSDC_PB2_RESPSTSENSEL, 2);
139 - sdr_set_field(host->base + MSDC_PATCH_BIT2,
140 - MSDC_PB2_CRCSTSENSEL, 2);
141 + if (host->dev_comp->enhance_rx) {
142 + sdr_set_bits(host->base + SDC_ADV_CFG0,
143 + SDC_RX_ENHANCE_EN);
144 + } else {
145 + sdr_set_field(host->base + MSDC_PATCH_BIT2,
146 + MSDC_PB2_RESPSTSENSEL, 2);
147 + sdr_set_field(host->base + MSDC_PATCH_BIT2,
148 + MSDC_PB2_CRCSTSENSEL, 2);
149 + }
150 /* use async fifo, then no need tune internal delay */
151 sdr_clr_bits(host->base + MSDC_PATCH_BIT2,
152 MSDC_PATCH_BIT2_CFGRESP);
153 @@ -1936,6 +1973,7 @@ static void msdc_save_reg(struct msdc_ho
154 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
155 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
156 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
157 + host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG);
158 }
159
160 static void msdc_restore_reg(struct msdc_host *host)
161 @@ -1952,6 +1990,7 @@ static void msdc_restore_reg(struct msdc
162 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
163 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
164 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
165 + writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG);
166 }
167
168 static int msdc_runtime_suspend(struct device *dev)