target/linux/mediatek/patches-4.14/0159-mmc-mediatek-improve-eMMC-hs400-mode-read-performanc.patch

   1 From 29e154716049310bb8c559f742bf2b460d5b6bbc Mon Sep 17 00:00:00 2001
   2 From: Chaotian Jing <chaotian.jing@mediatek.com>
   3 Date: Mon, 16 Oct 2017 09:46:38 +0800
   4 Subject: [PATCH 159/224] mmc: mediatek: improve eMMC hs400 mode read
   5  performance
   6
   7 enlarge outstanding value to improve read performance
   8
   9 Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
  10 Tested-by: Sean Wang <sean.wang@mediatek.com>
  11 Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
  12 ---
  13  drivers/mmc/host/mtk-sd.c | 9 +++++++++
  14  1 file changed, 9 insertions(+)
  15
  16 --- a/drivers/mmc/host/mtk-sd.c
  17 +++ b/drivers/mmc/host/mtk-sd.c
  18 @@ -81,6 +81,7 @@
  19  #define PAD_DS_TUNE      0x188
  20  #define PAD_CMD_TUNE     0x18c
  21  #define EMMC50_CFG0      0x208
  22 +#define EMMC50_CFG3      0x220
  23  #define SDC_FIFO_CFG     0x228
  24
  25  /*--------------------------------------------------------------------------*/
  26 @@ -251,6 +252,8 @@
  27  #define EMMC50_CFG_CRCSTS_EDGE    (0x1 << 3)   /* RW */
  28  #define EMMC50_CFG_CFCSTS_SEL     (0x1 << 4)   /* RW */
  29
  30 +#define EMMC50_CFG3_OUTS_WR       (0x1f << 0)  /* RW */
  31 +
  32  #define SDC_FIFO_CFG_WRVALIDSEL   (0x1 << 24)  /* RW */
  33  #define SDC_FIFO_CFG_RDVALIDSEL   (0x1 << 25)  /* RW */
  34
  35 @@ -320,6 +323,7 @@ struct msdc_save_para {
  36         u32 pad_ds_tune;
  37         u32 pad_cmd_tune;
  38         u32 emmc50_cfg0;
  39 +       u32 emmc50_cfg3;
  40         u32 sdc_fifo_cfg;
  41  };
  42
  43 @@ -1750,6 +1754,9 @@ static int msdc_prepare_hs400_tuning(str
  44         writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
  45         /* hs400 mode must set it to 0 */
  46         sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS);
  47 +       /* to improve read performance, set outstanding to 2 */
  48 +       sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2);
  49 +
  50         return 0;
  51  }
  52
  53 @@ -2000,6 +2007,7 @@ static void msdc_save_reg(struct msdc_ho
  54         host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
  55         host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
  56         host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
  57 +       host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3);
  58         host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG);
  59  }
  60
  61 @@ -2017,6 +2025,7 @@ static void msdc_restore_reg(struct msdc
  62         writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
  63         writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
  64         writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
  65 +       writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3);
  66         writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG);
  67  }
  68