target/linux/mediatek/patches-4.14/0159-mmc-mediatek-improve-eMMC-hs400-mode-read-performanc.patch

   1 From 29e154716049310bb8c559f742bf2b460d5b6bbc Mon Sep 17 00:00:00 2001
   2 From: Chaotian Jing <chaotian.jing@mediatek.com>
   3 Date: Mon, 16 Oct 2017 09:46:38 +0800
   4 Subject: [PATCH 159/224] mmc: mediatek: improve eMMC hs400 mode read
   5  performance
   6
   7 enlarge outstanding value to improve read performance
   8
   9 Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
  10 Tested-by: Sean Wang <sean.wang@mediatek.com>
  11 Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
  12 ---
  13  drivers/mmc/host/mtk-sd.c | 9 +++++++++
  14  1 file changed, 9 insertions(+)
  15
  16 diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
  17 index d75a93d6803f..95759bba0dd0 100644
  18 --- a/drivers/mmc/host/mtk-sd.c
  19 +++ b/drivers/mmc/host/mtk-sd.c
  20 @@ -81,6 +81,7 @@
  21  #define PAD_DS_TUNE      0x188
  22  #define PAD_CMD_TUNE     0x18c
  23  #define EMMC50_CFG0      0x208
  24 +#define EMMC50_CFG3      0x220
  25  #define SDC_FIFO_CFG     0x228
  26
  27  /*--------------------------------------------------------------------------*/
  28 @@ -249,6 +250,8 @@
  29  #define EMMC50_CFG_CRCSTS_EDGE    (0x1 << 3)   /* RW */
  30  #define EMMC50_CFG_CFCSTS_SEL     (0x1 << 4)   /* RW */
  31
  32 +#define EMMC50_CFG3_OUTS_WR       (0x1f << 0)  /* RW */
  33 +
  34  #define SDC_FIFO_CFG_WRVALIDSEL   (0x1 << 24)  /* RW */
  35  #define SDC_FIFO_CFG_RDVALIDSEL   (0x1 << 25)  /* RW */
  36
  37 @@ -318,6 +321,7 @@ struct msdc_save_para {
  38         u32 pad_ds_tune;
  39         u32 pad_cmd_tune;
  40         u32 emmc50_cfg0;
  41 +       u32 emmc50_cfg3;
  42         u32 sdc_fifo_cfg;
  43  };
  44
  45 @@ -1747,6 +1751,9 @@ static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
  46         writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
  47         /* hs400 mode must set it to 0 */
  48         sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS);
  49 +       /* to improve read performance, set outstanding to 2 */
  50 +       sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2);
  51 +
  52         return 0;
  53  }
  54
  55 @@ -1997,6 +2004,7 @@ static void msdc_save_reg(struct msdc_host *host)
  56         host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
  57         host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
  58         host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
  59 +       host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3);
  60         host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG);
  61  }
  62
  63 @@ -2014,6 +2022,7 @@ static void msdc_restore_reg(struct msdc_host *host)
  64         writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
  65         writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
  66         writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
  67 +       writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3);
  68         writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG);
  69  }
  70
  71 --
  72 2.11.0
  73