target/linux/mediatek/patches-4.14/0175-net-mediatek-remove-superfluous-pin-setup-for-MT7622.patch

   1 From d96cf7e724105dc73f623c2019ab5bc78cef036e Mon Sep 17 00:00:00 2001
   2 From: Sean Wang <sean.wang@mediatek.com>
   3 Date: Wed, 20 Dec 2017 17:47:06 +0800
   4 Subject: [PATCH 175/224] net: mediatek: remove superfluous pin setup for
   5  MT7622 SoC
   6
   7 Remove superfluous pin setup to get out of accessing invalid I/O pin
   8 registers because the way for pin configuring tends to be different from
   9 various SoCs and thus it should be better being managed and controlled by
  10 the pinctrl driver which MT7622 already can support.
  11
  12 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
  13 Signed-off-by: David S. Miller <davem@davemloft.net>
  14 ---
  15  drivers/net/ethernet/mediatek/mtk_eth_soc.c | 35 +++++++++++++++++------------
  16  drivers/net/ethernet/mediatek/mtk_eth_soc.h |  3 +++
  17  2 files changed, 24 insertions(+), 14 deletions(-)
  18
  19 Index: linux-4.14.37/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  20 ===================================================================
  21 --- linux-4.14.37.orig/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  22 +++ linux-4.14.37/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  23 @@ -1976,14 +1976,16 @@ static int mtk_hw_init(struct mtk_eth *e
  24         }
  25         regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
  26
  27 -       /* Set GE2 driving and slew rate */
  28 -       regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
  29 +       if (eth->pctl) {
  30 +               /* Set GE2 driving and slew rate */
  31 +               regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
  32
  33 -       /* set GE2 TDSEL */
  34 -       regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
  35 +               /* set GE2 TDSEL */
  36 +               regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
  37
  38 -       /* set GE2 TUNE */
  39 -       regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
  40 +               /* set GE2 TUNE */
  41 +               regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
  42 +       }
  43
  44         /* Set linkdown as the default for each GMAC. Its own MCR would be set
  45          * up with the more appropriate value when mtk_phy_link_adjust call is
  46 @@ -2568,11 +2570,13 @@ static int mtk_probe(struct platform_dev
  47                 }
  48         }
  49
  50 -       eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
  51 -                                                   "mediatek,pctl");
  52 -       if (IS_ERR(eth->pctl)) {
  53 -               dev_err(&pdev->dev, "no pctl regmap found\n");
  54 -               return PTR_ERR(eth->pctl);
  55 +       if (eth->soc->required_pctl) {
  56 +               eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
  57 +                                                           "mediatek,pctl");
  58 +               if (IS_ERR(eth->pctl)) {
  59 +                       dev_err(&pdev->dev, "no pctl regmap found\n");
  60 +                       return PTR_ERR(eth->pctl);
  61 +               }
  62         }
  63
  64         for (i = 0; i < 3; i++) {
  65 @@ -2698,17 +2702,20 @@ static int mtk_remove(struct platform_de
  66
  67  static const struct mtk_soc_data mt2701_data = {
  68         .caps = MTK_GMAC1_TRGMII,
  69 -       .required_clks = MT7623_CLKS_BITMAP
  70 +       .required_clks = MT7623_CLKS_BITMAP,
  71 +       .required_pctl = true,
  72  };
  73
  74  static const struct mtk_soc_data mt7622_data = {
  75         .caps = MTK_DUAL_GMAC_SHARED_SGMII | MTK_GMAC1_ESW,
  76 -       .required_clks = MT7622_CLKS_BITMAP
  77 +       .required_clks = MT7622_CLKS_BITMAP,
  78 +       .required_pctl = false,
  79  };
  80
  81  static const struct mtk_soc_data mt7623_data = {
  82         .caps = MTK_GMAC1_TRGMII,
  83 -       .required_clks = MT7623_CLKS_BITMAP
  84 +       .required_clks = MT7623_CLKS_BITMAP,
  85 +       .required_pctl = true,
  86  };
  87
  88  const struct of_device_id of_mtk_match[] = {
  89 Index: linux-4.14.37/drivers/net/ethernet/mediatek/mtk_eth_soc.h
  90 ===================================================================
  91 --- linux-4.14.37.orig/drivers/net/ethernet/mediatek/mtk_eth_soc.h
  92 +++ linux-4.14.37/drivers/net/ethernet/mediatek/mtk_eth_soc.h
  93 @@ -574,10 +574,13 @@ struct mtk_rx_ring {
  94   * @caps                       Flags shown the extra capability for the SoC
  95   * @required_clks              Flags shown the bitmap for required clocks on
  96   *                             the target SoC
  97 + * @required_pctl              A bool value to show whether the SoC requires
  98 + *                             the extra setup for those pins used by GMAC.
  99   */
 100  struct mtk_soc_data {
 101         u32             caps;
 102         u32             required_clks;
 103 +       bool            required_pctl;
 104  };
 105
 106  /* currently no SoC has more than 2 macs */