mediatek: backport upstream mediatek patches
[openwrt/openwrt.git] / target / linux / mediatek / patches-4.14 / 0182-ASoC-mediatek-cleanup-audio-driver-for-MT2701.patch
1 From 4087c924ec899881951b2170a7bb8888747ec532 Mon Sep 17 00:00:00 2001
2 From: Ryder Lee <ryder.lee@mediatek.com>
3 Date: Tue, 2 Jan 2018 19:47:20 +0800
4 Subject: [PATCH 182/224] ASoC: mediatek: cleanup audio driver for MT2701
5
6 Cleanup unused code such as 'i2s_num' guard, headers, indentation
7 and some defines.
8
9 Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
10 Signed-off-by: Mark Brown <broonie@kernel.org>
11 ---
12 sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c | 14 +---
13 sound/soc/mediatek/mt2701/mt2701-afe-common.h | 20 +----
14 sound/soc/mediatek/mt2701/mt2701-afe-pcm.c | 94 ++++-------------------
15 sound/soc/mediatek/mt2701/mt2701-reg.h | 41 +---------
16 4 files changed, 24 insertions(+), 145 deletions(-)
17
18 diff --git a/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c b/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c
19 index 75ccdca5811d..56a057c78c9a 100644
20 --- a/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c
21 +++ b/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c
22 @@ -14,10 +14,6 @@
23 * GNU General Public License for more details.
24 */
25
26 -#include <sound/soc.h>
27 -#include <linux/regmap.h>
28 -#include <linux/pm_runtime.h>
29 -
30 #include "mt2701-afe-common.h"
31 #include "mt2701-afe-clock-ctrl.h"
32
33 @@ -223,8 +219,8 @@ int mt2701_afe_enable_clock(struct mtk_base_afe *afe)
34 }
35
36 regmap_update_bits(afe->regmap, ASYS_TOP_CON,
37 - AUDIO_TOP_CON0_A1SYS_A2SYS_ON,
38 - AUDIO_TOP_CON0_A1SYS_A2SYS_ON);
39 + ASYS_TOP_CON_ASYS_TIMING_ON,
40 + ASYS_TOP_CON_ASYS_TIMING_ON);
41 regmap_update_bits(afe->regmap, AFE_DAC_CON0,
42 AFE_DAC_CON0_AFE_ON,
43 AFE_DAC_CON0_AFE_ON);
44 @@ -239,7 +235,7 @@ int mt2701_afe_enable_clock(struct mtk_base_afe *afe)
45 int mt2701_afe_disable_clock(struct mtk_base_afe *afe)
46 {
47 regmap_update_bits(afe->regmap, ASYS_TOP_CON,
48 - AUDIO_TOP_CON0_A1SYS_A2SYS_ON, 0);
49 + ASYS_TOP_CON_ASYS_TIMING_ON, 0);
50 regmap_update_bits(afe->regmap, AFE_DAC_CON0,
51 AFE_DAC_CON0_AFE_ON, 0);
52
53 @@ -272,7 +268,3 @@ void mt2701_mclk_configuration(struct mtk_base_afe *afe, int id, int domain,
54 if (ret)
55 dev_err(afe->dev, "failed to set mclk divider %d\n", ret);
56 }
57 -
58 -MODULE_DESCRIPTION("MT2701 afe clock control");
59 -MODULE_AUTHOR("Garlic Tseng <garlic.tseng@mediatek.com>");
60 -MODULE_LICENSE("GPL v2");
61 diff --git a/sound/soc/mediatek/mt2701/mt2701-afe-common.h b/sound/soc/mediatek/mt2701/mt2701-afe-common.h
62 index ce5bd4dc864d..9a2b301a4c21 100644
63 --- a/sound/soc/mediatek/mt2701/mt2701-afe-common.h
64 +++ b/sound/soc/mediatek/mt2701/mt2701-afe-common.h
65 @@ -16,6 +16,7 @@
66
67 #ifndef _MT_2701_AFE_COMMON_H_
68 #define _MT_2701_AFE_COMMON_H_
69 +
70 #include <sound/soc.h>
71 #include <linux/clk.h>
72 #include <linux/regmap.h>
73 @@ -25,16 +26,7 @@
74 #define MT2701_STREAM_DIR_NUM (SNDRV_PCM_STREAM_LAST + 1)
75 #define MT2701_PLL_DOMAIN_0_RATE 98304000
76 #define MT2701_PLL_DOMAIN_1_RATE 90316800
77 -#define MT2701_AUD_AUD_MUX1_DIV_RATE (MT2701_PLL_DOMAIN_0_RATE / 2)
78 -#define MT2701_AUD_AUD_MUX2_DIV_RATE (MT2701_PLL_DOMAIN_1_RATE / 2)
79 -
80 -enum {
81 - MT2701_I2S_1,
82 - MT2701_I2S_2,
83 - MT2701_I2S_3,
84 - MT2701_I2S_4,
85 - MT2701_I2S_NUM,
86 -};
87 +#define MT2701_I2S_NUM 4
88
89 enum {
90 MT2701_MEMIF_DL1,
91 @@ -62,8 +54,7 @@ enum {
92 };
93
94 enum {
95 - MT2701_IRQ_ASYS_START,
96 - MT2701_IRQ_ASYS_IRQ1 = MT2701_IRQ_ASYS_START,
97 + MT2701_IRQ_ASYS_IRQ1,
98 MT2701_IRQ_ASYS_IRQ2,
99 MT2701_IRQ_ASYS_IRQ3,
100 MT2701_IRQ_ASYS_END,
101 @@ -100,9 +91,6 @@ static const unsigned int mt2701_afe_backup_list[] = {
102 AFE_MEMIF_PBUF_SIZE,
103 };
104
105 -struct snd_pcm_substream;
106 -struct mtk_base_irq_data;
107 -
108 struct mt2701_i2s_data {
109 int i2s_ctrl_reg;
110 int i2s_asrc_fs_shift;
111 @@ -120,7 +108,7 @@ struct mt2701_i2s_path {
112 int mclk_rate;
113 int on[I2S_DIR_NUM];
114 int occupied[I2S_DIR_NUM];
115 - const struct mt2701_i2s_data *i2s_data[2];
116 + const struct mt2701_i2s_data *i2s_data[I2S_DIR_NUM];
117 struct clk *hop_ck[I2S_DIR_NUM];
118 struct clk *sel_ck;
119 struct clk *div_ck;
120 diff --git a/sound/soc/mediatek/mt2701/mt2701-afe-pcm.c b/sound/soc/mediatek/mt2701/mt2701-afe-pcm.c
121 index 33f809228f25..0edadca12a5e 100644
122 --- a/sound/soc/mediatek/mt2701/mt2701-afe-pcm.c
123 +++ b/sound/soc/mediatek/mt2701/mt2701-afe-pcm.c
124 @@ -20,16 +20,12 @@
125 #include <linux/of.h>
126 #include <linux/of_address.h>
127 #include <linux/pm_runtime.h>
128 -#include <sound/soc.h>
129
130 #include "mt2701-afe-common.h"
131 -
132 #include "mt2701-afe-clock-ctrl.h"
133 #include "../common/mtk-afe-platform-driver.h"
134 #include "../common/mtk-afe-fe-dai.h"
135
136 -#define AFE_IRQ_STATUS_BITS 0xff
137 -
138 static const struct snd_pcm_hardware mt2701_afe_hardware = {
139 .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED
140 | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID,
141 @@ -107,21 +103,16 @@ static int mt2701_afe_i2s_startup(struct snd_pcm_substream *substream,
142
143 static int mt2701_afe_i2s_path_shutdown(struct snd_pcm_substream *substream,
144 struct snd_soc_dai *dai,
145 + int i2s_num,
146 int dir_invert)
147 {
148 struct snd_soc_pcm_runtime *rtd = substream->private_data;
149 struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
150 struct mt2701_afe_private *afe_priv = afe->platform_priv;
151 - int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
152 - struct mt2701_i2s_path *i2s_path;
153 + struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[i2s_num];
154 const struct mt2701_i2s_data *i2s_data;
155 int stream_dir = substream->stream;
156
157 - if (i2s_num < 0)
158 - return i2s_num;
159 -
160 - i2s_path = &afe_priv->i2s_path[i2s_num];
161 -
162 if (dir_invert) {
163 if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK)
164 stream_dir = SNDRV_PCM_STREAM_CAPTURE;
165 @@ -167,11 +158,11 @@ static void mt2701_afe_i2s_shutdown(struct snd_pcm_substream *substream,
166 else
167 goto I2S_UNSTART;
168
169 - mt2701_afe_i2s_path_shutdown(substream, dai, 0);
170 + mt2701_afe_i2s_path_shutdown(substream, dai, i2s_num, 0);
171
172 /* need to disable i2s-out path when disable i2s-in */
173 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
174 - mt2701_afe_i2s_path_shutdown(substream, dai, 1);
175 + mt2701_afe_i2s_path_shutdown(substream, dai, i2s_num, 1);
176
177 I2S_UNSTART:
178 /* disable mclk */
179 @@ -180,24 +171,19 @@ static void mt2701_afe_i2s_shutdown(struct snd_pcm_substream *substream,
180
181 static int mt2701_i2s_path_prepare_enable(struct snd_pcm_substream *substream,
182 struct snd_soc_dai *dai,
183 + int i2s_num,
184 int dir_invert)
185 {
186 struct snd_soc_pcm_runtime *rtd = substream->private_data;
187 struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
188 struct mt2701_afe_private *afe_priv = afe->platform_priv;
189 - int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
190 - struct mt2701_i2s_path *i2s_path;
191 + struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[i2s_num];
192 const struct mt2701_i2s_data *i2s_data;
193 struct snd_pcm_runtime * const runtime = substream->runtime;
194 int reg, fs, w_len = 1; /* now we support bck 64bits only */
195 int stream_dir = substream->stream;
196 unsigned int mask = 0, val = 0;
197
198 - if (i2s_num < 0)
199 - return i2s_num;
200 -
201 - i2s_path = &afe_priv->i2s_path[i2s_num];
202 -
203 if (dir_invert) {
204 if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK)
205 stream_dir = SNDRV_PCM_STREAM_CAPTURE;
206 @@ -288,13 +274,13 @@ static int mt2701_afe_i2s_prepare(struct snd_pcm_substream *substream,
207 mt2701_mclk_configuration(afe, i2s_num, clk_domain, mclk_rate);
208
209 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
210 - mt2701_i2s_path_prepare_enable(substream, dai, 0);
211 + mt2701_i2s_path_prepare_enable(substream, dai, i2s_num, 0);
212 } else {
213 /* need to enable i2s-out path when enable i2s-in */
214 /* prepare for another direction "out" */
215 - mt2701_i2s_path_prepare_enable(substream, dai, 1);
216 + mt2701_i2s_path_prepare_enable(substream, dai, i2s_num, 1);
217 /* prepare for "in" */
218 - mt2701_i2s_path_prepare_enable(substream, dai, 0);
219 + mt2701_i2s_path_prepare_enable(substream, dai, i2s_num, 0);
220 }
221
222 return 0;
223 @@ -562,7 +548,6 @@ static const struct snd_soc_dai_ops mt2701_single_memif_dai_ops = {
224 .hw_free = mtk_afe_fe_hw_free,
225 .prepare = mtk_afe_fe_prepare,
226 .trigger = mtk_afe_fe_trigger,
227 -
228 };
229
230 static const struct snd_soc_dai_ops mt2701_dlm_memif_dai_ops = {
231 @@ -903,31 +888,6 @@ static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s4[] = {
232 PWR2_TOP_CON, 19, 1, 0),
233 };
234
235 -static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_asrc0[] = {
236 - SOC_DAPM_SINGLE_AUTODISABLE("Asrc0 out Switch", AUDIO_TOP_CON4, 14, 1,
237 - 1),
238 -};
239 -
240 -static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_asrc1[] = {
241 - SOC_DAPM_SINGLE_AUTODISABLE("Asrc1 out Switch", AUDIO_TOP_CON4, 15, 1,
242 - 1),
243 -};
244 -
245 -static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_asrc2[] = {
246 - SOC_DAPM_SINGLE_AUTODISABLE("Asrc2 out Switch", PWR2_TOP_CON, 6, 1,
247 - 1),
248 -};
249 -
250 -static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_asrc3[] = {
251 - SOC_DAPM_SINGLE_AUTODISABLE("Asrc3 out Switch", PWR2_TOP_CON, 7, 1,
252 - 1),
253 -};
254 -
255 -static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_asrc4[] = {
256 - SOC_DAPM_SINGLE_AUTODISABLE("Asrc4 out Switch", PWR2_TOP_CON, 8, 1,
257 - 1),
258 -};
259 -
260 static const struct snd_soc_dapm_widget mt2701_afe_pcm_widgets[] = {
261 /* inter-connections */
262 SND_SOC_DAPM_MIXER("I00", SND_SOC_NOPM, 0, 0, NULL, 0),
263 @@ -987,19 +947,6 @@ static const struct snd_soc_dapm_widget mt2701_afe_pcm_widgets[] = {
264 SND_SOC_DAPM_MIXER("I18I19", SND_SOC_NOPM, 0, 0,
265 mt2701_afe_multi_ch_out_i2s3,
266 ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s3)),
267 -
268 - SND_SOC_DAPM_MIXER("ASRC_O0", SND_SOC_NOPM, 0, 0,
269 - mt2701_afe_multi_ch_out_asrc0,
270 - ARRAY_SIZE(mt2701_afe_multi_ch_out_asrc0)),
271 - SND_SOC_DAPM_MIXER("ASRC_O1", SND_SOC_NOPM, 0, 0,
272 - mt2701_afe_multi_ch_out_asrc1,
273 - ARRAY_SIZE(mt2701_afe_multi_ch_out_asrc1)),
274 - SND_SOC_DAPM_MIXER("ASRC_O2", SND_SOC_NOPM, 0, 0,
275 - mt2701_afe_multi_ch_out_asrc2,
276 - ARRAY_SIZE(mt2701_afe_multi_ch_out_asrc2)),
277 - SND_SOC_DAPM_MIXER("ASRC_O3", SND_SOC_NOPM, 0, 0,
278 - mt2701_afe_multi_ch_out_asrc3,
279 - ARRAY_SIZE(mt2701_afe_multi_ch_out_asrc3)),
280 };
281
282 static const struct snd_soc_dapm_route mt2701_afe_pcm_routes[] = {
283 @@ -1009,7 +956,6 @@ static const struct snd_soc_dapm_route mt2701_afe_pcm_routes[] = {
284
285 {"I2S0 Playback", NULL, "O15"},
286 {"I2S0 Playback", NULL, "O16"},
287 -
288 {"I2S1 Playback", NULL, "O17"},
289 {"I2S1 Playback", NULL, "O18"},
290 {"I2S2 Playback", NULL, "O19"},
291 @@ -1026,7 +972,6 @@ static const struct snd_soc_dapm_route mt2701_afe_pcm_routes[] = {
292
293 {"I00", NULL, "I2S0 Capture"},
294 {"I01", NULL, "I2S0 Capture"},
295 -
296 {"I02", NULL, "I2S1 Capture"},
297 {"I03", NULL, "I2S1 Capture"},
298 /* I02,03 link to UL2, also need to open I2S0 */
299 @@ -1034,15 +979,10 @@ static const struct snd_soc_dapm_route mt2701_afe_pcm_routes[] = {
300
301 {"I26", NULL, "BT Capture"},
302
303 - {"ASRC_O0", "Asrc0 out Switch", "DLM"},
304 - {"ASRC_O1", "Asrc1 out Switch", "DLM"},
305 - {"ASRC_O2", "Asrc2 out Switch", "DLM"},
306 - {"ASRC_O3", "Asrc3 out Switch", "DLM"},
307 -
308 - {"I12I13", "Multich I2S0 Out Switch", "ASRC_O0"},
309 - {"I14I15", "Multich I2S1 Out Switch", "ASRC_O1"},
310 - {"I16I17", "Multich I2S2 Out Switch", "ASRC_O2"},
311 - {"I18I19", "Multich I2S3 Out Switch", "ASRC_O3"},
312 + {"I12I13", "Multich I2S0 Out Switch", "DLM"},
313 + {"I14I15", "Multich I2S1 Out Switch", "DLM"},
314 + {"I16I17", "Multich I2S2 Out Switch", "DLM"},
315 + {"I18I19", "Multich I2S3 Out Switch", "DLM"},
316
317 { "I12", NULL, "I12I13" },
318 { "I13", NULL, "I12I13" },
319 @@ -1067,7 +1007,6 @@ static const struct snd_soc_dapm_route mt2701_afe_pcm_routes[] = {
320 { "O21", "I18 Switch", "I18" },
321 { "O22", "I19 Switch", "I19" },
322 { "O31", "I35 Switch", "I35" },
323 -
324 };
325
326 static const struct snd_soc_component_driver mt2701_afe_pcm_dai_component = {
327 @@ -1484,12 +1423,13 @@ static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev)
328 afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
329 if (!afe)
330 return -ENOMEM;
331 +
332 afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
333 GFP_KERNEL);
334 if (!afe->platform_priv)
335 return -ENOMEM;
336 - afe_priv = afe->platform_priv;
337
338 + afe_priv = afe->platform_priv;
339 afe->dev = &pdev->dev;
340 dev = afe->dev;
341
342 @@ -1524,7 +1464,6 @@ static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev)
343 afe->memif_size = MT2701_MEMIF_NUM;
344 afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
345 GFP_KERNEL);
346 -
347 if (!afe->memif)
348 return -ENOMEM;
349
350 @@ -1537,7 +1476,6 @@ static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev)
351 afe->irqs_size = MT2701_IRQ_ASYS_END;
352 afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
353 GFP_KERNEL);
354 -
355 if (!afe->irqs)
356 return -ENOMEM;
357
358 @@ -1555,7 +1493,6 @@ static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev)
359 afe->mtk_afe_hardware = &mt2701_afe_hardware;
360 afe->memif_fs = mt2701_memif_fs;
361 afe->irq_fs = mt2701_irq_fs;
362 -
363 afe->reg_back_up_list = mt2701_afe_backup_list;
364 afe->reg_back_up_list_num = ARRAY_SIZE(mt2701_afe_backup_list);
365 afe->runtime_resume = mt2701_afe_runtime_resume;
366 @@ -1646,4 +1583,3 @@ module_platform_driver(mt2701_afe_pcm_driver);
367 MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 2701");
368 MODULE_AUTHOR("Garlic Tseng <garlic.tseng@mediatek.com>");
369 MODULE_LICENSE("GPL v2");
370 -
371 diff --git a/sound/soc/mediatek/mt2701/mt2701-reg.h b/sound/soc/mediatek/mt2701/mt2701-reg.h
372 index bb62b1c55957..f17c76f37b5f 100644
373 --- a/sound/soc/mediatek/mt2701/mt2701-reg.h
374 +++ b/sound/soc/mediatek/mt2701/mt2701-reg.h
375 @@ -17,17 +17,6 @@
376 #ifndef _MT2701_REG_H_
377 #define _MT2701_REG_H_
378
379 -#include <linux/delay.h>
380 -#include <linux/module.h>
381 -#include <linux/of.h>
382 -#include <linux/of_address.h>
383 -#include <linux/pm_runtime.h>
384 -#include <sound/soc.h>
385 -#include "mt2701-afe-common.h"
386 -
387 -/*****************************************************************************
388 - * R E G I S T E R D E F I N I T I O N
389 - *****************************************************************************/
390 #define AUDIO_TOP_CON0 0x0000
391 #define AUDIO_TOP_CON4 0x0010
392 #define AUDIO_TOP_CON5 0x0014
393 @@ -109,18 +98,6 @@
394 #define AFE_DAI_BASE 0x1370
395 #define AFE_DAI_CUR 0x137c
396
397 -/* AUDIO_TOP_CON0 (0x0000) */
398 -#define AUDIO_TOP_CON0_A1SYS_A2SYS_ON (0x3 << 0)
399 -#define AUDIO_TOP_CON0_PDN_AFE (0x1 << 2)
400 -#define AUDIO_TOP_CON0_PDN_APLL_CK (0x1 << 23)
401 -
402 -/* AUDIO_TOP_CON4 (0x0010) */
403 -#define AUDIO_TOP_CON4_I2SO1_PWN (0x1 << 6)
404 -#define AUDIO_TOP_CON4_PDN_A1SYS (0x1 << 21)
405 -#define AUDIO_TOP_CON4_PDN_A2SYS (0x1 << 22)
406 -#define AUDIO_TOP_CON4_PDN_AFE_CONN (0x1 << 23)
407 -#define AUDIO_TOP_CON4_PDN_MRGIF (0x1 << 25)
408 -
409 /* AFE_DAIBT_CON0 (0x001c) */
410 #define AFE_DAIBT_CON0_DAIBT_EN (0x1 << 0)
411 #define AFE_DAIBT_CON0_BT_FUNC_EN (0x1 << 1)
412 @@ -137,22 +114,8 @@
413 #define AFE_MRGIF_CON_I2S_MODE_MASK (0xf << 20)
414 #define AFE_MRGIF_CON_I2S_MODE_32K (0x4 << 20)
415
416 -/* ASYS_I2SO1_CON (0x061c) */
417 -#define ASYS_I2SO1_CON_FS (0x1f << 8)
418 -#define ASYS_I2SO1_CON_FS_SET(x) ((x) << 8)
419 -#define ASYS_I2SO1_CON_MULTI_CH (0x1 << 16)
420 -#define ASYS_I2SO1_CON_SIDEGEN (0x1 << 30)
421 -#define ASYS_I2SO1_CON_I2S_EN (0x1 << 0)
422 -/* 0:EIAJ 1:I2S */
423 -#define ASYS_I2SO1_CON_I2S_MODE (0x1 << 3)
424 -#define ASYS_I2SO1_CON_WIDE_MODE (0x1 << 1)
425 -#define ASYS_I2SO1_CON_WIDE_MODE_SET(x) ((x) << 1)
426 -
427 -/* PWR2_TOP_CON (0x0634) */
428 -#define PWR2_TOP_CON_INIT_VAL (0xffe1ffff)
429 -
430 -/* ASYS_IRQ_CLR (0x07c0) */
431 -#define ASYS_IRQ_CLR_ALL (0xffffffff)
432 +/* ASYS_TOP_CON (0x0600) */
433 +#define ASYS_TOP_CON_ASYS_TIMING_ON (0x3 << 0)
434
435 /* PWR2_ASM_CON1 (0x1070) */
436 #define PWR2_ASM_CON1_INIT_VAL (0x492492)
437 --
438 2.11.0
439