mediatek: backport upstream mediatek patches
[openwrt/openwrt.git] / target / linux / mediatek / patches-4.14 / 0201-dt-bindings-clock-mediatek-add-missing-required-rese.patch
1 From 4a1990ee249df257848f9583cef71478e3411c3e Mon Sep 17 00:00:00 2001
2 From: Sean Wang <sean.wang@mediatek.com>
3 Date: Thu, 28 Dec 2017 11:24:45 +0800
4 Subject: [PATCH 201/224] dt-bindings: clock: mediatek: add missing required
5 #reset-cells
6
7 All ethsys, pciesys and ssusbsys internally include reset controller, so
8 explicitly add back these missing cell definitions to related bindings
9 and examples.
10
11 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
12 Cc: Rob Herring <robh@kernel.org>
13 Cc: Michael Turquette <mturquette@baylibre.com>
14 Cc: Stephen Boyd <sboyd@codeaurora.org>
15 Cc: linux-clk@vger.kernel.org
16 Reviewed-by: Rob Herring <robh@kernel.org>
17 ---
18 Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt | 1 +
19 Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt | 2 ++
20 Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt | 2 ++
21 3 files changed, 5 insertions(+)
22
23 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
24 index 7aa3fa167668..52757adf86bb 100644
25 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
26 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
27 @@ -9,6 +9,7 @@ Required Properties:
28 - "mediatek,mt2701-ethsys", "syscon"
29 - "mediatek,mt7622-ethsys", "syscon"
30 - #clock-cells: Must be 1
31 +- #reset-cells: Must be 1
32
33 The ethsys controller uses the common clk binding from
34 Documentation/devicetree/bindings/clock/clock-bindings.txt
35 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt
36 index d5d5f1227665..7fe5dc6097a6 100644
37 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt
38 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt
39 @@ -8,6 +8,7 @@ Required Properties:
40 - compatible: Should be:
41 - "mediatek,mt7622-pciesys", "syscon"
42 - #clock-cells: Must be 1
43 +- #reset-cells: Must be 1
44
45 The PCIESYS controller uses the common clk binding from
46 Documentation/devicetree/bindings/clock/clock-bindings.txt
47 @@ -19,4 +20,5 @@ pciesys: pciesys@1a100800 {
48 compatible = "mediatek,mt7622-pciesys", "syscon";
49 reg = <0 0x1a100800 0 0x1000>;
50 #clock-cells = <1>;
51 + #reset-cells = <1>;
52 };
53 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt
54 index 00760019da00..b8184da2508c 100644
55 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt
56 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt
57 @@ -8,6 +8,7 @@ Required Properties:
58 - compatible: Should be:
59 - "mediatek,mt7622-ssusbsys", "syscon"
60 - #clock-cells: Must be 1
61 +- #reset-cells: Must be 1
62
63 The SSUSBSYS controller uses the common clk binding from
64 Documentation/devicetree/bindings/clock/clock-bindings.txt
65 @@ -19,4 +20,5 @@ ssusbsys: ssusbsys@1a000000 {
66 compatible = "mediatek,mt7622-ssusbsys", "syscon";
67 reg = <0 0x1a000000 0 0x1000>;
68 #clock-cells = <1>;
69 + #reset-cells = <1>;
70 };
71 --
72 2.11.0
73