mediatek: backport upstream mediatek patches
[openwrt/openwrt.git] / target / linux / mediatek / patches-4.14 / 0218-arm64-dts-mt7622-add-ethernet-device-nodes.patch
1 From 4fbacf244953285ac58cb833060076fafd990588 Mon Sep 17 00:00:00 2001
2 From: Sean Wang <sean.wang@mediatek.com>
3 Date: Fri, 29 Dec 2017 10:45:07 +0800
4 Subject: [PATCH 218/224] arm64: dts: mt7622: add ethernet device nodes
5
6 add ethernet device nodes which enable GMAC1 with SGMII interface
7
8 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
9 ---
10 arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 22 ++++++++++++++++++++
11 arch/arm64/boot/dts/mediatek/mt7622.dtsi | 31 ++++++++++++++++++++++++++++
12 2 files changed, 53 insertions(+)
13
14 diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
15 index 48c5ba472721..e2bd93e1b49b 100644
16 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
17 +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
18 @@ -249,6 +249,28 @@
19 status = "okay";
20 };
21
22 +&eth {
23 + pinctrl-names = "default";
24 + pinctrl-0 = <&eth_pins>;
25 + status = "okay";
26 +
27 + gmac1: mac@1 {
28 + compatible = "mediatek,eth-mac";
29 + reg = <1>;
30 + phy-handle = <&phy5>;
31 + };
32 +
33 + mdio-bus {
34 + #address-cells = <1>;
35 + #size-cells = <0>;
36 +
37 + phy5: ethernet-phy@5 {
38 + reg = <5>;
39 + phy-mode = "sgmii";
40 + };
41 + };
42 +};
43 +
44 &i2c1 {
45 pinctrl-names = "default";
46 pinctrl-0 = <&i2c1_pins>;
47 diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
48 index d287d75e1a54..95f947eb824c 100644
49 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
50 +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
51 @@ -550,6 +550,37 @@
52 #reset-cells = <1>;
53 };
54
55 + eth: ethernet@1b100000 {
56 + compatible = "mediatek,mt7622-eth",
57 + "mediatek,mt2701-eth",
58 + "syscon";
59 + reg = <0 0x1b100000 0 0x20000>;
60 + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
61 + <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
62 + <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
63 + clocks = <&topckgen CLK_TOP_ETH_SEL>,
64 + <&ethsys CLK_ETH_ESW_EN>,
65 + <&ethsys CLK_ETH_GP0_EN>,
66 + <&ethsys CLK_ETH_GP1_EN>,
67 + <&ethsys CLK_ETH_GP2_EN>,
68 + <&sgmiisys CLK_SGMII_TX250M_EN>,
69 + <&sgmiisys CLK_SGMII_RX250M_EN>,
70 + <&sgmiisys CLK_SGMII_CDR_REF>,
71 + <&sgmiisys CLK_SGMII_CDR_FB>,
72 + <&topckgen CLK_TOP_SGMIIPLL>,
73 + <&apmixedsys CLK_APMIXED_ETH2PLL>;
74 + clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
75 + "sgmii_tx250m", "sgmii_rx250m",
76 + "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
77 + "eth2pll";
78 + power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
79 + mediatek,ethsys = <&ethsys>;
80 + mediatek,sgmiisys = <&sgmiisys>;
81 + #address-cells = <1>;
82 + #size-cells = <0>;
83 + status = "disabled";
84 + };
85 +
86 sgmiisys: sgmiisys@1b128000 {
87 compatible = "mediatek,mt7622-sgmiisys",
88 "syscon";
89 --
90 2.11.0
91