target/linux/mediatek/patches-4.14/0220-arm64-dts-mt7622-add-SATA-device-nodes.patch

   1 From 0c8d249a70818f4f8e0d5543dc7157dfd8a5265e Mon Sep 17 00:00:00 2001
   2 From: Ryder Lee <ryder.lee@mediatek.com>
   3 Date: Wed, 20 Dec 2017 16:04:24 +0800
   4 Subject: [PATCH 220/224] arm64: dts: mt7622: add SATA device nodes
   5
   6 This patch adds SATA support fot MT7622.
   7
   8 Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
   9 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
  10 ---
  11  arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts |  8 ++++++
  12  arch/arm64/boot/dts/mediatek/mt7622.dtsi     | 40 ++++++++++++++++++++++++++++
  13  2 files changed, 48 insertions(+)
  14
  15 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
  16 +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
  17 @@ -323,6 +323,14 @@
  18         status = "okay";
  19  };
  20
  21 +&sata {
  22 +       status = "okay";
  23 +};
  24 +
  25 +&sata_phy {
  26 +       status = "okay";
  27 +};
  28 +
  29  &spi0 {
  30         pinctrl-names = "default";
  31         pinctrl-0 = <&spic0_pins>;
  32 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
  33 +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
  34 @@ -9,6 +9,7 @@
  35  #include <dt-bindings/interrupt-controller/irq.h>
  36  #include <dt-bindings/interrupt-controller/arm-gic.h>
  37  #include <dt-bindings/clock/mt7622-clk.h>
  38 +#include <dt-bindings/phy/phy.h>
  39  #include <dt-bindings/power/mt7622-power.h>
  40  #include <dt-bindings/reset/mt7622-reset.h>
  41  #include <dt-bindings/thermal/thermal.h>
  42 @@ -616,6 +617,45 @@
  43                 };
  44         };
  45
  46 +       sata: sata@1a200000 {
  47 +               compatible = "mediatek,mt7622-ahci",
  48 +                            "mediatek,mtk-ahci";
  49 +               reg = <0 0x1a200000 0 0x1100>;
  50 +               interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
  51 +               interrupt-names = "hostc";
  52 +               clocks = <&pciesys CLK_SATA_AHB_EN>,
  53 +                        <&pciesys CLK_SATA_AXI_EN>,
  54 +                        <&pciesys CLK_SATA_ASIC_EN>,
  55 +                        <&pciesys CLK_SATA_RBC_EN>,
  56 +                        <&pciesys CLK_SATA_PM_EN>;
  57 +               clock-names = "ahb", "axi", "asic", "rbc", "pm";
  58 +               phys = <&sata_port PHY_TYPE_SATA>;
  59 +               phy-names = "sata-phy";
  60 +               ports-implemented = <0x1>;
  61 +               power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
  62 +               resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
  63 +                        <&pciesys MT7622_SATA_PHY_SW_RST>,
  64 +                        <&pciesys MT7622_SATA_PHY_REG_RST>;
  65 +               reset-names = "axi", "sw", "reg";
  66 +               mediatek,phy-mode = <&pciesys>;
  67 +               status = "disabled";
  68 +       };
  69 +
  70 +       sata_phy: sata-phy@1a243000 {
  71 +               compatible = "mediatek,generic-tphy-v1";
  72 +               #address-cells = <2>;
  73 +               #size-cells = <2>;
  74 +               ranges;
  75 +               status = "disabled";
  76 +
  77 +               sata_port: sata-phy@1a243000 {
  78 +                       reg = <0 0x1a243000 0 0x0100>;
  79 +                       clocks = <&topckgen CLK_TOP_ETH_500M>;
  80 +                       clock-names = "ref";
  81 +                       #phy-cells = <1>;
  82 +               };
  83 +       };
  84 +
  85         ethsys: syscon@1b000000 {
  86                 compatible = "mediatek,mt7622-ethsys",
  87                              "syscon";