mediatek: backport upstream mediatek patches
[openwrt/openwrt.git] / target / linux / mediatek / patches-4.14 / 0220-arm64-dts-mt7622-add-SATA-device-nodes.patch
1 From 0c8d249a70818f4f8e0d5543dc7157dfd8a5265e Mon Sep 17 00:00:00 2001
2 From: Ryder Lee <ryder.lee@mediatek.com>
3 Date: Wed, 20 Dec 2017 16:04:24 +0800
4 Subject: [PATCH 220/224] arm64: dts: mt7622: add SATA device nodes
5
6 This patch adds SATA support fot MT7622.
7
8 Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
9 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
10 ---
11 arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 8 ++++++
12 arch/arm64/boot/dts/mediatek/mt7622.dtsi | 40 ++++++++++++++++++++++++++++
13 2 files changed, 48 insertions(+)
14
15 diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
16 index 72ef4434bcef..6715ffa5c15e 100644
17 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
18 +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
19 @@ -323,6 +323,14 @@
20 status = "okay";
21 };
22
23 +&sata {
24 + status = "okay";
25 +};
26 +
27 +&sata_phy {
28 + status = "okay";
29 +};
30 +
31 &spi0 {
32 pinctrl-names = "default";
33 pinctrl-0 = <&spic0_pins>;
34 diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
35 index cc026ebda2f4..881bc17f8f0d 100644
36 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
37 +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
38 @@ -9,6 +9,7 @@
39 #include <dt-bindings/interrupt-controller/irq.h>
40 #include <dt-bindings/interrupt-controller/arm-gic.h>
41 #include <dt-bindings/clock/mt7622-clk.h>
42 +#include <dt-bindings/phy/phy.h>
43 #include <dt-bindings/power/mt7622-power.h>
44 #include <dt-bindings/reset/mt7622-reset.h>
45 #include <dt-bindings/thermal/thermal.h>
46 @@ -616,6 +617,45 @@
47 };
48 };
49
50 + sata: sata@1a200000 {
51 + compatible = "mediatek,mt7622-ahci",
52 + "mediatek,mtk-ahci";
53 + reg = <0 0x1a200000 0 0x1100>;
54 + interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
55 + interrupt-names = "hostc";
56 + clocks = <&pciesys CLK_SATA_AHB_EN>,
57 + <&pciesys CLK_SATA_AXI_EN>,
58 + <&pciesys CLK_SATA_ASIC_EN>,
59 + <&pciesys CLK_SATA_RBC_EN>,
60 + <&pciesys CLK_SATA_PM_EN>;
61 + clock-names = "ahb", "axi", "asic", "rbc", "pm";
62 + phys = <&sata_port PHY_TYPE_SATA>;
63 + phy-names = "sata-phy";
64 + ports-implemented = <0x1>;
65 + power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
66 + resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
67 + <&pciesys MT7622_SATA_PHY_SW_RST>,
68 + <&pciesys MT7622_SATA_PHY_REG_RST>;
69 + reset-names = "axi", "sw", "reg";
70 + mediatek,phy-mode = <&pciesys>;
71 + status = "disabled";
72 + };
73 +
74 + sata_phy: sata-phy@1a243000 {
75 + compatible = "mediatek,generic-tphy-v1";
76 + #address-cells = <2>;
77 + #size-cells = <2>;
78 + ranges;
79 + status = "disabled";
80 +
81 + sata_port: sata-phy@1a243000 {
82 + reg = <0 0x1a243000 0 0x0100>;
83 + clocks = <&topckgen CLK_TOP_ETH_500M>;
84 + clock-names = "ref";
85 + #phy-cells = <1>;
86 + };
87 + };
88 +
89 ethsys: syscon@1b000000 {
90 compatible = "mediatek,mt7622-ethsys",
91 "syscon";
92 --
93 2.11.0
94