kernel: bump 4.14 to 4.14.53
[openwrt/openwrt.git] / target / linux / mediatek / patches-4.14 / 0225-arm-dts-Add-missing-mt7623-pcie-nodes.patch
1 From d31800ff6ed81f44488b590fe372e7b6572d2896 Mon Sep 17 00:00:00 2001
2 From: Kristian Evensen <kristian.evensen@gmail.com>
3 Date: Sun, 17 Jun 2018 14:18:45 +0200
4 Subject: [PATCH] arm: dts: Add missing mt7623 pcie nodes
5
6 ---
7 arch/arm/boot/dts/mt7623.dtsi | 105 ++++++++++++++++++++++++++++++++++++++++++
8 1 file changed, 105 insertions(+)
9
10 --- a/arch/arm/boot/dts/mt7623.dtsi
11 +++ b/arch/arm/boot/dts/mt7623.dtsi
12 @@ -671,6 +671,111 @@
13 #reset-cells = <1>;
14 };
15
16 + pcie: pcie@1a140000 {
17 + compatible = "mediatek,mt7623-pcie";
18 + device_type = "pci";
19 + reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
20 + <0 0x1a142000 0 0x1000>, /* Port0 registers */
21 + <0 0x1a143000 0 0x1000>, /* Port1 registers */
22 + <0 0x1a144000 0 0x1000>; /* Port2 registers */
23 + reg-names = "subsys", "port0", "port1", "port2";
24 + #address-cells = <3>;
25 + #size-cells = <2>;
26 + #interrupt-cells = <1>;
27 + interrupt-map-mask = <0xf800 0 0 0>;
28 + interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
29 + <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
30 + <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
31 + clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
32 + <&hifsys CLK_HIFSYS_PCIE0>,
33 + <&hifsys CLK_HIFSYS_PCIE1>,
34 + <&hifsys CLK_HIFSYS_PCIE2>;
35 + clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
36 + resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
37 + <&hifsys MT2701_HIFSYS_PCIE1_RST>,
38 + <&hifsys MT2701_HIFSYS_PCIE2_RST>;
39 + reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
40 + phys = <&pcie0_port PHY_TYPE_PCIE>,
41 + <&pcie1_port PHY_TYPE_PCIE>,
42 + <&u3port1 PHY_TYPE_PCIE>;
43 + phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
44 + power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
45 + bus-range = <0x00 0xff>;
46 + status = "disabled";
47 + ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000
48 + 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>;
49 +
50 + pcie@0,0 {
51 + reg = <0x0000 0 0 0 0>;
52 + #address-cells = <3>;
53 + #size-cells = <2>;
54 + #interrupt-cells = <1>;
55 + interrupt-map-mask = <0 0 0 0>;
56 + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
57 + ranges;
58 + num-lanes = <1>;
59 + status = "disabled";
60 + };
61 + pcie@1,0 {
62 + reg = <0x0800 0 0 0 0>;
63 + #address-cells = <3>;
64 + #size-cells = <2>;
65 + #interrupt-cells = <1>;
66 + interrupt-map-mask = <0 0 0 0>;
67 + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
68 + ranges;
69 + num-lanes = <1>;
70 + status = "disabled";
71 + };
72 +
73 + pcie@2,0 {
74 + reg = <0x1000 0 0 0 0>;
75 + #address-cells = <3>;
76 + #size-cells = <2>;
77 + #interrupt-cells = <1>;
78 + interrupt-map-mask = <0 0 0 0>;
79 + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
80 + ranges;
81 + num-lanes = <1>;
82 + status = "disabled";
83 + };
84 + };
85 +
86 + pcie0_phy: pcie-phy@1a149000 {
87 + compatible = "mediatek,generic-tphy-v1";
88 + reg = <0 0x1a149000 0 0x0700>;
89 + #address-cells = <2>;
90 + #size-cells = <2>;
91 + ranges;
92 + status = "disabled";
93 +
94 + pcie0_port: pcie-phy@1a149900 {
95 + reg = <0 0x1a149900 0 0x0700>;
96 + clocks = <&clk26m>;
97 + clock-names = "ref";
98 + #phy-cells = <1>;
99 + status = "okay";
100 + };
101 + };
102 +
103 + pcie1_phy: pcie-phy@1a14a000 {
104 + compatible = "mediatek,generic-tphy-v1";
105 + reg = <0 0x1a14a000 0 0x0700>;
106 + #address-cells = <2>;
107 + #size-cells = <2>;
108 + ranges;
109 + status = "disabled";
110 +
111 + pcie1_port: pcie-phy@1a14a900 {
112 + reg = <0 0x1a14a900 0 0x0700>;
113 + clocks = <&clk26m>;
114 + clock-names = "ref";
115 + #phy-cells = <1>;
116 + status = "okay";
117 + };
118 + };
119 +
120 +
121 usb1: usb@1a1c0000 {
122 compatible = "mediatek,mt7623-xhci",
123 "mediatek,mt8173-xhci";