b87f95c1f9e93fd2fa5000b5b3fe42f71b4c035b
[openwrt/openwrt.git] / target / linux / mediatek / patches-4.14 / 0225-arm-dts-Add-missing-mt7623-pcie-nodes.patch
1 From d31800ff6ed81f44488b590fe372e7b6572d2896 Mon Sep 17 00:00:00 2001
2 From: Kristian Evensen <kristian.evensen@gmail.com>
3 Date: Sun, 17 Jun 2018 14:18:45 +0200
4 Subject: [PATCH] arm: dts: Add missing mt7623 pcie nodes
5
6 ---
7 arch/arm/boot/dts/mt7623.dtsi | 105 ++++++++++++++++++++++++++++++++++++++++++
8 1 file changed, 105 insertions(+)
9
10 diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
11 index 36983a7d7..714245365 100644
12 --- a/arch/arm/boot/dts/mt7623.dtsi
13 +++ b/arch/arm/boot/dts/mt7623.dtsi
14 @@ -669,6 +669,111 @@
15 #reset-cells = <1>;
16 };
17
18 + pcie: pcie@1a140000 {
19 + compatible = "mediatek,mt7623-pcie";
20 + device_type = "pci";
21 + reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
22 + <0 0x1a142000 0 0x1000>, /* Port0 registers */
23 + <0 0x1a143000 0 0x1000>, /* Port1 registers */
24 + <0 0x1a144000 0 0x1000>; /* Port2 registers */
25 + reg-names = "subsys", "port0", "port1", "port2";
26 + #address-cells = <3>;
27 + #size-cells = <2>;
28 + #interrupt-cells = <1>;
29 + interrupt-map-mask = <0xf800 0 0 0>;
30 + interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
31 + <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
32 + <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
33 + clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
34 + <&hifsys CLK_HIFSYS_PCIE0>,
35 + <&hifsys CLK_HIFSYS_PCIE1>,
36 + <&hifsys CLK_HIFSYS_PCIE2>;
37 + clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
38 + resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
39 + <&hifsys MT2701_HIFSYS_PCIE1_RST>,
40 + <&hifsys MT2701_HIFSYS_PCIE2_RST>;
41 + reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
42 + phys = <&pcie0_port PHY_TYPE_PCIE>,
43 + <&pcie1_port PHY_TYPE_PCIE>,
44 + <&u3port1 PHY_TYPE_PCIE>;
45 + phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
46 + power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
47 + bus-range = <0x00 0xff>;
48 + status = "disabled";
49 + ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000
50 + 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>;
51 +
52 + pcie@0,0 {
53 + reg = <0x0000 0 0 0 0>;
54 + #address-cells = <3>;
55 + #size-cells = <2>;
56 + #interrupt-cells = <1>;
57 + interrupt-map-mask = <0 0 0 0>;
58 + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
59 + ranges;
60 + num-lanes = <1>;
61 + status = "disabled";
62 + };
63 + pcie@1,0 {
64 + reg = <0x0800 0 0 0 0>;
65 + #address-cells = <3>;
66 + #size-cells = <2>;
67 + #interrupt-cells = <1>;
68 + interrupt-map-mask = <0 0 0 0>;
69 + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
70 + ranges;
71 + num-lanes = <1>;
72 + status = "disabled";
73 + };
74 +
75 + pcie@2,0 {
76 + reg = <0x1000 0 0 0 0>;
77 + #address-cells = <3>;
78 + #size-cells = <2>;
79 + #interrupt-cells = <1>;
80 + interrupt-map-mask = <0 0 0 0>;
81 + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
82 + ranges;
83 + num-lanes = <1>;
84 + status = "disabled";
85 + };
86 + };
87 +
88 + pcie0_phy: pcie-phy@1a149000 {
89 + compatible = "mediatek,generic-tphy-v1";
90 + reg = <0 0x1a149000 0 0x0700>;
91 + #address-cells = <2>;
92 + #size-cells = <2>;
93 + ranges;
94 + status = "disabled";
95 +
96 + pcie0_port: pcie-phy@1a149900 {
97 + reg = <0 0x1a149900 0 0x0700>;
98 + clocks = <&clk26m>;
99 + clock-names = "ref";
100 + #phy-cells = <1>;
101 + status = "okay";
102 + };
103 + };
104 +
105 + pcie1_phy: pcie-phy@1a14a000 {
106 + compatible = "mediatek,generic-tphy-v1";
107 + reg = <0 0x1a14a000 0 0x0700>;
108 + #address-cells = <2>;
109 + #size-cells = <2>;
110 + ranges;
111 + status = "disabled";
112 +
113 + pcie1_port: pcie-phy@1a14a900 {
114 + reg = <0 0x1a14a900 0 0x0700>;
115 + clocks = <&clk26m>;
116 + clock-names = "ref";
117 + #phy-cells = <1>;
118 + status = "okay";
119 + };
120 + };
121 +
122 +
123 usb1: usb@1a1c0000 {
124 compatible = "mediatek,mt7623-xhci",
125 "mediatek,mt8173-xhci";
126 --
127 2.14.1
128