9d554da0be2521fda20504bf87e46a1ef7e0aef8
[openwrt/openwrt.git] / target / linux / mediatek / patches-4.14 / 0227-arm-dts-Add-Unielec-U7623-DTS.patch
1 From 0c88c72bf130c9276958dc6f595ea473ea357a75 Mon Sep 17 00:00:00 2001
2 From: Kristian Evensen <kristian.evensen@gmail.com>
3 Date: Sun, 17 Jun 2018 14:41:47 +0200
4 Subject: [PATCH] arm: dts: Add Unielec U7623 DTS
5
6 ---
7 arch/arm/boot/dts/Makefile | 1 +
8 .../dts/mt7623a-unielec-u7623-02-emmc-512M.dts | 17 +
9 .../boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi | 374 +++++++++++++++++++++
10 3 files changed, 392 insertions(+)
11 create mode 100644 arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512M.dts
12 create mode 100644 arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi
13
14 diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
15 index 3fec84fa0..e685ce9a4 100644
16 --- a/arch/arm/boot/dts/Makefile
17 +++ b/arch/arm/boot/dts/Makefile
18 @@ -1062,6 +1062,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
19 mt6589-aquaris5.dtb \
20 mt6592-evb.dtb \
21 mt7623a-rfb-emmc.dtb \
22 + mt7623a-unielec-u7623-02-emmc-512M.dtb \
23 mt7623n-rfb-nand.dtb \
24 mt7623n-bananapi-bpi-r2.dtb \
25 mt8127-moose.dtb \
26 diff --git a/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512M.dts b/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512M.dts
27 new file mode 100644
28 index 000000000..3b14eccd3
29 --- /dev/null
30 +++ b/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512M.dts
31 @@ -0,0 +1,17 @@
32 +/*
33 + * Copyright 2018 Kristian Evensen <kristian.evensen@gmail.com>
34 + *
35 + * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
36 + */
37 +
38 +/dts-v1/;
39 +#include "mt7623a-unielec-u7623-02-emmc.dtsi"
40 +
41 +/ {
42 + model = "UniElec U7623-02 eMMC (512M RAM)";
43 + compatible = "unielec,u7623-02-emmc-512m", "unielec,u7623-02-emmc", "mediatek,mt7623";
44 +
45 + memory {
46 + reg = <0 0x80000000 0 0x20000000>;
47 + };
48 +};
49 diff --git a/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi b/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi
50 new file mode 100644
51 index 000000000..4fc8ce8a9
52 --- /dev/null
53 +++ b/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi
54 @@ -0,0 +1,374 @@
55 +/*
56 + * Copyright 2018 Kristian Evensen <kristian.evensen@gmail.com>
57 + *
58 + * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
59 + */
60 +
61 +#include <dt-bindings/input/input.h>
62 +#include "mt7623.dtsi"
63 +#include "mt6323.dtsi"
64 +
65 +/ {
66 + compatible = "unielec,u7623-02-emmc", "mediatek,mt7623";
67 +
68 + aliases {
69 + serial2 = &uart2;
70 + };
71 +
72 + chosen {
73 + bootargs = "root=/dev/mmcblk0p2 rootfstype=squashfs,f2fs";
74 + stdout-path = "serial2:115200n8";
75 + };
76 +
77 + memory {
78 + reg = <0 0x80000000 0 0x20000000>;
79 + };
80 +
81 + cpus {
82 + cpu@0 {
83 + proc-supply = <&mt6323_vproc_reg>;
84 + };
85 +
86 + cpu@1 {
87 + proc-supply = <&mt6323_vproc_reg>;
88 + };
89 +
90 + cpu@2 {
91 + proc-supply = <&mt6323_vproc_reg>;
92 + };
93 +
94 + cpu@3 {
95 + proc-supply = <&mt6323_vproc_reg>;
96 + };
97 + };
98 +
99 + reg_1p8v: regulator-1p8v {
100 + compatible = "regulator-fixed";
101 + regulator-name = "fixed-1.8V";
102 + regulator-min-microvolt = <1800000>;
103 + regulator-max-microvolt = <1800000>;
104 + regulator-boot-on;
105 + regulator-always-on;
106 + };
107 +
108 + reg_3p3v: regulator-3p3v {
109 + compatible = "regulator-fixed";
110 + regulator-name = "fixed-3.3V";
111 + regulator-min-microvolt = <3300000>;
112 + regulator-max-microvolt = <3300000>;
113 + regulator-boot-on;
114 + regulator-always-on;
115 + };
116 +
117 + reg_5v: regulator-5v {
118 + compatible = "regulator-fixed";
119 + regulator-name = "fixed-5V";
120 + regulator-min-microvolt = <5000000>;
121 + regulator-max-microvolt = <5000000>;
122 + regulator-boot-on;
123 + regulator-always-on;
124 + };
125 +
126 + gpio-keys {
127 + compatible = "gpio-keys";
128 + pinctrl-names = "default";
129 + pinctrl-0 = <&key_pins_a>;
130 +
131 + factory {
132 + label = "factory";
133 + linux,code = <KEY_RESTART>;
134 + gpios = <&pio 256 GPIO_ACTIVE_LOW>;
135 + };
136 + };
137 +
138 + leds {
139 + compatible = "gpio-leds";
140 + pinctrl-names = "default";
141 + pinctrl-0 = <&led_pins_unielec>;
142 +
143 + led3 {
144 + label = "u7623-01:green:led3";
145 + gpios = <&pio 14 GPIO_ACTIVE_LOW>;
146 + default-state = "off";
147 + };
148 +
149 + led4 {
150 + label = "u7623-01:green:led4";
151 + gpios = <&pio 15 GPIO_ACTIVE_LOW>;
152 + default-state = "off";
153 + };
154 + };
155 +
156 + memory@80000000 {
157 + reg = <0 0x80000000 0 0x40000000>;
158 + };
159 +
160 + mt7530: switch@0 {
161 + compatible = "mediatek,mt7530";
162 + #address-cells = <1>;
163 + #size-cells = <0>;
164 + };
165 +};
166 +
167 +&crypto {
168 + status = "okay";
169 +};
170 +
171 +&eth {
172 + status = "okay";
173 +
174 + gmac0: mac@0 {
175 + compatible = "mediatek,eth-mac";
176 + reg = <0>;
177 + phy-mode = "trgmii";
178 +
179 + fixed-link {
180 + speed = <1000>;
181 + full-duplex;
182 + pause;
183 + };
184 + };
185 +
186 + mdio: mdio-bus {
187 + #address-cells = <1>;
188 + #size-cells = <0>;
189 + phy5: ethernet-phy@5 {
190 + reg = <5>;
191 + phy-mode = "rgmii-rxid";
192 + };
193 + };
194 +};
195 +
196 +&mt7530 {
197 + compatible = "mediatek,mt7530";
198 + #address-cells = <1>;
199 + #size-cells = <0>;
200 + reg = <0>;
201 + pinctrl-names = "default";
202 + mediatek,mcm;
203 + resets = <&ethsys 2>;
204 + reset-names = "mcm";
205 + core-supply = <&mt6323_vpa_reg>;
206 + io-supply = <&mt6323_vemc3v3_reg>;
207 +
208 + dsa,mii-bus = <&mdio>;
209 +
210 + ports {
211 + #address-cells = <1>;
212 + #size-cells = <0>;
213 + reg = <0>;
214 +
215 + port@0 {
216 + reg = <0>;
217 + label = "lan0";
218 + cpu = <&cpu_port0>;
219 + };
220 +
221 + port@1 {
222 + reg = <1>;
223 + label = "lan1";
224 + cpu = <&cpu_port0>;
225 + };
226 +
227 + port@2 {
228 + reg = <2>;
229 + label = "lan2";
230 + cpu = <&cpu_port0>;
231 + };
232 +
233 + port@3 {
234 + reg = <3>;
235 + label = "lan3";
236 + cpu = <&cpu_port0>;
237 + };
238 +
239 + port@4 {
240 + reg = <4>;
241 + label = "wan";
242 + cpu = <&cpu_port0>;
243 + };
244 +
245 + cpu_port0: port@6 {
246 + reg = <6>;
247 + label = "cpu";
248 + ethernet = <&gmac0>;
249 + phy-mode = "trgmii";
250 +
251 + fixed-link {
252 + speed = <1000>;
253 + full-duplex;
254 + };
255 + };
256 + };
257 +};
258 +
259 +&mmc0 {
260 + pinctrl-names = "default", "state_uhs";
261 + pinctrl-0 = <&mmc0_pins_default>;
262 + pinctrl-1 = <&mmc0_pins_uhs>;
263 + status = "okay";
264 + bus-width = <8>;
265 + max-frequency = <50000000>;
266 + cap-mmc-highspeed;
267 + vmmc-supply = <&reg_3p3v>;
268 + vqmmc-supply = <&reg_1p8v>;
269 + non-removable;
270 +};
271 +
272 +&pio {
273 + key_pins_a: keys-alt {
274 + pins-keys {
275 + pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>,
276 + <MT7623_PIN_257_GPIO257_FUNC_GPIO257>;
277 + input-enable;
278 + };
279 + };
280 +
281 + led_pins_unielec: leds-unielec {
282 + pins-leds {
283 + pinmux = <MT7623_PIN_14_GPIO14_FUNC_GPIO14>,
284 + <MT7623_PIN_15_GPIO15_FUNC_GPIO15>;
285 + };
286 + };
287 +
288 + mmc0_pins_default: mmc0default {
289 + pins_cmd_dat {
290 + pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
291 + <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
292 + <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
293 + <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
294 + <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
295 + <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
296 + <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
297 + <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
298 + <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
299 + input-enable;
300 + bias-pull-up;
301 + };
302 +
303 + pins_clk {
304 + pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
305 + bias-pull-down;
306 + };
307 +
308 + pins_rst {
309 + pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
310 + bias-pull-up;
311 + };
312 + };
313 +
314 + mmc0_pins_uhs: mmc0 {
315 + pins_cmd_dat {
316 + pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
317 + <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
318 + <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
319 + <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
320 + <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
321 + <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
322 + <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
323 + <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
324 + <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
325 + input-enable;
326 + drive-strength = <MTK_DRIVE_2mA>;
327 + bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
328 + };
329 +
330 + pins_clk {
331 + pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
332 + drive-strength = <MTK_DRIVE_2mA>;
333 + bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
334 + };
335 +
336 + pins_rst {
337 + pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
338 + bias-pull-up;
339 + };
340 + };
341 +
342 + pwm_pins_a: pwm@0 {
343 + pins_pwm {
344 + pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>,
345 + <MT7623_PIN_204_PWM1_FUNC_PWM1>,
346 + <MT7623_PIN_205_PWM2_FUNC_PWM2>,
347 + <MT7623_PIN_206_PWM3_FUNC_PWM3>,
348 + <MT7623_PIN_207_PWM4_FUNC_PWM4>;
349 + };
350 + };
351 +
352 + uart2_pins_b: uart@2 {
353 + pins_dat {
354 + pinmux = <MT7623_PIN_200_URXD2_FUNC_URXD2>,
355 + <MT7623_PIN_201_UTXD2_FUNC_UTXD2>;
356 + };
357 + };
358 +
359 + pcie_default: pcie_pin_default {
360 + pins_cmd_dat {
361 + pinmux = <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>,
362 + <MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>;
363 + bias-disable;
364 + };
365 + };
366 +};
367 +
368 +&pwm {
369 + pinctrl-names = "default";
370 + pinctrl-0 = <&pwm_pins_a>;
371 + status = "okay";
372 +};
373 +
374 +&pwrap {
375 + mt6323 {
376 + mt6323led: led {
377 + compatible = "mediatek,mt6323-led";
378 + #address-cells = <1>;
379 + #size-cells = <0>;
380 +
381 + led@0 {
382 + reg = <0>;
383 + label = "led0";
384 + default-state = "off";
385 + };
386 + };
387 + };
388 +};
389 +
390 +&uart2 {
391 + pinctrl-names = "default";
392 + pinctrl-0 = <&uart2_pins_b>;
393 + status = "okay";
394 +};
395 +
396 +&usb1 {
397 + vusb33-supply = <&reg_3p3v>;
398 + vbus-supply = <&reg_3p3v>;
399 + status = "okay";
400 +};
401 +
402 +&u3phy1 {
403 + status = "okay";
404 +};
405 +
406 +&u3phy2 {
407 + status = "okay";
408 + mediatek,phy-switch = <&hifsys>;
409 +};
410 +
411 +&pcie {
412 + pinctrl-names = "default";
413 + pinctrl-0 = <&pcie_default>;
414 + status = "okay";
415 +
416 + pcie@1,0 {
417 + status = "okay";
418 + };
419 +
420 + pcie@2,0 {
421 + status = "okay";
422 + };
423 +};
424 +
425 +&pcie1_phy {
426 + status = "okay";
427 +};
428 +
429 --
430 2.14.1
431