1 From 2fcbc15da2f13164e0851b9c7fae290249f0b44d Mon Sep 17 00:00:00 2001
2 From: Shunli Wang <shunli.wang@mediatek.com>
3 Date: Tue, 5 Jan 2016 14:30:19 +0800
4 Subject: [PATCH 08/53] clk: mediatek: Add dt-bindings for MT2701 clocks
6 Add MT2701 clock dt-bindings, include topckgen, apmixedsys,
7 infracfg, pericfg and subsystem clocks.
9 Signed-off-by: Shunli Wang <shunli.wang@mediatek.com>
10 Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
12 include/dt-bindings/clock/mt2701-clk.h | 481 ++++++++++++++++++++++++++++++++
13 1 file changed, 481 insertions(+)
14 create mode 100644 include/dt-bindings/clock/mt2701-clk.h
16 diff --git a/include/dt-bindings/clock/mt2701-clk.h b/include/dt-bindings/clock/mt2701-clk.h
18 index 0000000..50972d1
20 +++ b/include/dt-bindings/clock/mt2701-clk.h
23 + * Copyright (c) 2014 MediaTek Inc.
24 + * Author: Shunli Wang <shunli.wang@mediatek.com>
26 + * This program is free software; you can redistribute it and/or modify
27 + * it under the terms of the GNU General Public License version 2 as
28 + * published by the Free Software Foundation.
30 + * This program is distributed in the hope that it will be useful,
31 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
32 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33 + * GNU General Public License for more details.
36 +#ifndef _DT_BINDINGS_CLK_MT2701_H
37 +#define _DT_BINDINGS_CLK_MT2701_H
40 +#define CLK_TOP_SYSPLL 1
41 +#define CLK_TOP_SYSPLL_D2 2
42 +#define CLK_TOP_SYSPLL_D3 3
43 +#define CLK_TOP_SYSPLL_D5 4
44 +#define CLK_TOP_SYSPLL_D7 5
45 +#define CLK_TOP_SYSPLL1_D2 6
46 +#define CLK_TOP_SYSPLL1_D4 7
47 +#define CLK_TOP_SYSPLL1_D8 8
48 +#define CLK_TOP_SYSPLL1_D16 9
49 +#define CLK_TOP_SYSPLL2_D2 10
50 +#define CLK_TOP_SYSPLL2_D4 11
51 +#define CLK_TOP_SYSPLL2_D8 12
52 +#define CLK_TOP_SYSPLL3_D2 13
53 +#define CLK_TOP_SYSPLL3_D4 14
54 +#define CLK_TOP_SYSPLL4_D2 15
55 +#define CLK_TOP_SYSPLL4_D4 16
56 +#define CLK_TOP_UNIVPLL 17
57 +#define CLK_TOP_UNIVPLL_D2 18
58 +#define CLK_TOP_UNIVPLL_D3 19
59 +#define CLK_TOP_UNIVPLL_D5 20
60 +#define CLK_TOP_UNIVPLL_D7 21
61 +#define CLK_TOP_UNIVPLL_D26 22
62 +#define CLK_TOP_UNIVPLL_D52 23
63 +#define CLK_TOP_UNIVPLL_D108 24
64 +#define CLK_TOP_USB_PHY48M 25
65 +#define CLK_TOP_UNIVPLL1_D2 26
66 +#define CLK_TOP_UNIVPLL1_D4 27
67 +#define CLK_TOP_UNIVPLL1_D8 28
68 +#define CLK_TOP_UNIVPLL2_D2 29
69 +#define CLK_TOP_UNIVPLL2_D4 30
70 +#define CLK_TOP_UNIVPLL2_D8 31
71 +#define CLK_TOP_UNIVPLL2_D16 32
72 +#define CLK_TOP_UNIVPLL2_D32 33
73 +#define CLK_TOP_UNIVPLL3_D2 34
74 +#define CLK_TOP_UNIVPLL3_D4 35
75 +#define CLK_TOP_UNIVPLL3_D8 36
76 +#define CLK_TOP_MSDCPLL 37
77 +#define CLK_TOP_MSDCPLL_D2 38
78 +#define CLK_TOP_MSDCPLL_D4 39
79 +#define CLK_TOP_MSDCPLL_D8 40
80 +#define CLK_TOP_MMPLL 41
81 +#define CLK_TOP_MMPLL_D2 42
82 +#define CLK_TOP_DMPLL 43
83 +#define CLK_TOP_DMPLL_D2 44
84 +#define CLK_TOP_DMPLL_D4 45
85 +#define CLK_TOP_DMPLL_X2 46
86 +#define CLK_TOP_TVDPLL 47
87 +#define CLK_TOP_TVDPLL_D2 48
88 +#define CLK_TOP_TVDPLL_D4 49
89 +#define CLK_TOP_TVD2PLL 50
90 +#define CLK_TOP_TVD2PLL_D2 51
91 +#define CLK_TOP_HADDS2PLL_98M 52
92 +#define CLK_TOP_HADDS2PLL_294M 53
93 +#define CLK_TOP_HADDS2_FB 54
94 +#define CLK_TOP_MIPIPLL_D2 55
95 +#define CLK_TOP_MIPIPLL_D4 56
96 +#define CLK_TOP_HDMIPLL 57
97 +#define CLK_TOP_HDMIPLL_D2 58
98 +#define CLK_TOP_HDMIPLL_D3 59
99 +#define CLK_TOP_HDMI_SCL_RX 60
100 +#define CLK_TOP_HDMI_0_PIX340M 61
101 +#define CLK_TOP_HDMI_0_DEEP340M 62
102 +#define CLK_TOP_HDMI_0_PLL340M 63
103 +#define CLK_TOP_AUD1PLL_98M 64
104 +#define CLK_TOP_AUD2PLL_90M 65
105 +#define CLK_TOP_AUDPLL 66
106 +#define CLK_TOP_AUDPLL_D4 67
107 +#define CLK_TOP_AUDPLL_D8 68
108 +#define CLK_TOP_AUDPLL_D16 69
109 +#define CLK_TOP_AUDPLL_D24 70
110 +#define CLK_TOP_ETHPLL_500M 71
111 +#define CLK_TOP_VDECPLL 72
112 +#define CLK_TOP_VENCPLL 73
113 +#define CLK_TOP_MIPIPLL 74
114 +#define CLK_TOP_ARMPLL_1P3G 75
116 +#define CLK_TOP_MM_SEL 76
117 +#define CLK_TOP_DDRPHYCFG_SEL 77
118 +#define CLK_TOP_MEM_SEL 78
119 +#define CLK_TOP_AXI_SEL 79
120 +#define CLK_TOP_CAMTG_SEL 80
121 +#define CLK_TOP_MFG_SEL 81
122 +#define CLK_TOP_VDEC_SEL 82
123 +#define CLK_TOP_PWM_SEL 83
124 +#define CLK_TOP_MSDC30_0_SEL 84
125 +#define CLK_TOP_USB20_SEL 85
126 +#define CLK_TOP_SPI0_SEL 86
127 +#define CLK_TOP_UART_SEL 87
128 +#define CLK_TOP_AUDINTBUS_SEL 88
129 +#define CLK_TOP_AUDIO_SEL 89
130 +#define CLK_TOP_MSDC30_2_SEL 90
131 +#define CLK_TOP_MSDC30_1_SEL 91
132 +#define CLK_TOP_DPI1_SEL 92
133 +#define CLK_TOP_DPI0_SEL 93
134 +#define CLK_TOP_SCP_SEL 94
135 +#define CLK_TOP_PMICSPI_SEL 95
136 +#define CLK_TOP_APLL_SEL 96
137 +#define CLK_TOP_HDMI_SEL 97
138 +#define CLK_TOP_TVE_SEL 98
139 +#define CLK_TOP_EMMC_HCLK_SEL 99
140 +#define CLK_TOP_NFI2X_SEL 100
141 +#define CLK_TOP_RTC_SEL 101
142 +#define CLK_TOP_OSD_SEL 102
143 +#define CLK_TOP_NR_SEL 103
144 +#define CLK_TOP_DI_SEL 104
145 +#define CLK_TOP_FLASH_SEL 105
146 +#define CLK_TOP_ASM_M_SEL 106
147 +#define CLK_TOP_ASM_I_SEL 107
148 +#define CLK_TOP_INTDIR_SEL 108
149 +#define CLK_TOP_HDMIRX_BIST_SEL 109
150 +#define CLK_TOP_ETHIF_SEL 110
151 +#define CLK_TOP_MS_CARD_SEL 111
152 +#define CLK_TOP_ASM_H_SEL 112
153 +#define CLK_TOP_SPI1_SEL 113
154 +#define CLK_TOP_CMSYS_SEL 114
155 +#define CLK_TOP_MSDC30_3_SEL 115
156 +#define CLK_TOP_HDMIRX26_24_SEL 116
157 +#define CLK_TOP_AUD2DVD_SEL 117
158 +#define CLK_TOP_8BDAC_SEL 118
159 +#define CLK_TOP_SPI2_SEL 119
160 +#define CLK_TOP_AUD_MUX1_SEL 120
161 +#define CLK_TOP_AUD_MUX2_SEL 121
162 +#define CLK_TOP_AUDPLL_MUX_SEL 122
163 +#define CLK_TOP_AUD_K1_SRC_SEL 123
164 +#define CLK_TOP_AUD_K2_SRC_SEL 124
165 +#define CLK_TOP_AUD_K3_SRC_SEL 125
166 +#define CLK_TOP_AUD_K4_SRC_SEL 126
167 +#define CLK_TOP_AUD_K5_SRC_SEL 127
168 +#define CLK_TOP_AUD_K6_SRC_SEL 128
169 +#define CLK_TOP_PADMCLK_SEL 129
170 +#define CLK_TOP_AUD_EXTCK1_DIV 130
171 +#define CLK_TOP_AUD_EXTCK2_DIV 131
172 +#define CLK_TOP_AUD_MUX1_DIV 132
173 +#define CLK_TOP_AUD_MUX2_DIV 133
174 +#define CLK_TOP_AUD_K1_SRC_DIV 134
175 +#define CLK_TOP_AUD_K2_SRC_DIV 135
176 +#define CLK_TOP_AUD_K3_SRC_DIV 136
177 +#define CLK_TOP_AUD_K4_SRC_DIV 137
178 +#define CLK_TOP_AUD_K5_SRC_DIV 138
179 +#define CLK_TOP_AUD_K6_SRC_DIV 139
180 +#define CLK_TOP_AUD_I2S1_MCLK 140
181 +#define CLK_TOP_AUD_I2S2_MCLK 141
182 +#define CLK_TOP_AUD_I2S3_MCLK 142
183 +#define CLK_TOP_AUD_I2S4_MCLK 143
184 +#define CLK_TOP_AUD_I2S5_MCLK 144
185 +#define CLK_TOP_AUD_I2S6_MCLK 145
186 +#define CLK_TOP_AUD_48K_TIMING 146
187 +#define CLK_TOP_AUD_44K_TIMING 147
189 +#define CLK_TOP_32K_INTERNAL 148
190 +#define CLK_TOP_32K_EXTERNAL 149
191 +#define CLK_TOP_CLK26M_D8 150
192 +#define CLK_TOP_8BDAC 151
193 +#define CLK_TOP_WBG_DIG_416M 152
194 +#define CLK_TOP_DPI 153
195 +#define CLK_TOP_HDMITX_CLKDIG_CTS 154
196 +#define CLK_TOP_NR 155
200 +#define CLK_APMIXED_ARMPLL 1
201 +#define CLK_APMIXED_MAINPLL 2
202 +#define CLK_APMIXED_UNIVPLL 3
203 +#define CLK_APMIXED_MMPLL 4
204 +#define CLK_APMIXED_MSDCPLL 5
205 +#define CLK_APMIXED_TVDPLL 6
206 +#define CLK_APMIXED_AUD1PLL 7
207 +#define CLK_APMIXED_TRGPLL 8
208 +#define CLK_APMIXED_ETHPLL 9
209 +#define CLK_APMIXED_VDECPLL 10
210 +#define CLK_APMIXED_HADDS2PLL 11
211 +#define CLK_APMIXED_AUD2PLL 12
212 +#define CLK_APMIXED_TVD2PLL 13
213 +#define CLK_APMIXED_NR 14
217 +#define CLK_DDRPHY_VENCPLL 1
218 +#define CLK_DDRPHY_NR 2
222 +#define CLK_INFRA_DBG 1
223 +#define CLK_INFRA_SMI 2
224 +#define CLK_INFRA_QAXI_CM4 3
225 +#define CLK_INFRA_AUD_SPLIN_B 4
226 +#define CLK_INFRA_AUDIO 5
227 +#define CLK_INFRA_EFUSE 6
228 +#define CLK_INFRA_L2C_SRAM 7
229 +#define CLK_INFRA_M4U 8
230 +#define CLK_INFRA_CONNMCU 9
231 +#define CLK_INFRA_TRNG 10
232 +#define CLK_INFRA_RAMBUFIF 11
233 +#define CLK_INFRA_CPUM 12
234 +#define CLK_INFRA_KP 13
235 +#define CLK_INFRA_CEC 14
236 +#define CLK_INFRA_IRRX 15
237 +#define CLK_INFRA_PMICSPI 16
238 +#define CLK_INFRA_PMICWRAP 17
239 +#define CLK_INFRA_DDCCI 18
240 +#define CLK_INFRA_CLK_13M 19
241 +#define CLK_INFRA_NR 20
245 +#define CLK_PERI_NFI 1
246 +#define CLK_PERI_THERM 2
247 +#define CLK_PERI_PWM1 3
248 +#define CLK_PERI_PWM2 4
249 +#define CLK_PERI_PWM3 5
250 +#define CLK_PERI_PWM4 6
251 +#define CLK_PERI_PWM5 7
252 +#define CLK_PERI_PWM6 8
253 +#define CLK_PERI_PWM7 9
254 +#define CLK_PERI_PWM 10
255 +#define CLK_PERI_USB0 11
256 +#define CLK_PERI_USB1 12
257 +#define CLK_PERI_AP_DMA 13
258 +#define CLK_PERI_MSDC30_0 14
259 +#define CLK_PERI_MSDC30_1 15
260 +#define CLK_PERI_MSDC30_2 16
261 +#define CLK_PERI_MSDC30_3 17
262 +#define CLK_PERI_MSDC50_3 18
263 +#define CLK_PERI_NLI 19
264 +#define CLK_PERI_UART0 20
265 +#define CLK_PERI_UART1 21
266 +#define CLK_PERI_UART2 22
267 +#define CLK_PERI_UART3 23
268 +#define CLK_PERI_BTIF 24
269 +#define CLK_PERI_I2C0 25
270 +#define CLK_PERI_I2C1 26
271 +#define CLK_PERI_I2C2 27
272 +#define CLK_PERI_I2C3 28
273 +#define CLK_PERI_AUXADC 29
274 +#define CLK_PERI_SPI0 30
275 +#define CLK_PERI_ETH 31
276 +#define CLK_PERI_USB0_MCU 32
278 +#define CLK_PERI_USB1_MCU 33
279 +#define CLK_PERI_USB_SLV 34
280 +#define CLK_PERI_GCPU 35
281 +#define CLK_PERI_NFI_ECC 36
282 +#define CLK_PERI_NFI_PAD 37
283 +#define CLK_PERI_FLASH 38
284 +#define CLK_PERI_HOST89_INT 39
285 +#define CLK_PERI_HOST89_SPI 40
286 +#define CLK_PERI_HOST89_DVD 41
287 +#define CLK_PERI_SPI1 42
288 +#define CLK_PERI_SPI2 43
289 +#define CLK_PERI_FCI 44
291 +#define CLK_PERI_UART0_SEL 45
292 +#define CLK_PERI_UART1_SEL 46
293 +#define CLK_PERI_UART2_SEL 47
294 +#define CLK_PERI_UART3_SEL 48
295 +#define CLK_PERI_NR 49
299 +#define CLK_AUD_AFE 1
300 +#define CLK_AUD_LRCK_DETECT 2
301 +#define CLK_AUD_I2S 3
302 +#define CLK_AUD_APLL_TUNER 4
303 +#define CLK_AUD_HDMI 5
304 +#define CLK_AUD_SPDF 6
305 +#define CLK_AUD_SPDF2 7
306 +#define CLK_AUD_APLL 8
307 +#define CLK_AUD_TML 9
308 +#define CLK_AUD_AHB_IDLE_EXT 10
309 +#define CLK_AUD_AHB_IDLE_INT 11
311 +#define CLK_AUD_I2SIN1 12
312 +#define CLK_AUD_I2SIN2 13
313 +#define CLK_AUD_I2SIN3 14
314 +#define CLK_AUD_I2SIN4 15
315 +#define CLK_AUD_I2SIN5 16
316 +#define CLK_AUD_I2SIN6 17
317 +#define CLK_AUD_I2SO1 18
318 +#define CLK_AUD_I2SO2 19
319 +#define CLK_AUD_I2SO3 20
320 +#define CLK_AUD_I2SO4 21
321 +#define CLK_AUD_I2SO5 22
322 +#define CLK_AUD_I2SO6 23
323 +#define CLK_AUD_ASRCI1 24
324 +#define CLK_AUD_ASRCI2 25
325 +#define CLK_AUD_ASRCO1 26
326 +#define CLK_AUD_ASRCO2 27
327 +#define CLK_AUD_ASRC11 28
328 +#define CLK_AUD_ASRC12 29
329 +#define CLK_AUD_HDMIRX 30
330 +#define CLK_AUD_INTDIR 31
331 +#define CLK_AUD_A1SYS 32
332 +#define CLK_AUD_A2SYS 33
333 +#define CLK_AUD_AFE_CONN 34
334 +#define CLK_AUD_AFE_PCMIF 35
335 +#define CLK_AUD_AFE_MRGIF 36
337 +#define CLK_AUD_MMIF_UL1 37
338 +#define CLK_AUD_MMIF_UL2 38
339 +#define CLK_AUD_MMIF_UL3 39
340 +#define CLK_AUD_MMIF_UL4 40
341 +#define CLK_AUD_MMIF_UL5 41
342 +#define CLK_AUD_MMIF_UL6 42
343 +#define CLK_AUD_MMIF_DL1 43
344 +#define CLK_AUD_MMIF_DL2 44
345 +#define CLK_AUD_MMIF_DL3 45
346 +#define CLK_AUD_MMIF_DL4 46
347 +#define CLK_AUD_MMIF_DL5 47
348 +#define CLK_AUD_MMIF_DL6 48
349 +#define CLK_AUD_MMIF_DLMCH 49
350 +#define CLK_AUD_MMIF_ARB1 50
351 +#define CLK_AUD_MMIF_AWB1 51
352 +#define CLK_AUD_MMIF_AWB2 52
353 +#define CLK_AUD_MMIF_DAI 53
355 +#define CLK_AUD_DMIC1 54
356 +#define CLK_AUD_DMIC2 55
357 +#define CLK_AUD_ASRCI3 56
358 +#define CLK_AUD_ASRCI4 57
359 +#define CLK_AUD_ASRCI5 58
360 +#define CLK_AUD_ASRCI6 59
361 +#define CLK_AUD_ASRCO3 60
362 +#define CLK_AUD_ASRCO4 61
363 +#define CLK_AUD_ASRCO5 62
364 +#define CLK_AUD_ASRCO6 63
365 +#define CLK_AUD_MEM_ASRC1 64
366 +#define CLK_AUD_MEM_ASRC2 65
367 +#define CLK_AUD_MEM_ASRC3 66
368 +#define CLK_AUD_MEM_ASRC4 67
369 +#define CLK_AUD_MEM_ASRC5 68
370 +#define CLK_AUD_DSD_ENC 69
371 +#define CLK_AUD_ASRC_BRG 70
372 +#define CLK_AUD_NR 71
376 +#define CLK_MM_SMI_COMMON 1
377 +#define CLK_MM_SMI_LARB0 2
378 +#define CLK_MM_CMDQ 3
379 +#define CLK_MM_MUTEX 4
380 +#define CLK_MM_DISP_COLOR 5
381 +#define CLK_MM_DISP_BLS 6
382 +#define CLK_MM_DISP_WDMA 7
383 +#define CLK_MM_DISP_RDMA 8
384 +#define CLK_MM_DISP_OVL 9
385 +#define CLK_MM_MDP_TDSHP 10
386 +#define CLK_MM_MDP_WROT 11
387 +#define CLK_MM_MDP_WDMA 12
388 +#define CLK_MM_MDP_RSZ1 13
389 +#define CLK_MM_MDP_RSZ0 14
390 +#define CLK_MM_MDP_RDMA 15
391 +#define CLK_MM_MDP_BLS_26M 16
392 +#define CLK_MM_CAM_MDP 17
393 +#define CLK_MM_FAKE_ENG 18
394 +#define CLK_MM_MUTEX_32K 19
395 +#define CLK_MM_DISP_RDMA1 20
396 +#define CLK_MM_DISP_UFOE 21
398 +#define CLK_MM_DSI_ENGINE 22
399 +#define CLK_MM_DSI_DIG 23
400 +#define CLK_MM_DPI_DIGL 24
401 +#define CLK_MM_DPI_ENGINE 25
402 +#define CLK_MM_DPI1_DIGL 26
403 +#define CLK_MM_DPI1_ENGINE 27
404 +#define CLK_MM_TVE_OUTPUT 28
405 +#define CLK_MM_TVE_INPUT 29
406 +#define CLK_MM_HDMI_PIXEL 30
407 +#define CLK_MM_HDMI_PLL 31
408 +#define CLK_MM_HDMI_AUDIO 32
409 +#define CLK_MM_HDMI_SPDIF 33
410 +#define CLK_MM_TVE_FMM 34
411 +#define CLK_MM_NR 35
415 +#define CLK_IMG_SMI_COMM 1
416 +#define CLK_IMG_RESZ 2
417 +#define CLK_IMG_JPGDEC 3
418 +#define CLK_IMG_VENC_LT 4
419 +#define CLK_IMG_VENC 5
420 +#define CLK_IMG_NR 6
424 +#define CLK_VDEC_CKGEN 1
425 +#define CLK_VDEC_LARB 2
426 +#define CLK_VDEC_NR 3
430 +#define CLK_HIFSYS_USB0PHY 1
431 +#define CLK_HIFSYS_USB1PHY 2
432 +#define CLK_HIFSYS_PCIE0 3
433 +#define CLK_HIFSYS_PCIE1 4
434 +#define CLK_HIFSYS_PCIE2 5
435 +#define CLK_HIFSYS_NR 6
438 +#define CLK_ETHSYS_HSDMA 1
439 +#define CLK_ETHSYS_ESW 2
440 +#define CLK_ETHSYS_GP2 3
441 +#define CLK_ETHSYS_GP1 4
442 +#define CLK_ETHSYS_PCM 5
443 +#define CLK_ETHSYS_GDMA 6
444 +#define CLK_ETHSYS_I2S 7
445 +#define CLK_ETHSYS_CRYPTO 8
446 +#define CLK_ETHSYS_NR 9
450 +#define CLK_BDP_BRG_BA 1
451 +#define CLK_BDP_BRG_DRAM 2
452 +#define CLK_BDP_LARB_DRAM 3
453 +#define CLK_BDP_WR_VDI_PXL 4
454 +#define CLK_BDP_WR_VDI_DRAM 5
455 +#define CLK_BDP_WR_B 6
456 +#define CLK_BDP_DGI_IN 7
457 +#define CLK_BDP_DGI_OUT 8
458 +#define CLK_BDP_FMT_MAST_27 9
459 +#define CLK_BDP_FMT_B 10
460 +#define CLK_BDP_OSD_B 11
461 +#define CLK_BDP_OSD_DRAM 12
462 +#define CLK_BDP_OSD_AGENT 13
463 +#define CLK_BDP_OSD_PXL 14
464 +#define CLK_BDP_RLE_B 15
465 +#define CLK_BDP_RLE_AGENT 16
466 +#define CLK_BDP_RLE_DRAM 17
467 +#define CLK_BDP_F27M 18
468 +#define CLK_BDP_F27M_VDOUT 19
469 +#define CLK_BDP_F27_74_74 20
470 +#define CLK_BDP_F2FS 21
471 +#define CLK_BDP_F2FS74_148 22
472 +#define CLK_BDP_FB 23
473 +#define CLK_BDP_VDO_DRAM 24
474 +#define CLK_BDP_VDO_2FS 25
475 +#define CLK_BDP_VDO_B 26
476 +#define CLK_BDP_WR_DI_PXL 27
477 +#define CLK_BDP_WR_DI_DRAM 28
478 +#define CLK_BDP_WR_DI_B 29
479 +#define CLK_BDP_NR_PXL 30
480 +#define CLK_BDP_NR_DRAM 31
481 +#define CLK_BDP_NR_B 32
483 +#define CLK_BDP_RX_F 33
484 +#define CLK_BDP_RX_X 34
485 +#define CLK_BDP_RXPDT 35
486 +#define CLK_BDP_RX_CSCL_N 36
487 +#define CLK_BDP_RX_CSCL 37
488 +#define CLK_BDP_RX_DDCSCL_N 38
489 +#define CLK_BDP_RX_DDCSCL 39
490 +#define CLK_BDP_RX_VCO 40
491 +#define CLK_BDP_RX_DP 41
492 +#define CLK_BDP_RX_P 42
493 +#define CLK_BDP_RX_M 43
494 +#define CLK_BDP_RX_PLL 44
495 +#define CLK_BDP_BRG_RT_B 45
496 +#define CLK_BDP_BRG_RT_DRAM 46
497 +#define CLK_BDP_LARBRT_DRAM 47
498 +#define CLK_BDP_TMDS_SYN 48
499 +#define CLK_BDP_HDMI_MON 49
500 +#define CLK_BDP_NR 50
502 +#endif /* _DT_BINDINGS_CLK_MT2701_H */
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