target/linux/mediatek/patches-4.4/0010-reset-mediatek-mt2701-reset-controller-dt-binding-fi.patch

   1 From 8d134cbe750b59d15c591622d81e2e9daa09f0c4 Mon Sep 17 00:00:00 2001
   2 From: Shunli Wang <shunli.wang@mediatek.com>
   3 Date: Tue, 5 Jan 2016 14:30:21 +0800
   4 Subject: [PATCH 10/90] reset: mediatek: mt2701 reset controller dt-binding
   5  file
   6
   7 Dt-binding file about reset controller is used to provide
   8 kinds of definition, which is referenced by dts file and
   9 IC-specified reset controller driver code.
  10
  11 Signed-off-by: Shunli Wang <shunli.wang@mediatek.com>
  12 ---
  13  .../dt-bindings/reset-controller/mt2701-resets.h   |   74 ++++++++++++++++++++
  14  1 file changed, 74 insertions(+)
  15  create mode 100644 include/dt-bindings/reset-controller/mt2701-resets.h
  16
  17 diff --git a/include/dt-bindings/reset-controller/mt2701-resets.h b/include/dt-bindings/reset-controller/mt2701-resets.h
  18 new file mode 100644
  19 index 0000000..00efeb0
  20 --- /dev/null
  21 +++ b/include/dt-bindings/reset-controller/mt2701-resets.h
  22 @@ -0,0 +1,74 @@
  23 +/*
  24 + * Copyright (c) 2015 MediaTek, Shunli Wang <shunli.wang@mediatek.com>
  25 + *
  26 + * This program is free software; you can redistribute it and/or modify
  27 + * it under the terms of the GNU General Public License version 2 as
  28 + * published by the Free Software Foundation.
  29 + *
  30 + * This program is distributed in the hope that it will be useful,
  31 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  32 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  33 + * GNU General Public License for more details.
  34 + */
  35 +
  36 +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT2701
  37 +#define _DT_BINDINGS_RESET_CONTROLLER_MT2701
  38 +
  39 +/* INFRACFG resets */
  40 +#define MT2701_INFRA_EMI_REG_RST               0
  41 +#define MT2701_INFRA_DRAMC0_A0_RST             1
  42 +#define MT2701_INFRA_FHCTL_RST                 2
  43 +#define MT2701_INFRA_APCIRQ_EINT_RST           3
  44 +#define MT2701_INFRA_APXGPT_RST                        4
  45 +#define MT2701_INFRA_SCPSYS_RST                        5
  46 +#define MT2701_INFRA_KP_RST                    6
  47 +#define MT2701_INFRA_PMIC_WRAP_RST             7
  48 +#define MT2701_INFRA_MIPI_RST                  8
  49 +#define MT2701_INFRA_IRRX_RST                  9
  50 +#define MT2701_INFRA_CEC_RST                   10
  51 +#define MT2701_INFRA_EMI_RST                   32
  52 +#define MT2701_INFRA_DRAMC0_RST                        34
  53 +#define MT2701_INFRA_TRNG_RST                  37
  54 +#define MT2701_INFRA_SYSIRQ_RST                        38
  55 +
  56 +/*  PERICFG resets */
  57 +#define MT2701_PERI_UART0_SW_RST               0
  58 +#define MT2701_PERI_UART1_SW_RST               1
  59 +#define MT2701_PERI_UART2_SW_RST               2
  60 +#define MT2701_PERI_UART3_SW_RST               3
  61 +#define MT2701_PERI_GCPU_SW_RST                        5
  62 +#define MT2701_PERI_BTIF_SW_RST                        6
  63 +#define MT2701_PERI_PWM_SW_RST                 8
  64 +#define MT2701_PERI_AUXADC_SW_RST              10
  65 +#define MT2701_PERI_DMA_SW_RST                 11
  66 +#define MT2701_PERI_NFI_SW_RST                 14
  67 +#define MT2701_PERI_NLI_SW_RST                 15
  68 +#define MT2701_PERI_THERM_SW_RST               16
  69 +#define MT2701_PERI_MSDC2_SW_RST               17
  70 +#define MT2701_PERI_MSDC0_SW_RST               19
  71 +#define MT2701_PERI_MSDC1_SW_RST               20
  72 +#define MT2701_PERI_I2C0_SW_RST                        22
  73 +#define MT2701_PERI_I2C1_SW_RST                        23
  74 +#define MT2701_PERI_I2C2_SW_RST                        24
  75 +#define MT2701_PERI_I2C3_SW_RST                        25
  76 +#define MT2701_PERI_USB_SW_RST                 28
  77 +#define MT2701_PERI_ETH_SW_RST                 29
  78 +#define MT2701_PERI_SPI0_SW_RST                        33
  79 +
  80 +/* TOPRGU resets */
  81 +#define MT2701_TOPRGU_INFRA_RST                        0
  82 +#define MT2701_TOPRGU_MM_RST                   1
  83 +#define MT2701_TOPRGU_MFG_RST                  2
  84 +#define MT2701_TOPRGU_ETHDMA_RST               3
  85 +#define MT2701_TOPRGU_VDEC_RST                 4
  86 +#define MT2701_TOPRGU_VENC_IMG_RST             5
  87 +#define MT2701_TOPRGU_DDRPHY_RST               6
  88 +#define MT2701_TOPRGU_MD_RST                   7
  89 +#define MT2701_TOPRGU_INFRA_AO_RST             8
  90 +#define MT2701_TOPRGU_CONN_RST                 9
  91 +#define MT2701_TOPRGU_APMIXED_RST              10
  92 +#define MT2701_TOPRGU_HIFSYS_RST               11
  93 +#define MT2701_TOPRGU_CONN_MCU_RST             12
  94 +#define MT2701_TOPRGU_BDP_DISP_RST             13
  95 +
  96 +#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT2701 */
  97 --
  98 1.7.10.4
  99