target/linux/mediatek/patches-4.4/0011-reset-mediatek-mt2701-reset-driver.patch

   1 From b86d3303db25a8296e4c3de46ee1470f60f71b0c Mon Sep 17 00:00:00 2001
   2 From: Shunli Wang <shunli.wang@mediatek.com>
   3 Date: Tue, 5 Jan 2016 14:30:22 +0800
   4 Subject: [PATCH 11/81] reset: mediatek: mt2701 reset driver
   5
   6 In infrasys and perifsys, there are many reset
   7 control bits for kinds of modules. These bits are
   8 used as actual reset controllers to be registered
   9 into kernel's generic reset controller framework.
  10
  11 Signed-off-by: Shunli Wang <shunli.wang@mediatek.com>
  12 Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
  13 ---
  14  drivers/clk/mediatek/clk-mt2701.c |    4 ++++
  15  1 file changed, 4 insertions(+)
  16
  17 --- a/drivers/clk/mediatek/clk-mt2701.c
  18 +++ b/drivers/clk/mediatek/clk-mt2701.c
  19 @@ -665,6 +665,8 @@ static void __init mtk_infrasys_init(str
  20         if (r)
  21                 pr_err("%s(): could not register clock provider: %d\n",
  22                         __func__, r);
  23 +
  24 +       mtk_register_reset_controller(node, 2, 0x30);
  25  }
  26  CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt2701-infracfg", mtk_infrasys_init);
  27
  28 @@ -782,6 +784,8 @@ static void __init mtk_pericfg_init(stru
  29         if (r)
  30                 pr_err("%s(): could not register clock provider: %d\n",
  31                         __func__, r);
  32 +
  33 +       mtk_register_reset_controller(node, 2, 0x0);
  34  }
  35  CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt2701-pericfg", mtk_pericfg_init);
  36