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[openwrt/openwrt.git] / target / linux / mediatek / patches-4.4 / 0023-ARM-dts-mediatek-add-MT7623-basic-support.patch
1 From 51d5ca9e151eb323bd965e72ad1e1dc93fcf7b13 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Tue, 5 Jan 2016 12:16:17 +0100
4 Subject: [PATCH 023/102] ARM: dts: mediatek: add MT7623 basic support
5
6 This adds basic chip support for Mediatek MT7623.
7
8 Signed-off-by: John Crispin <blogic@openwrt.org>
9 ---
10 arch/arm/boot/dts/Makefile | 1 +
11 arch/arm/boot/dts/mt7623-evb.dts | 421 ++++++++++++++++++++++++++
12 arch/arm/boot/dts/mt7623.dtsi | 601 +++++++++++++++++++++++++++++++++++++
13 arch/arm/mach-mediatek/Kconfig | 4 +
14 arch/arm/mach-mediatek/mediatek.c | 1 +
15 5 files changed, 1028 insertions(+)
16 create mode 100644 arch/arm/boot/dts/mt7623-evb.dts
17 create mode 100644 arch/arm/boot/dts/mt7623.dtsi
18
19 diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
20 index 30bbc37..2bce370 100644
21 --- a/arch/arm/boot/dts/Makefile
22 +++ b/arch/arm/boot/dts/Makefile
23 @@ -774,6 +774,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
24 mt6580-evbp1.dtb \
25 mt6589-aquaris5.dtb \
26 mt6592-evb.dtb \
27 + mt7623-evb.dtb \
28 mt8127-moose.dtb \
29 mt8135-evbp1.dtb
30 dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
31 diff --git a/arch/arm/boot/dts/mt7623-evb.dts b/arch/arm/boot/dts/mt7623-evb.dts
32 new file mode 100644
33 index 0000000..5ad1448
34 --- /dev/null
35 +++ b/arch/arm/boot/dts/mt7623-evb.dts
36 @@ -0,0 +1,421 @@
37 +/*
38 + * Copyright (c) 2016 MediaTek Inc.
39 + * Author: John Crispin <blogic@openwrt.org>
40 + *
41 + * This program is free software; you can redistribute it and/or modify
42 + * it under the terms of the GNU General Public License version 2 as
43 + * published by the Free Software Foundation.
44 + *
45 + * This program is distributed in the hope that it will be useful,
46 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
47 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
48 + * GNU General Public License for more details.
49 + */
50 +
51 +/dts-v1/;
52 +
53 +#include "mt7623.dtsi"
54 +#include <dt-bindings/gpio/gpio.h>
55 +
56 +/ {
57 + model = "MediaTek MT7623 evaluation board";
58 + compatible = "mediatek,mt7623-evb", "mediatek,mt7623";
59 +
60 + chosen {
61 + stdout-path = &uart2;
62 + };
63 +
64 + memory {
65 + reg = <0 0x80000000 0 0x20000000>;
66 + };
67 +
68 + usb_p1_vbus: regulator@0 {
69 + compatible = "regulator-fixed";
70 + regulator-name = "usb_vbus";
71 + regulator-min-microvolt = <5000000>;
72 + regulator-max-microvolt = <5000000>;
73 + gpio = <&pio 135 GPIO_ACTIVE_HIGH>;
74 + enable-active-high;
75 + };
76 +};
77 +
78 +&cpu0 {
79 + proc-supply = <&mt6323_vproc_reg>;
80 +};
81 +
82 +&cpu1 {
83 + proc-supply = <&mt6323_vproc_reg>;
84 +};
85 +
86 +&cpu2 {
87 + proc-supply = <&mt6323_vproc_reg>;
88 +};
89 +
90 +&cpu3 {
91 + proc-supply = <&mt6323_vproc_reg>;
92 +};
93 +
94 +&pwrap {
95 + pmic: mt6323 {
96 + compatible = "mediatek,mt6323";
97 + interrupt-parent = <&pio>;
98 + interrupts = <150 IRQ_TYPE_LEVEL_HIGH>;
99 + interrupt-controller;
100 + #interrupt-cells = <2>;
101 +
102 + mt6323regulator: mt6323regulator{
103 + compatible = "mediatek,mt6323-regulator";
104 +
105 + mt6323_vproc_reg: buck_vproc{
106 + regulator-name = "vproc";
107 + regulator-min-microvolt = < 700000>;
108 + regulator-max-microvolt = <1350000>;
109 + regulator-ramp-delay = <12500>;
110 + regulator-always-on;
111 + regulator-boot-on;
112 + };
113 +
114 + mt6323_vsys_reg: buck_vsys{
115 + regulator-name = "vsys";
116 + regulator-min-microvolt = <1400000>;
117 + regulator-max-microvolt = <2987500>;
118 + regulator-ramp-delay = <25000>;
119 + regulator-always-on;
120 + regulator-boot-on;
121 + };
122 +
123 + mt6323_vpa_reg: buck_vpa{
124 + regulator-name = "vpa";
125 + regulator-min-microvolt = < 500000>;
126 + regulator-max-microvolt = <3650000>;
127 + };
128 +
129 + mt6323_vtcxo_reg: ldo_vtcxo{
130 + regulator-name = "vtcxo";
131 + regulator-min-microvolt = <2800000>;
132 + regulator-max-microvolt = <2800000>;
133 + regulator-enable-ramp-delay = <90>;
134 + regulator-always-on;
135 + regulator-boot-on;
136 + };
137 +
138 + mt6323_vcn28_reg: ldo_vcn28{
139 + regulator-name = "vcn28";
140 + regulator-min-microvolt = <2800000>;
141 + regulator-max-microvolt = <2800000>;
142 + regulator-enable-ramp-delay = <185>;
143 + };
144 +
145 + mt6323_vcn33_bt_reg: ldo_vcn33_bt{
146 + regulator-name = "vcn33_bt";
147 + regulator-min-microvolt = <3300000>;
148 + regulator-max-microvolt = <3600000>;
149 + regulator-enable-ramp-delay = <185>;
150 + };
151 +
152 + mt6323_vcn33_wifi_reg: ldo_vcn33_wifi{
153 + regulator-name = "vcn33_wifi";
154 + regulator-min-microvolt = <3300000>;
155 + regulator-max-microvolt = <3600000>;
156 + regulator-enable-ramp-delay = <185>;
157 + };
158 +
159 + mt6323_va_reg: ldo_va{
160 + regulator-name = "va";
161 + regulator-min-microvolt = <2800000>;
162 + regulator-max-microvolt = <2800000>;
163 + regulator-enable-ramp-delay = <216>;
164 + regulator-always-on;
165 + regulator-boot-on;
166 + };
167 +
168 + mt6323_vcama_reg: ldo_vcama{
169 + regulator-name = "vcama";
170 + regulator-min-microvolt = <1500000>;
171 + regulator-max-microvolt = <2800000>;
172 + regulator-enable-ramp-delay = <216>;
173 + };
174 +
175 + mt6323_vio28_reg: ldo_vio28{
176 + regulator-name = "vio28";
177 + regulator-min-microvolt = <2800000>;
178 + regulator-max-microvolt = <2800000>;
179 + regulator-enable-ramp-delay = <216>;
180 + regulator-always-on;
181 + regulator-boot-on;
182 + };
183 +
184 + mt6323_vusb_reg: ldo_vusb{
185 + regulator-name = "vusb";
186 + regulator-min-microvolt = <3300000>;
187 + regulator-max-microvolt = <3300000>;
188 + regulator-enable-ramp-delay = <216>;
189 + regulator-boot-on;
190 + };
191 +
192 + mt6323_vmc_reg: ldo_vmc{
193 + regulator-name = "vmc";
194 + regulator-min-microvolt = <1800000>;
195 + regulator-max-microvolt = <3300000>;
196 + regulator-enable-ramp-delay = <36>;
197 + regulator-boot-on;
198 + };
199 +
200 + mt6323_vmch_reg: ldo_vmch{
201 + regulator-name = "vmch";
202 + regulator-min-microvolt = <3000000>;
203 + regulator-max-microvolt = <3300000>;
204 + regulator-enable-ramp-delay = <36>;
205 + regulator-boot-on;
206 + };
207 +
208 + mt6323_vemc3v3_reg: ldo_vemc3v3{
209 + regulator-name = "vemc3v3";
210 + regulator-min-microvolt = <3000000>;
211 + regulator-max-microvolt = <3300000>;
212 + regulator-enable-ramp-delay = <36>;
213 + regulator-boot-on;
214 + };
215 +
216 + mt6323_vgp1_reg: ldo_vgp1{
217 + regulator-name = "vgp1";
218 + regulator-min-microvolt = <1200000>;
219 + regulator-max-microvolt = <3300000>;
220 + regulator-enable-ramp-delay = <216>;
221 + };
222 +
223 + mt6323_vgp2_reg: ldo_vgp2{
224 + regulator-name = "vgp2";
225 + regulator-min-microvolt = <1200000>;
226 + regulator-max-microvolt = <3000000>;
227 + regulator-enable-ramp-delay = <216>;
228 + };
229 +
230 + mt6323_vgp3_reg: ldo_vgp3{
231 + regulator-name = "vgp3";
232 + regulator-min-microvolt = <1200000>;
233 + regulator-max-microvolt = <1800000>;
234 + regulator-enable-ramp-delay = <216>;
235 + };
236 +
237 + mt6323_vcn18_reg: ldo_vcn18{
238 + regulator-name = "vcn18";
239 + regulator-min-microvolt = <1800000>;
240 + regulator-max-microvolt = <1800000>;
241 + regulator-enable-ramp-delay = <216>;
242 + };
243 +
244 + mt6323_vsim1_reg: ldo_vsim1{
245 + regulator-name = "vsim1";
246 + regulator-min-microvolt = <1800000>;
247 + regulator-max-microvolt = <3000000>;
248 + regulator-enable-ramp-delay = <216>;
249 + };
250 +
251 + mt6323_vsim2_reg: ldo_vsim2{
252 + regulator-name = "vsim2";
253 + regulator-min-microvolt = <1800000>;
254 + regulator-max-microvolt = <3000000>;
255 + regulator-enable-ramp-delay = <216>;
256 + };
257 +
258 + mt6323_vrtc_reg: ldo_vrtc{
259 + regulator-name = "vrtc";
260 + regulator-min-microvolt = <2800000>;
261 + regulator-max-microvolt = <2800000>;
262 + regulator-always-on;
263 + regulator-boot-on;
264 + };
265 +
266 + mt6323_vcamaf_reg: ldo_vcamaf{
267 + regulator-name = "vcamaf";
268 + regulator-min-microvolt = <1200000>;
269 + regulator-max-microvolt = <3300000>;
270 + regulator-enable-ramp-delay = <216>;
271 + };
272 +
273 + mt6323_vibr_reg: ldo_vibr{
274 + regulator-name = "vibr";
275 + regulator-min-microvolt = <1200000>;
276 + regulator-max-microvolt = <3300000>;
277 + regulator-enable-ramp-delay = <36>;
278 + };
279 +
280 + mt6323_vrf18_reg: ldo_vrf18{
281 + regulator-name = "vrf18";
282 + regulator-min-microvolt = <1825000>;
283 + regulator-max-microvolt = <1825000>;
284 + regulator-enable-ramp-delay = <187>;
285 + };
286 +
287 + mt6323_vm_reg: ldo_vm{
288 + regulator-name = "vm";
289 + regulator-min-microvolt = <1200000>;
290 + regulator-max-microvolt = <1800000>;
291 + regulator-enable-ramp-delay = <216>;
292 + regulator-always-on;
293 + regulator-boot-on;
294 + };
295 +
296 + mt6323_vio18_reg: ldo_vio18{
297 + regulator-name = "vio18";
298 + regulator-min-microvolt = <1800000>;
299 + regulator-max-microvolt = <1800000>;
300 + regulator-enable-ramp-delay = <216>;
301 + regulator-always-on;
302 + regulator-boot-on;
303 + };
304 +
305 + mt6323_vcamd_reg: ldo_vcamd{
306 + regulator-name = "vcamd";
307 + regulator-min-microvolt = <1200000>;
308 + regulator-max-microvolt = <1800000>;
309 + regulator-enable-ramp-delay = <216>;
310 + };
311 +
312 + mt6323_vcamio_reg: ldo_vcamio{
313 + regulator-name = "vcamio";
314 + regulator-min-microvolt = <1800000>;
315 + regulator-max-microvolt = <1800000>;
316 + regulator-enable-ramp-delay = <216>;
317 + };
318 + };
319 + };
320 +};
321 +
322 +&uart2 {
323 + status = "okay";
324 +};
325 +
326 +&pio {
327 + nand_pins_default: nanddefault {
328 + pins_dat {
329 + pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_NLD7>,
330 + <MT7623_PIN_112_MSDC0_DAT6_FUNC_NLD6>,
331 + <MT7623_PIN_114_MSDC0_DAT4_FUNC_NLD4>,
332 + <MT7623_PIN_118_MSDC0_DAT3_FUNC_NLD3>,
333 + <MT7623_PIN_121_MSDC0_DAT0_FUNC_NLD0>,
334 + <MT7623_PIN_120_MSDC0_DAT1_FUNC_NLD1>,
335 + <MT7623_PIN_113_MSDC0_DAT5_FUNC_NLD5>,
336 + <MT7623_PIN_115_MSDC0_RSTB_FUNC_NLD8>,
337 + <MT7623_PIN_119_MSDC0_DAT2_FUNC_NLD2>;
338 + input-enable;
339 + drive-strength = <MTK_DRIVE_8mA>;
340 + bias-pull-up;
341 + };
342 +
343 + pins_we {
344 + pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_NWEB>;
345 + drive-strength = <MTK_DRIVE_8mA>;
346 + bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
347 + };
348 +
349 + pins_ale {
350 + pinmux = <MT7623_PIN_116_MSDC0_CMD_FUNC_NALE>;
351 + drive-strength = <MTK_DRIVE_8mA>;
352 + bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
353 + };
354 + };
355 +
356 + eth_default: eth {
357 + pins_eth {
358 + pinmux = <MT7623_PIN_275_G2_MDC_FUNC_MDC>,
359 + <MT7623_PIN_276_G2_MDIO_FUNC_MDIO>,
360 + <MT7623_PIN_262_G2_TXEN_FUNC_G2_TXEN>,
361 + <MT7623_PIN_263_G2_TXD3_FUNC_G2_TXD3>,
362 + <MT7623_PIN_264_G2_TXD2_FUNC_G2_TXD2>,
363 + <MT7623_PIN_265_G2_TXD1_FUNC_G2_TXD1>,
364 + <MT7623_PIN_266_G2_TXD0_FUNC_G2_TXD0>,
365 + <MT7623_PIN_267_G2_TXCLK_FUNC_G2_TXC>,
366 + <MT7623_PIN_268_G2_RXCLK_FUNC_G2_RXC>,
367 + <MT7623_PIN_269_G2_RXD0_FUNC_G2_RXD0>,
368 + <MT7623_PIN_270_G2_RXD1_FUNC_G2_RXD1>,
369 + <MT7623_PIN_271_G2_RXD2_FUNC_G2_RXD2>,
370 + <MT7623_PIN_272_G2_RXD3_FUNC_G2_RXD3>,
371 + <MT7623_PIN_273_ESW_INT_FUNC_ESW_INT>,
372 + <MT7623_PIN_274_G2_RXDV_FUNC_G2_RXDV>;
373 + };
374 +
375 + pins_eth_rst {
376 + pinmux = <MT7623_PIN_15_GPIO15_FUNC_GPIO15>;
377 + output-low;
378 + };
379 + };
380 +};
381 +
382 +&nandc {
383 + status = "okay";
384 + pinctrl-names = "default";
385 + pinctrl-0 = <&nand_pins_default>;
386 + nand@0 {
387 + reg = <0>;
388 + partitions {
389 + compatible = "fixed-partitions";
390 + #address-cells = <1>;
391 + #size-cells = <1>;
392 +
393 + partition@C0000 {
394 + label = "uboot-env";
395 + reg = <0xC0000 0x40000>;
396 + };
397 +
398 + partition@100000 {
399 + label = "factory";
400 + reg = <0x100000 0x40000>;
401 + };
402 +
403 + partition@140000 {
404 + label = "kernel";
405 + reg = <0x140000 0x2000000>;
406 + };
407 +
408 + partition@2140000 {
409 + label = "recovery";
410 + reg = <0x2140000 0x2000000>;
411 + };
412 +
413 + partition@4140000 {
414 + label = "rootfs";
415 + reg = <0x4140000 0x1000000>;
416 + };
417 + };
418 + };
419 +};
420 +&bch {
421 + status = "okay";
422 +};
423 +
424 +&usb1 {
425 + vusb33-supply = <&mt6323_vusb_reg>;
426 + vbus-supply = <&usb_p1_vbus>;
427 + status = "okay";
428 +};
429 +
430 +&u3phy1 {
431 + status = "okay";
432 +};
433 +
434 +&pcie {
435 + status = "okay";
436 +};
437 +
438 +&eth {
439 + status = "okay";
440 +};
441 +
442 +&gmac1 {
443 + mac-address = [00 11 22 33 44 56];
444 + status = "okay";
445 +};
446 +
447 +&gmac2 {
448 + mac-address = [00 11 22 33 44 55];
449 + status = "okay";
450 +};
451 +
452 +&gsw {
453 + pinctrl-names = "default";
454 + pinctrl-0 = <&eth_default>;
455 + mediatek,reset-pin = <&pio 15 0>;
456 + status = "okay";
457 +};
458 diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
459 new file mode 100644
460 index 0000000..cbbdf16
461 --- /dev/null
462 +++ b/arch/arm/boot/dts/mt7623.dtsi
463 @@ -0,0 +1,601 @@
464 +/*
465 + * Copyright (c) 2016 MediaTek Inc.
466 + * Author: John Crispin <blogic@openwrt.org>
467 + *
468 + * This program is free software; you can redistribute it and/or modify
469 + * it under the terms of the GNU General Public License version 2 as
470 + * published by the Free Software Foundation.
471 + *
472 + * This program is distributed in the hope that it will be useful,
473 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
474 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
475 + * GNU General Public License for more details.
476 + */
477 +
478 +#include <dt-bindings/interrupt-controller/irq.h>
479 +#include <dt-bindings/interrupt-controller/arm-gic.h>
480 +#include <dt-bindings/clock/mt2701-clk.h>
481 +#include <dt-bindings/power/mt2701-power.h>
482 +#include <dt-bindings/phy/phy.h>
483 +#include <dt-bindings/reset-controller/mt2701-resets.h>
484 +#include <dt-bindings/pinctrl/mt7623-pinfunc.h>
485 +#include "skeleton64.dtsi"
486 +
487 +
488 +/ {
489 + compatible = "mediatek,mt7623";
490 + interrupt-parent = <&sysirq>;
491 +
492 + cpus {
493 + #address-cells = <1>;
494 + #size-cells = <0>;
495 + enable-method = "mediatek,mt6589-smp";
496 +
497 + cpu0: cpu@0 {
498 + device_type = "cpu";
499 + compatible = "arm,cortex-a7";
500 + reg = <0x0>;
501 + clocks = <&infracfg CLK_INFRA_CPUSEL>,
502 + <&apmixedsys CLK_APMIXED_MAINPLL>;
503 + clock-names = "cpu", "intermediate";
504 + operating-points = <
505 + 598000 1150000
506 + 747500 1150000
507 + 1040000 1150000
508 + 1196000 1200000
509 + 1300000 1300000
510 + >;
511 + };
512 + cpu1: cpu@1 {
513 + device_type = "cpu";
514 + compatible = "arm,cortex-a7";
515 + reg = <0x1>;
516 + clocks = <&infracfg CLK_INFRA_CPUSEL>,
517 + <&apmixedsys CLK_APMIXED_MAINPLL>;
518 + clock-names = "cpu", "intermediate";
519 + operating-points = <
520 + 598000 1150000
521 + 747500 1150000
522 + 1040000 1150000
523 + 1196000 1200000
524 + 1300000 1300000
525 + >;
526 + };
527 + cpu2: cpu@2 {
528 + device_type = "cpu";
529 + compatible = "arm,cortex-a7";
530 + reg = <0x2>;
531 + clocks = <&infracfg CLK_INFRA_CPUSEL>,
532 + <&apmixedsys CLK_APMIXED_MAINPLL>;
533 + clock-names = "cpu", "intermediate";
534 + operating-points = <
535 + 598000 1150000
536 + 747500 1150000
537 + 1040000 1150000
538 + 1196000 1200000
539 + 1300000 1300000
540 + >;
541 + };
542 + cpu3: cpu@3 {
543 + device_type = "cpu";
544 + compatible = "arm,cortex-a7";
545 + reg = <0x3>;
546 + clocks = <&infracfg CLK_INFRA_CPUSEL>,
547 + <&apmixedsys CLK_APMIXED_MAINPLL>;
548 + clock-names = "cpu", "intermediate";
549 + operating-points = <
550 + 598000 1150000
551 + 747500 1150000
552 + 1040000 1150000
553 + 1196000 1200000
554 + 1300000 1300000
555 + >;
556 + };
557 + };
558 +
559 + system_clk: dummy13m {
560 + compatible = "fixed-clock";
561 + clock-frequency = <13000000>;
562 + #clock-cells = <0>;
563 + };
564 +
565 + rtc_clk: dummy32k {
566 + compatible = "fixed-clock";
567 + clock-frequency = <32000>;
568 + #clock-cells = <0>;
569 + clock-output-names = "clk32k";
570 + };
571 +
572 + clk26m: dummy26m {
573 + compatible = "fixed-clock";
574 + clock-frequency = <26000000>;
575 + #clock-cells = <0>;
576 + clock-output-names = "clk26m";
577 + };
578 +
579 + timer {
580 + compatible = "arm,armv7-timer";
581 + interrupt-parent = <&gic>;
582 + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
583 + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
584 + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
585 + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
586 + clock-frequency = <13000000>;
587 + arm,cpu-registers-not-fw-configured;
588 + };
589 +
590 + topckgen: power-controller@10000000 {
591 + compatible = "mediatek,mt7623-topckgen",
592 + "mediatek,mt2701-topckgen",
593 + "syscon";
594 + reg = <0 0x10000000 0 0x1000>;
595 + #clock-cells = <1>;
596 + };
597 +
598 + infracfg: power-controller@10001000 {
599 + compatible = "mediatek,mt7623-infracfg",
600 + "mediatek,mt2701-infracfg",
601 + "syscon";
602 + reg = <0 0x10001000 0 0x1000>;
603 + #clock-cells = <1>;
604 + #reset-cells = <1>;
605 + };
606 +
607 + pericfg: pericfg@10003000 {
608 + compatible = "mediatek,mt7623-pericfg",
609 + "mediatek,mt2701-pericfg",
610 + "syscon";
611 + reg = <0 0x10003000 0 0x1000>;
612 + #clock-cells = <1>;
613 + #reset-cells = <1>;
614 + };
615 +
616 + pio: pinctrl@10005000 {
617 + compatible = "mediatek,mt7623-pinctrl";
618 + reg = <0 0x1000b000 0 0x1000>;
619 + mediatek,pctl-regmap = <&syscfg_pctl_a>;
620 + pins-are-numbered;
621 + gpio-controller;
622 + #gpio-cells = <2>;
623 + interrupt-controller;
624 + interrupt-parent = <&gic>;
625 + #interrupt-cells = <2>;
626 + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
627 + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
628 + };
629 +
630 + syscfg_pctl_a: syscfg@10005000 {
631 + compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
632 + reg = <0 0x10005000 0 0x1000>;
633 + };
634 +
635 + scpsys: scpsys@10006000 {
636 + #power-domain-cells = <1>;
637 + compatible = "mediatek,mt7623-scpsys",
638 + "mediatek,mt2701-scpsys";
639 + reg = <0 0x10006000 0 0x1000>;
640 + infracfg = <&infracfg>;
641 + clocks = <&clk26m>,
642 + <&topckgen CLK_TOP_MM_SEL>;
643 + clock-names = "mfg", "mm";
644 + };
645 +
646 + watchdog: watchdog@10007000 {
647 + compatible = "mediatek,mt7623-wdt",
648 + "mediatek,mt6589-wdt";
649 + reg = <0 0x10007000 0 0x100>;
650 + };
651 +
652 + timer: timer@10008000 {
653 + compatible = "mediatek,mt7623-timer",
654 + "mediatek,mt6577-timer";
655 + reg = <0 0x10008000 0 0x80>;
656 + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
657 + clocks = <&system_clk>, <&rtc_clk>;
658 + clock-names = "system-clk", "rtc-clk";
659 + };
660 +
661 + pwrap: pwrap@1000d000 {
662 + compatible = "mediatek,mt7623-pwrap",
663 + "mediatek,mt2701-pwrap";
664 + reg = <0 0x1000d000 0 0x1000>;
665 + reg-names = "pwrap";
666 + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
667 + resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
668 + reset-names = "pwrap";
669 + clocks = <&infracfg CLK_INFRA_PMICSPI>,
670 + <&infracfg CLK_INFRA_PMICWRAP>;
671 + clock-names = "spi", "wrap";
672 + };
673 +
674 + sysirq: interrupt-controller@10200100 {
675 + compatible = "mediatek,mt7623-sysirq",
676 + "mediatek,mt6577-sysirq";
677 + interrupt-controller;
678 + #interrupt-cells = <3>;
679 + interrupt-parent = <&gic>;
680 + reg = <0 0x10200100 0 0x1c>;
681 + };
682 +
683 + apmixedsys: apmixedsys@10209000 {
684 + compatible = "mediatek,mt7623-apmixedsys",
685 + "mediatek,mt2701-apmixedsys";
686 + reg = <0 0x10209000 0 0x1000>;
687 + #clock-cells = <1>;
688 + };
689 +
690 + gic: interrupt-controller@10211000 {
691 + compatible = "arm,cortex-a7-gic";
692 + interrupt-controller;
693 + #interrupt-cells = <3>;
694 + interrupt-parent = <&gic>;
695 + reg = <0 0x10211000 0 0x1000>,
696 + <0 0x10212000 0 0x1000>,
697 + <0 0x10214000 0 0x2000>,
698 + <0 0x10216000 0 0x2000>;
699 + };
700 +
701 + i2c0: i2c@11007000 {
702 + compatible = "mediatek,mt7623-i2c",
703 + "mediatek,mt6577-i2c";
704 + reg = <0 0x11007000 0 0x70>,
705 + <0 0x11000200 0 0x80>;
706 + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
707 + clock-div = <16>;
708 + clocks = <&pericfg CLK_PERI_I2C0>,
709 + <&pericfg CLK_PERI_AP_DMA>;
710 + clock-names = "main", "dma";
711 + #address-cells = <1>;
712 + #size-cells = <0>;
713 + status = "disabled";
714 + };
715 +
716 + i2c1: i2c@11008000 {
717 + compatible = "mediatek,mt7623-i2c",
718 + "mediatek,mt6577-i2c";
719 + reg = <0 0x11008000 0 0x70>,
720 + <0 0x11000280 0 0x80>;
721 + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
722 + clock-div = <16>;
723 + clocks = <&pericfg CLK_PERI_I2C1>,
724 + <&pericfg CLK_PERI_AP_DMA>;
725 + clock-names = "main", "dma";
726 + #address-cells = <1>;
727 + #size-cells = <0>;
728 + status = "disabled";
729 + };
730 +
731 + i2c2: i2c@11009000 {
732 + compatible = "mediatek,mt7623-i2c",
733 + "mediatek,mt6577-i2c";
734 + reg = <0 0x11009000 0 0x70>,
735 + <0 0x11000300 0 0x80>;
736 + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
737 + clock-div = <16>;
738 + clocks = <&pericfg CLK_PERI_I2C2>,
739 + <&pericfg CLK_PERI_AP_DMA>;
740 + clock-names = "main", "dma";
741 + #address-cells = <1>;
742 + #size-cells = <0>;
743 + status = "disabled";
744 + };
745 +
746 + uart0: serial@11002000 {
747 + compatible = "mediatek,mt7623-uart",
748 + "mediatek,mt6577-uart";
749 + reg = <0 0x11002000 0 0x400>;
750 + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
751 + clocks = <&pericfg CLK_PERI_UART0_SEL>,
752 + <&pericfg CLK_PERI_UART0>;
753 + clock-names = "baud", "bus";
754 + status = "disabled";
755 + };
756 +
757 + uart1: serial@11003000 {
758 + compatible = "mediatek,mt7623-uart",
759 + "mediatek,mt6577-uart";
760 + reg = <0 0x11003000 0 0x400>;
761 + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
762 + clocks = <&pericfg CLK_PERI_UART1_SEL>,
763 + <&pericfg CLK_PERI_UART1>;
764 + clock-names = "baud", "bus";
765 + status = "disabled";
766 + };
767 +
768 + uart2: serial@11004000 {
769 + compatible = "mediatek,mt7623-uart",
770 + "mediatek,mt6577-uart";
771 + reg = <0 0x11004000 0 0x400>;
772 + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
773 + clocks = <&pericfg CLK_PERI_UART2_SEL>,
774 + <&pericfg CLK_PERI_UART2>;
775 + clock-names = "baud", "bus";
776 + status = "disabled";
777 + };
778 +
779 + uart3: serial@11005000 {
780 + compatible = "mediatek,mt7623-uart",
781 + "mediatek,mt6577-uart";
782 + reg = <0 0x11005000 0 0x400>;
783 + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
784 + clocks = <&pericfg CLK_PERI_UART3_SEL>,
785 + <&pericfg CLK_PERI_UART3>;
786 + clock-names = "baud", "bus";
787 + status = "disabled";
788 + };
789 +
790 + spi: spi@1100a000 {
791 + compatible = "mediatek,mt7623-spi", "mediatek,mt6589-spi";
792 + reg = <0 0x1100a000 0 0x1000>;
793 + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
794 + clocks = <&pericfg CLK_PERI_SPI0>;
795 + clock-names = "main";
796 +
797 + status = "disabled";
798 + };
799 +
800 + nandc: nfi@1100d000 {
801 + compatible = "mediatek,mt2701-nfc";
802 + reg = <0 0x1100d000 0 0x1000>;
803 + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
804 + power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
805 + clocks = <&pericfg CLK_PERI_NFI>,
806 + <&pericfg CLK_PERI_NFI_PAD>;
807 + clock-names = "nfi_clk", "pad_clk";
808 + status = "disabled";
809 + ecc-engine = <&bch>;
810 + #address-cells = <1>;
811 + #size-cells = <0>;
812 + };
813 +
814 + bch: ecc@1100e000 {
815 + compatible = "mediatek,mt2701-ecc";
816 + reg = <0 0x1100e000 0 0x1000>;
817 + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
818 + clocks = <&pericfg CLK_PERI_NFI_ECC>;
819 + clock-names = "nfiecc_clk";
820 + status = "disabled";
821 + };
822 +
823 + mmc0: mmc@11230000 {
824 + compatible = "mediatek,mt7623-mmc",
825 + "mediatek,mt8135-mmc";
826 + reg = <0 0x11230000 0 0x1000>;
827 + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
828 + clocks = <&pericfg CLK_PERI_MSDC30_0>,
829 + <&topckgen CLK_TOP_MSDC30_0_SEL>;
830 + clock-names = "source", "hclk";
831 + status = "disabled";
832 + };
833 +
834 + mmc1: mmc@11240000 {
835 + compatible = "mediatek,mt7623-mmc",
836 + "mediatek,mt8135-mmc";
837 + reg = <0 0x11240000 0 0x1000>;
838 + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
839 + clocks = <&pericfg CLK_PERI_MSDC30_1>,
840 + <&topckgen CLK_TOP_MSDC30_1_SEL>;
841 + clock-names = "source", "hclk";
842 + status = "disabled";
843 + };
844 +
845 + usb1: usb@1a1c0000 {
846 + compatible = "mediatek,mt2701-xhci",
847 + "mediatek,mt8173-xhci";
848 + reg = <0 0x1a1c0000 0 0x1000>,
849 + <0 0x1a1c4700 0 0x0100>;
850 + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
851 + clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
852 + <&topckgen CLK_TOP_ETHIF_SEL>;
853 + clock-names = "sys_ck", "ethif";
854 + power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
855 + phys = <&phy_port0 PHY_TYPE_USB3>;
856 + status = "disabled";
857 + };
858 +
859 + u3phy1: usb-phy@1a1c4000 {
860 + compatible = "mediatek,mt2701-u3phy",
861 + "mediatek,mt8173-u3phy";
862 + reg = <0 0x1a1c4000 0 0x0700>;
863 + clocks = <&clk26m>;
864 + clock-names = "u3phya_ref";
865 + #phy-cells = <1>;
866 + #address-cells = <2>;
867 + #size-cells = <2>;
868 + ranges;
869 + status = "disabled";
870 +
871 + phy_port0: phy_port0: port@1a1c4800 {
872 + reg = <0 0x1a1c4800 0 0x800>;
873 + #phy-cells = <1>;
874 + status = "okay";
875 + };
876 + };
877 +
878 + usb2: usb@1a240000 {
879 + compatible = "mediatek,mt2701-xhci",
880 + "mediatek,mt8173-xhci";
881 + reg = <0 0x1a240000 0 0x1000>,
882 + <0 0x1a244700 0 0x0100>;
883 + interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
884 + clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
885 + <&topckgen CLK_TOP_ETHIF_SEL>;
886 + clock-names = "sys_ck", "ethif";
887 + power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
888 + phys = <&u3phy2 0>;
889 + status = "disabled";
890 + };
891 +
892 + u3phy2: usb-phy@1a244000 {
893 + compatible = "mediatek,mt2701-u3phy",
894 + "mediatek,mt8173-u3phy";
895 + reg = <0 0x1a244000 0 0x0700>,
896 + <0 0x1a244800 0 0x0800>;
897 + clocks = <&clk26m>;
898 + clock-names = "u3phya_ref";
899 + #phy-cells = <1>;
900 + status = "disabled";
901 + };
902 +
903 + hifsys: clock-controller@1a000000 {
904 + compatible = "mediatek,mt7623-hifsys",
905 + "mediatek,mt2701-hifsys",
906 + "syscon";
907 + reg = <0 0x1a000000 0 0x1000>;
908 + #clock-cells = <1>;
909 + #reset-cells = <1>;
910 + };
911 +
912 + pcie: pcie@1a140000 {
913 + compatible = "mediatek,mt7623-pcie";
914 + device_type = "pci";
915 + reg = <0 0x1a140000 0 0x8000>, /* PCI-Express registers */
916 + <0 0x1a149000 0 0x1000>, /* PCI-Express PHY0 */
917 + <0 0x1a14a000 0 0x1000>, /* PCI-Express PHY1 */
918 + <0 0x1a244000 0 0x1000>; /* PCI-Express PHY2 */
919 + reg-names = "pcie", "pcie phy0", "pcie phy1", "pcie phy2";
920 + interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
921 + <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
922 + <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
923 + interrupt-names = "pcie0", "pcie1", "pcie2";
924 + clocks = <&topckgen CLK_TOP_ETHIF_SEL>;
925 + clock-names = "pcie";
926 + power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
927 + resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
928 + <&hifsys MT2701_HIFSYS_PCIE1_RST>,
929 + <&hifsys MT2701_HIFSYS_PCIE2_RST>;
930 + reset-names = "pcie0", "pcie1", "pcie2";
931 +
932 + mediatek,hifsys = <&hifsys>;
933 +
934 + bus-range = <0x00 0xff>;
935 + #address-cells = <3>;
936 + #size-cells = <2>;
937 +
938 + ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* io space */
939 + 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* pci memory */
940 +
941 + status = "disabled";
942 +
943 + pcie@1,0 {
944 + device_type = "pci";
945 + reg = <0x0800 0 0 0 0>;
946 +
947 + #address-cells = <3>;
948 + #size-cells = <2>;
949 + ranges;
950 + };
951 +
952 + pcie@2,0{
953 + device_type = "pci";
954 + reg = <0x1000 0 0 0 0>;
955 +
956 + #address-cells = <3>;
957 + #size-cells = <2>;
958 + ranges;
959 + };
960 +
961 + pcie@3,0{
962 + device_type = "pci";
963 + reg = <0x1800 0 0 0 0>;
964 +
965 + #address-cells = <3>;
966 + #size-cells = <2>;
967 + ranges;
968 + };
969 + };
970 +
971 + ethsys: syscon@1b000000 {
972 + compatible = "mediatek,mt2701-ethsys", "syscon";
973 + reg = <0 0x1b000000 0 0x1000>;
974 + #reset-cells = <1>;
975 + #clock-cells = <1>;
976 + };
977 +
978 + eth: ethernet@1b100000 {
979 + compatible = "mediatek,mt7623-eth";
980 + reg = <0 0x1b100000 0 0x20000>;
981 +
982 + clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
983 + <&ethsys CLK_ETHSYS_ESW>,
984 + <&ethsys CLK_ETHSYS_GP2>,
985 + <&ethsys CLK_ETHSYS_GP1>;
986 + clock-names = "ethif", "esw", "gp2", "gp1";
987 + interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW
988 + GIC_SPI 199 IRQ_TYPE_LEVEL_LOW
989 + GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
990 + power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
991 +
992 + resets = <&ethsys 6>;
993 + reset-names = "eth";
994 +
995 + mediatek,ethsys = <&ethsys>;
996 + mediatek,pctl = <&syscfg_pctl_a>;
997 +
998 + mediatek,switch = <&gsw>;
999 +
1000 + #address-cells = <1>;
1001 + #size-cells = <0>;
1002 +
1003 + status = "disabled";
1004 +
1005 + gmac1: mac@0 {
1006 + compatible = "mediatek,eth-mac";
1007 + reg = <0>;
1008 +
1009 + status = "disabled";
1010 +
1011 + phy-mode = "rgmii";
1012 +
1013 + fixed-link {
1014 + speed = <1000>;
1015 + full-duplex;
1016 + pause;
1017 + };
1018 + };
1019 +
1020 + gmac2: mac@1 {
1021 + compatible = "mediatek,eth-mac";
1022 + reg = <1>;
1023 +
1024 + status = "disabled";
1025 +
1026 + phy-mode = "rgmii";
1027 +
1028 + fixed-link {
1029 + speed = <1000>;
1030 + full-duplex;
1031 + pause;
1032 + };
1033 + };
1034 +
1035 + mdio-bus {
1036 + #address-cells = <1>;
1037 + #size-cells = <0>;
1038 +
1039 + phy5: ethernet-phy@5 {
1040 + reg = <5>;
1041 + phy-mode = "rgmii-rxid";
1042 + };
1043 +
1044 + phy1f: ethernet-phy@1f {
1045 + reg = <0x1f>;
1046 + phy-mode = "rgmii";
1047 + };
1048 + };
1049 + };
1050 +
1051 + gsw: switch@1b100000 {
1052 + compatible = "mediatek,mt7623-gsw";
1053 + interrupt-parent = <&pio>;
1054 + interrupts = <168 IRQ_TYPE_EDGE_RISING>;
1055 + resets = <&ethsys 2>;
1056 + reset-names = "eth";
1057 + clocks = <&apmixedsys CLK_APMIXED_TRGPLL>;
1058 + clock-names = "trgpll";
1059 + mt7530-supply = <&mt6323_vpa_reg>;
1060 + mediatek,pctl-regmap = <&syscfg_pctl_a>;
1061 + mediatek,ethsys = <&ethsys>;
1062 + status = "disabled";
1063 + };
1064 +};
1065 diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
1066 index 37dd438..7fb605e 100644
1067 --- a/arch/arm/mach-mediatek/Kconfig
1068 +++ b/arch/arm/mach-mediatek/Kconfig
1069 @@ -21,6 +21,10 @@ config MACH_MT6592
1070 bool "MediaTek MT6592 SoCs support"
1071 default ARCH_MEDIATEK
1072
1073 +config MACH_MT7623
1074 + bool "MediaTek MT7623 SoCs support"
1075 + default ARCH_MEDIATEK
1076 +
1077 config MACH_MT8127
1078 bool "MediaTek MT8127 SoCs support"
1079 default ARCH_MEDIATEK
1080 diff --git a/arch/arm/mach-mediatek/mediatek.c b/arch/arm/mach-mediatek/mediatek.c
1081 index d019a08..bcfca37 100644
1082 --- a/arch/arm/mach-mediatek/mediatek.c
1083 +++ b/arch/arm/mach-mediatek/mediatek.c
1084 @@ -46,6 +46,7 @@ static void __init mediatek_timer_init(void)
1085 static const char * const mediatek_board_dt_compat[] = {
1086 "mediatek,mt6589",
1087 "mediatek,mt6592",
1088 + "mediatek,mt7623",
1089 "mediatek,mt8127",
1090 "mediatek,mt8135",
1091 NULL,
1092 --
1093 1.7.10.4
1094
OpenWrt Source Repository