target/linux/mediatek/patches-4.4/0024-dt-bindings-add-MediaTek-PCIe-binding-documentation.patch

   1 From 0afae16fffe2cf547fad21279c120bedf19e9b8e Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Wed, 6 Jan 2016 21:55:10 +0100
   4 Subject: [PATCH 24/91] dt-bindings: add MediaTek PCIe binding documentation
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  .../devicetree/bindings/pci/mediatek-pcie.txt      |  140 ++++++++++++++++++++
   9  1 file changed, 140 insertions(+)
  10  create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie.txt
  11
  12 diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
  13 new file mode 100644
  14 index 0000000..8fea3ed
  15 --- /dev/null
  16 +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
  17 @@ -0,0 +1,140 @@
  18 +Mediatek PCIe controller
  19 +
  20 +Required properties:
  21 +- compatible: Should be one of:
  22 +       - "mediatek,mt2701-pcie"
  23 +       - "mediatek,mt7623-pcie"
  24 +- device_type: Must be "pci"
  25 +- reg: A list of physical base address and length for each set of controller
  26 +  registers. A list of register ranges to use. Must contain an
  27 +    entry for each entry in the reg-names property.
  28 +- reg-names: Must include the following entries:
  29 +  "pcie": PCIe registers
  30 +  "pcie phy0": PCIe PHY0 registers
  31 +  "pcie phy1": PCIe PHY0 registers
  32 +  "pcie phy2": PCIe PHY0 registers
  33 +- interrupts: A list of interrupt outputs of the controller. Must contain an
  34 +  entry for each entry in the interrupt-names property.
  35 +- interrupt-names: Must include the following entries:
  36 +  "pcie0": The interrupt that is asserted for port0
  37 +  "pcie1": The interrupt that is asserted for port1
  38 +  "pcie2": The interrupt that is asserted for port2
  39 +- bus-range: Range of bus numbers associated with this controller
  40 +- #address-cells: Address representation for root ports (must be 3)
  41 +- #size-cells: Size representation for root ports (must be 2)
  42 +- ranges: Describes the translation of addresses for root ports and standard
  43 +  PCI regions. The entries must be 6 cells each.
  44 +  Please refer to the standard PCI bus binding document for a more detailed
  45 +  explanation.
  46 +- #interrupt-cells: Size representation for interrupts (must be 1)
  47 +- clocks: Must contain an entry for each entry in clock-names.
  48 +  See ../clocks/clock-bindings.txt for details.
  49 +- clock-names: Must include the following entries:
  50 +  - pcie0
  51 +  - pcie1
  52 +  - pcie2
  53 +- resets: Must contain an entry for each entry in reset-names.
  54 +  See ../reset/reset.txt for details.
  55 +- reset-names: Must include the following entries:
  56 +  - pcie0
  57 +  - pcie1
  58 +  - pcie2
  59 +- mediatek,hifsys: Must contain a phandle to the HIFSYS syscon range.
  60 +Root ports are defined as subnodes of the PCIe controller node.
  61 +
  62 +Required properties:
  63 +- device_type: Must be "pci"
  64 +- assigned-addresses: Address and size of the port configuration registers
  65 +- reg: PCI bus address of the root port
  66 +- #address-cells: Must be 3
  67 +- #size-cells: Must be 2
  68 +- ranges: Sub-ranges distributed from the PCIe controller node. An empty
  69 +  property is sufficient.
  70 +
  71 +Example:
  72 +
  73 +SoC DTSI:
  74 +
  75 +       hifsys: clock-controller@1a000000 {
  76 +               compatible = "mediatek,mt7623-hifsys",
  77 +                            "mediatek,mt2701-hifsys",
  78 +                            "syscon";
  79 +               reg = <0 0x1a000000 0 0x1000>;
  80 +               #clock-cells = <1>;
  81 +               #reset-cells = <1>;
  82 +       };
  83 +
  84 +       pcie-controller@1a140000 {
  85 +               compatible = "mediatek,mt7623-pcie";
  86 +               device_type = "pci";
  87 +               reg = <0 0x1a140000 0 0x8000>, /* PCI-Express registers */
  88 +                     <0 0x1a149000 0 0x1000>, /* PCI-Express PHY0 */
  89 +                     <0 0x1a14a000 0 0x1000>, /* PCI-Express PHY1 */
  90 +                     <0 0x1a244000 0 0x1000>; /* PCI-Express PHY2 */
  91 +               reg-names = "pcie", "pcie phy0", "pcie phy1", "pcie phy2";
  92 +               interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
  93 +                            <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
  94 +                            <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
  95 +               interrupt-names = "pcie0", "pcie1", "pcie2";
  96 +               clocks = <&topckgen CLK_TOP_ETHIF_SEL>;
  97 +               clock-names = "pcie";
  98 +               power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
  99 +               resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
 100 +                        <&hifsys MT2701_HIFSYS_PCIE1_RST>,
 101 +                        <&hifsys MT2701_HIFSYS_PCIE2_RST>;
 102 +               reset-names = "pcie0", "pice1", "pcie2";
 103 +
 104 +               bus-range = <0x00 0xff>;
 105 +               #address-cells = <3>;
 106 +               #size-cells = <2>;
 107 +
 108 +                mediatek,hifsys = <&hifsys>;
 109 +
 110 +               ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* io space */
 111 +                         0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* pci memory */
 112 +
 113 +               status = "disabled";
 114 +
 115 +               pcie@1,0 {
 116 +                       device_type = "pci";
 117 +                       reg = <0x0800 0 0 0 0>;
 118 +
 119 +                       #address-cells = <3>;
 120 +                       #size-cells = <2>;
 121 +                       ranges;
 122 +
 123 +                       status = "disabled";
 124 +               };
 125 +
 126 +               pcie@2,0{
 127 +                       device_type = "pci";
 128 +                       reg = <0x1000 0 0 0 0>;
 129 +
 130 +                       #address-cells = <3>;
 131 +                       #size-cells = <2>;
 132 +                       ranges;
 133 +
 134 +                       status = "disabled";
 135 +               };
 136 +
 137 +               pcie@3,0{
 138 +                       device_type = "pci";
 139 +                       reg = <0x1800 0 0 0 0>;
 140 +
 141 +                       #address-cells = <3>;
 142 +                       #size-cells = <2>;
 143 +                       ranges;
 144 +
 145 +                       status = "disabled";
 146 +               };
 147 +       };
 148 +
 149 +Board DTS:
 150 +
 151 +       pcie-controller {
 152 +               status = "okay";
 153 +
 154 +               pci@1,0 {
 155 +                       status = "okay";
 156 +               };
 157 +       };
 158 --
 159 1.7.10.4
 160