target/linux/mediatek/patches-4.4/0025-PCI-mediatek-add-support-for-PCIe-found-on-MT7623-MT.patch

   1 From 4e9a4574e833ee42d646de2dc3b0cb912360e6c5 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Tue, 5 Jan 2016 20:20:04 +0100
   4 Subject: [PATCH 25/90] PCI: mediatek: add support for PCIe found on
   5  MT7623/MT2701
   6
   7 Add PCIe controller support on MediaTek MT2701/MT7623. The driver supports
   8 a single Root complex (RC) with 3 Root Ports. The SoCs supports a Gen2
   9 1-lan Link on each port.
  10
  11 Signed-off-by: John Crispin <blogic@openwrt.org>
  12 ---
  13  arch/arm/mach-mediatek/Kconfig   |    1 +
  14  drivers/pci/host/Kconfig         |   11 +
  15  drivers/pci/host/Makefile        |    1 +
  16  drivers/pci/host/pcie-mediatek.c |  641 ++++++++++++++++++++++++++++++++++++++
  17  4 files changed, 654 insertions(+)
  18  create mode 100644 drivers/pci/host/pcie-mediatek.c
  19
  20 diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
  21 index 7fb605e..a7fef77 100644
  22 --- a/arch/arm/mach-mediatek/Kconfig
  23 +++ b/arch/arm/mach-mediatek/Kconfig
  24 @@ -24,6 +24,7 @@ config MACH_MT6592
  25  config MACH_MT7623
  26         bool "MediaTek MT7623 SoCs support"
  27         default ARCH_MEDIATEK
  28 +       select MIGHT_HAVE_PCI
  29
  30  config MACH_MT8127
  31         bool "MediaTek MT8127 SoCs support"
  32 diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
  33 index f131ba9..912f0e1 100644
  34 --- a/drivers/pci/host/Kconfig
  35 +++ b/drivers/pci/host/Kconfig
  36 @@ -172,4 +172,15 @@ config PCI_HISI
  37         help
  38           Say Y here if you want PCIe controller support on HiSilicon HIP05 SoC
  39
  40 +config PCIE_MTK
  41 +       bool "Mediatek PCIe Controller"
  42 +       depends on MACH_MT2701 || MACH_MT7623
  43 +       depends on OF
  44 +       depends on PCI
  45 +       help
  46 +         Say Y here if you want to enable PCI controller support on Mediatek MT7623.
  47 +         MT7623 PCIe supports single Root complex (RC) with 3 Root Ports.
  48 +         Each port supports a Gen2 1-lan Link.
  49 +         PCIe include one Host/PCI bridge and 3 PCIe MAC.
  50 +
  51  endmenu
  52 diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
  53 index 9d4d3c6..3b53374 100644
  54 --- a/drivers/pci/host/Makefile
  55 +++ b/drivers/pci/host/Makefile
  56 @@ -20,3 +20,4 @@ obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
  57  obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
  58  obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
  59  obj-$(CONFIG_PCI_HISI) += pcie-hisi.o
  60 +obj-$(CONFIG_PCIE_MTK) += pcie-mediatek.o
  61 diff --git a/drivers/pci/host/pcie-mediatek.c b/drivers/pci/host/pcie-mediatek.c
  62 new file mode 100644
  63 index 0000000..ef03952
  64 --- /dev/null
  65 +++ b/drivers/pci/host/pcie-mediatek.c
  66 @@ -0,0 +1,641 @@
  67 +/*
  68 + *  Mediatek MT2701/MT7623 SoC PCIE support
  69 + *
  70 + *  Copyright (C) 2015 Mediatek
  71 + *  Copyright (C) 2015 Ziv Huang <ziv.huang@mediatek.com>
  72 + *  Copyright (C) 2015 John Crispin <blogic@openwrt.org>
  73 + *
  74 + *  This program is free software; you can redistribute it and/or modify it
  75 + *  under the terms of the GNU General Public License version 2 as published
  76 + *  by the Free Software Foundation.
  77 + */
  78 +
  79 +#include <linux/kernel.h>
  80 +#include <linux/pci.h>
  81 +#include <linux/ioport.h>
  82 +#include <linux/interrupt.h>
  83 +#include <linux/spinlock.h>
  84 +#include <linux/init.h>
  85 +#include <linux/device.h>
  86 +#include <linux/io.h>
  87 +#include <linux/delay.h>
  88 +#include <asm/irq.h>
  89 +#include <asm/mach/pci.h>
  90 +#include <linux/module.h>
  91 +#include <linux/of.h>
  92 +#include <linux/of_address.h>
  93 +#include <linux/of_pci.h>
  94 +#include <linux/of_platform.h>
  95 +#include <linux/of_irq.h>
  96 +#include <linux/reset.h>
  97 +#include <linux/platform_device.h>
  98 +#include <linux/regulator/consumer.h>
  99 +#include <linux/pm_runtime.h>
 100 +#include <linux/clk.h>
 101 +#include <linux/regmap.h>
 102 +#include <linux/mfd/syscon.h>
 103 +
 104 +#define MEMORY_BASE                    0x80000000
 105 +
 106 +/* PCIE Registers */
 107 +#define PCICFG                         0x00
 108 +#define PCIINT                         0x08
 109 +#define PCIENA                         0x0c
 110 +#define CFGADDR                                0x20
 111 +#define CFGDATA                                0x24
 112 +#define MEMBASE                                0x28
 113 +#define IOBASE                         0x2c
 114 +
 115 +/* per Port Registers */
 116 +#define BAR0SETUP                      0x10
 117 +#define IMBASEBAR0                     0x18
 118 +#define PCIE_CLASS                     0x34
 119 +#define PCIE_SISTAT                    0x50
 120 +
 121 +#define MTK_PCIE_HIGH_PERF             BIT(14)
 122 +#define PCIEP0_BASE                    0x2000
 123 +#define PCIEP1_BASE                    0x3000
 124 +#define PCIEP2_BASE                    0x4000
 125 +
 126 +#define PHY_P0_CTL                     0x9000
 127 +#define PHY_P1_CTL                     0xa000
 128 +#define PHY_P2_CTL                     0x4000
 129 +
 130 +#define RSTCTL_PCIE0_RST               BIT(24)
 131 +#define RSTCTL_PCIE1_RST               BIT(25)
 132 +#define RSTCTL_PCIE2_RST               BIT(26)
 133 +
 134 +#define HIFSYS_SYSCFG1                 0x14
 135 +#define HIFSYS_SYSCFG1_PHY2_MASK       (0x3 << 20)
 136 +
 137 +#define MTK_PHY_CLK                    0xb00
 138 +#define MTK_PHY_CLKDRV_OFFSET          BIT(2)
 139 +#define MTK_PHY_CLKDRV_OFFSET_MASK     0xe
 140 +#define MTK_PHY_PLL                    0xb04
 141 +#define MTK_PHY_CLKDRV_AMP             BIT(30)
 142 +#define MTK_PHY_CLKDRV_AMP_MASK                0xe0000000
 143 +#define MTK_PHY_REFCLK_SEL             0xc00
 144 +#define MTK_PHY_XTAL_EXT_EN            (BIT(17) | BIT(12))
 145 +#define MTK_PHY_XTAL_EXT_EN_MASK       0x33000
 146 +#define MTK_PHY_PLL_BC                 0xc08
 147 +#define MTK_PHY_PLL_BC_PE2H            0xc0
 148 +#define MTK_PHY_PLL_BC_PE2H_MASK       0x380000
 149 +#define MTK_PHY_PLL_IC                 0xc0c
 150 +#define MTK_PHY_PLL_IC_BR_PE2H         BIT(28)
 151 +#define MTK_PHY_PLL_IC_BR_PE2H_MASK    0x30000000
 152 +#define MTK_PHY_PLL_IC_PE2H            BIT(12)
 153 +#define MTK_PHY_PLL_IC_PE2H_MASK       0xf000
 154 +#define MTK_PHY_PLL_IR                 0xc10
 155 +#define MTK_PHY_PLL_IR_PE2H            BIT(17)
 156 +#define MTK_PHY_PLL_IR_PE2H_MASK       0xf0000
 157 +#define MTK_PHY_PLL_BP                 0xc14
 158 +#define MTK_PHY_PLL_BP_PE2H            (BIT(19) | BIT(17))
 159 +#define MTK_PHY_PLL_BP_PE2H_MASK       0xf0000
 160 +#define MTK_PHY_SSC_DELTA1             0xc3c
 161 +#define MTK_PHY_SSC_DELTA1_PE2H                (0x3c << 16)
 162 +#define MTK_PHY_SSC_DELTA1_PE2H_MASK   0xffff0000
 163 +#define MTK_PHY_SSC_DELTA              0xc48
 164 +#define MTK_PHY_SSC_DELTA_PE2H         0x36
 165 +#define MTK_PHY_SSC_DELTA_PE2H_MASK    0xffff
 166 +
 167 +#define MAX_PORT_NUM                   3
 168 +
 169 +struct mtk_pcie_port {
 170 +       int id;
 171 +       int enable;
 172 +       int irq;
 173 +       u32 link;
 174 +       void __iomem *phy_base;
 175 +       struct reset_control *rstc;
 176 +};
 177 +
 178 +#define mtk_foreach_port(pcie, p)                      \
 179 +               for ((p) = pcie->port;  \
 180 +                    (p) != &pcie->port[MAX_PORT_NUM]; (p)++)
 181 +
 182 +struct mtk_pcie {
 183 +       struct device *dev;
 184 +       void __iomem *pcie_base;
 185 +       struct regmap *hifsys;
 186 +
 187 +       struct resource io;
 188 +       struct resource pio;
 189 +       struct resource mem;
 190 +       struct resource prefetch;
 191 +       struct resource busn;
 192 +
 193 +       u32 io_bus_addr;
 194 +       u32 mem_bus_addr;
 195 +
 196 +       struct clk *clk;
 197 +
 198 +       struct mtk_pcie_port port[MAX_PORT_NUM];
 199 +       int pcie_card_link;
 200 +};
 201 +
 202 +static struct mtk_pcie_port_data {
 203 +       u32 base;
 204 +       u32 perst_n;
 205 +       u32 interrupt_en;
 206 +} mtk_pcie_port_data[MAX_PORT_NUM] = {
 207 +       { PCIEP0_BASE, BIT(1), BIT(20) },
 208 +       { PCIEP1_BASE, BIT(2), BIT(21) },
 209 +       { PCIEP2_BASE, BIT(3), BIT(22) },
 210 +};
 211 +
 212 +static const struct mtk_phy_init {
 213 +       uint32_t reg;
 214 +       uint32_t mask;
 215 +       uint32_t val;
 216 +} mtk_phy_init[] = {
 217 +       { MTK_PHY_REFCLK_SEL, MTK_PHY_XTAL_EXT_EN_MASK, MTK_PHY_XTAL_EXT_EN },
 218 +       { MTK_PHY_PLL, MTK_PHY_CLKDRV_AMP_MASK, MTK_PHY_CLKDRV_AMP },
 219 +       { MTK_PHY_CLK, MTK_PHY_CLKDRV_OFFSET_MASK, MTK_PHY_CLKDRV_OFFSET },
 220 +       { MTK_PHY_SSC_DELTA1, MTK_PHY_SSC_DELTA1_PE2H_MASK, MTK_PHY_SSC_DELTA1_PE2H },
 221 +       { MTK_PHY_SSC_DELTA, MTK_PHY_SSC_DELTA_PE2H_MASK, MTK_PHY_SSC_DELTA_PE2H },
 222 +       { MTK_PHY_PLL_IC, MTK_PHY_PLL_IC_BR_PE2H_MASK, MTK_PHY_PLL_IC_BR_PE2H },
 223 +       { MTK_PHY_PLL_BC, MTK_PHY_PLL_BC_PE2H_MASK, MTK_PHY_PLL_BC_PE2H },
 224 +       { MTK_PHY_PLL_IR, MTK_PHY_PLL_IR_PE2H_MASK, MTK_PHY_PLL_IR_PE2H },
 225 +       { MTK_PHY_PLL_IC, MTK_PHY_PLL_IC_PE2H_MASK, MTK_PHY_PLL_IC_PE2H },
 226 +       { MTK_PHY_PLL_BP, MTK_PHY_PLL_BP_PE2H_MASK, MTK_PHY_PLL_BP_PE2H },
 227 +};
 228 +
 229 +static struct mtk_pcie *sys_to_pcie(struct pci_sys_data *sys)
 230 +{
 231 +       return sys->private_data;
 232 +}
 233 +
 234 +static void pcie_w32(struct mtk_pcie *pcie, u32 val, unsigned reg)
 235 +{
 236 +       iowrite32(val, pcie->pcie_base + reg);
 237 +}
 238 +
 239 +static u32 pcie_r32(struct mtk_pcie *pcie, unsigned reg)
 240 +{
 241 +       return ioread32(pcie->pcie_base + reg);
 242 +}
 243 +
 244 +static void pcie_m32(struct mtk_pcie *pcie, u32 mask, u32 val, unsigned reg)
 245 +{
 246 +       u32 v = pcie_r32(pcie, reg);
 247 +
 248 +       v &= mask;
 249 +       v |= val;
 250 +       pcie_w32(pcie, v, reg);
 251 +}
 252 +
 253 +static int pcie_config_read(struct pci_bus *bus, unsigned int devfn, int where,
 254 +                           int size, u32 *val)
 255 +{
 256 +       struct mtk_pcie *pcie = sys_to_pcie(bus->sysdata);
 257 +       unsigned int slot = PCI_SLOT(devfn);
 258 +       u8 func = PCI_FUNC(devfn);
 259 +       u32 address;
 260 +       u32 data;
 261 +       u32 num = 0;
 262 +
 263 +       if (bus)
 264 +               num = bus->number;
 265 +
 266 +       address = (((where & 0xf00) >> 8) << 24) |
 267 +                 (num << 16) |
 268 +                 (slot << 11) |
 269 +                 (func << 8) |
 270 +                 (where & 0xfc);
 271 +
 272 +       pcie_w32(pcie, address, CFGADDR);
 273 +       data = pcie_r32(pcie, CFGDATA);
 274 +
 275 +       switch (size) {
 276 +       case 1:
 277 +               *val = (data >> ((where & 3) << 3)) & 0xff;
 278 +               break;
 279 +       case 2:
 280 +               *val = (data >> ((where & 3) << 3)) & 0xffff;
 281 +               break;
 282 +       case 4:
 283 +               *val = data;
 284 +               break;
 285 +       }
 286 +
 287 +       return PCIBIOS_SUCCESSFUL;
 288 +}
 289 +
 290 +static int pcie_config_write(struct pci_bus *bus, unsigned int devfn, int where,
 291 +                            int size, u32 val)
 292 +{
 293 +       struct mtk_pcie *pcie = sys_to_pcie(bus->sysdata);
 294 +       unsigned int slot = PCI_SLOT(devfn);
 295 +       u8 func = PCI_FUNC(devfn);
 296 +       u32 address;
 297 +       u32 data;
 298 +       u32 num = 0;
 299 +
 300 +       if (bus)
 301 +               num = bus->number;
 302 +
 303 +       address = (((where & 0xf00) >> 8) << 24) |
 304 +                 (num << 16) | (slot << 11) | (func << 8) | (where & 0xfc);
 305 +       pcie_w32(pcie, address, CFGADDR);
 306 +       data = pcie_r32(pcie, CFGDATA);
 307 +
 308 +       switch (size) {
 309 +       case 1:
 310 +               data = (data & ~(0xff << ((where & 3) << 3))) |
 311 +                      (val << ((where & 3) << 3));
 312 +               break;
 313 +       case 2:
 314 +               data = (data & ~(0xffff << ((where & 3) << 3))) |
 315 +                      (val << ((where & 3) << 3));
 316 +               break;
 317 +       case 4:
 318 +               data = val;
 319 +               break;
 320 +       }
 321 +       pcie_w32(pcie, data, CFGDATA);
 322 +
 323 +       return PCIBIOS_SUCCESSFUL;
 324 +}
 325 +
 326 +static struct pci_ops mtk_pcie_ops = {
 327 +       .read   = pcie_config_read,
 328 +       .write  = pcie_config_write,
 329 +};
 330 +
 331 +static int __init mtk_pcie_setup(int nr, struct pci_sys_data *sys)
 332 +{
 333 +       struct mtk_pcie *pcie = sys_to_pcie(sys);
 334 +
 335 +       request_resource(&ioport_resource, &pcie->pio);
 336 +       request_resource(&iomem_resource, &pcie->mem);
 337 +
 338 +       pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
 339 +       pci_add_resource_offset(&sys->resources, &pcie->pio, sys->io_offset);
 340 +       pci_add_resource(&sys->resources, &pcie->busn);
 341 +
 342 +       return 1;
 343 +}
 344 +
 345 +static struct pci_bus * __init mtk_pcie_scan_bus(int nr,
 346 +                                               struct pci_sys_data *sys)
 347 +{
 348 +       struct mtk_pcie *pcie = sys_to_pcie(sys);
 349 +       struct pci_bus *bus;
 350 +
 351 +       bus = pci_create_root_bus(pcie->dev, sys->busnr, &mtk_pcie_ops, sys,
 352 +                                 &sys->resources);
 353 +       if (!bus)
 354 +               return NULL;
 355 +
 356 +       pci_scan_child_bus(bus);
 357 +
 358 +       return bus;
 359 +}
 360 +
 361 +static int __init mtk_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 362 +{
 363 +       struct mtk_pcie *pcie = sys_to_pcie(dev->bus->sysdata);
 364 +       struct mtk_pcie_port *port;
 365 +       int irq = -1;
 366 +
 367 +       mtk_foreach_port(pcie, port)
 368 +               if (port->id == slot)
 369 +                       irq = port->irq;
 370 +
 371 +       return irq;
 372 +}
 373 +
 374 +static void mtk_pcie_configure_phy(struct mtk_pcie *pcie,
 375 +                                  struct mtk_pcie_port *port)
 376 +{
 377 +       int i;
 378 +
 379 +       for (i = 0; i < ARRAY_SIZE(mtk_phy_init); i++) {
 380 +               void __iomem *phy_addr = port->phy_base + mtk_phy_init[i].reg;
 381 +               u32 val = ioread32(phy_addr);
 382 +
 383 +               val &= ~mtk_phy_init[i].mask;
 384 +               val |= mtk_phy_init[i].val;
 385 +               iowrite32(val, phy_addr);
 386 +       }
 387 +       usleep_range(5000, 6000);
 388 +}
 389 +
 390 +static void mtk_pcie_configure_rc(struct mtk_pcie *pcie,
 391 +                                 struct mtk_pcie_port *port,
 392 +                                 struct pci_bus *bus)
 393 +{
 394 +       u32 val = 0;
 395 +
 396 +       pcie_config_write(bus,
 397 +                         port->id << 3,
 398 +                         PCI_BASE_ADDRESS_0, 4, MEMORY_BASE);
 399 +
 400 +       pcie_config_read(bus,
 401 +                        port->id << 3, PCI_BASE_ADDRESS_0, 4, &val);
 402 +
 403 +       /* Configure RC Credit */
 404 +       pcie_config_read(bus, port->id << 3, 0x73c, 4, &val);
 405 +       val &= ~(0x9fff) << 16;
 406 +       val |= 0x806c << 16;
 407 +       pcie_config_write(bus, port->id << 3, 0x73c, 4, val);
 408 +
 409 +       /* Configure RC FTS number */
 410 +       pcie_config_read(bus, port->id << 3, 0x70c, 4, &val);
 411 +       val &= ~(0xff3) << 8;
 412 +       val |= 0x50 << 8;
 413 +       pcie_config_write(bus, port->id << 3, 0x70c, 4, val);
 414 +}
 415 +
 416 +static int mtk_pcie_preinit(struct mtk_pcie *pcie)
 417 +{
 418 +       struct mtk_pcie_port *port;
 419 +       u32 val = 0;
 420 +       struct pci_bus bus;
 421 +       struct pci_sys_data sys;
 422 +
 423 +       memset(&bus, 0, sizeof(bus));
 424 +       memset(&sys, 0, sizeof(sys));
 425 +       bus.sysdata = (void *)&sys;
 426 +       sys.private_data = (void *)pcie;
 427 +
 428 +       pcibios_min_io = 0;
 429 +       pcibios_min_mem = 0;
 430 +
 431 +       /* The PHY on Port 2 is shared with USB */
 432 +       if (pcie->port[2].enable)
 433 +               regmap_update_bits(pcie->hifsys, HIFSYS_SYSCFG1,
 434 +                                  HIFSYS_SYSCFG1_PHY2_MASK, 0x0);
 435 +
 436 +       /* PCIe RC Reset */
 437 +       mtk_foreach_port(pcie, port)
 438 +               if (port->enable)
 439 +                       reset_control_assert(port->rstc);
 440 +       usleep_range(1000, 2000);
 441 +       mtk_foreach_port(pcie, port)
 442 +               if (port->enable)
 443 +                       reset_control_deassert(port->rstc);
 444 +       usleep_range(1000, 2000);
 445 +
 446 +       /* Configure PCIe PHY */
 447 +       mtk_foreach_port(pcie, port)
 448 +               if (port->enable)
 449 +                       mtk_pcie_configure_phy(pcie, port);
 450 +
 451 +       /* PCIe EP reset */
 452 +       val = 0;
 453 +       mtk_foreach_port(pcie, port)
 454 +               if (port->enable)
 455 +                       val |= mtk_pcie_port_data[port->id].perst_n;
 456 +       pcie_w32(pcie, pcie_r32(pcie, PCICFG) | val, PCICFG);
 457 +       usleep_range(1000, 2000);
 458 +       pcie_w32(pcie, pcie_r32(pcie, PCICFG) & ~val, PCICFG);
 459 +       usleep_range(1000, 2000);
 460 +       msleep(100);
 461 +
 462 +       /* check the link status */
 463 +       val = 0;
 464 +       mtk_foreach_port(pcie, port) {
 465 +               if (port->enable) {
 466 +                       u32 base = mtk_pcie_port_data[port->id].base;
 467 +
 468 +                       if ((pcie_r32(pcie, base + PCIE_SISTAT) & 0x1))
 469 +                               port->link = 1;
 470 +                       else
 471 +                               reset_control_assert(port->rstc);
 472 +               }
 473 +       }
 474 +
 475 +       mtk_foreach_port(pcie, port)
 476 +               if (port->link)
 477 +                       pcie->pcie_card_link++;
 478 +
 479 +       if (!pcie->pcie_card_link)
 480 +               return -ENODEV;
 481 +
 482 +       pcie_w32(pcie, pcie->mem_bus_addr, MEMBASE);
 483 +       pcie_w32(pcie, pcie->io_bus_addr, IOBASE);
 484 +
 485 +       mtk_foreach_port(pcie, port) {
 486 +               if (port->link) {
 487 +                       u32 base = mtk_pcie_port_data[port->id].base;
 488 +                       u32 inte = mtk_pcie_port_data[port->id].interrupt_en;
 489 +
 490 +                       pcie_m32(pcie, 0, inte, PCIENA);
 491 +                       pcie_w32(pcie, 0x7fff0001, base + BAR0SETUP);
 492 +                       pcie_w32(pcie, MEMORY_BASE, base + IMBASEBAR0);
 493 +                       pcie_w32(pcie, 0x06040001, base + PCIE_CLASS);
 494 +               }
 495 +       }
 496 +
 497 +       mtk_foreach_port(pcie, port)
 498 +               if (port->link)
 499 +                       mtk_pcie_configure_rc(pcie, port, &bus);
 500 +
 501 +       return 0;
 502 +}
 503 +
 504 +static int mtk_pcie_parse_dt(struct mtk_pcie *pcie)
 505 +{
 506 +       struct device_node *np = pcie->dev->of_node, *port;
 507 +       struct of_pci_range_parser parser;
 508 +       struct of_pci_range range;
 509 +       struct resource res;
 510 +       int err;
 511 +
 512 +       pcie->hifsys = syscon_regmap_lookup_by_phandle(np, "mediatek,hifsys");
 513 +       if (IS_ERR(pcie->hifsys)) {
 514 +               dev_err(pcie->dev, "missing \"mediatek,hifsys\" phandle\n");
 515 +               return PTR_ERR(pcie->hifsys);
 516 +       }
 517 +
 518 +       if (of_pci_range_parser_init(&parser, np)) {
 519 +               dev_err(pcie->dev, "missing \"ranges\" property\n");
 520 +               return -EINVAL;
 521 +       }
 522 +
 523 +       for_each_of_pci_range(&parser, &range) {
 524 +               err = of_pci_range_to_resource(&range, np, &res);
 525 +               if (err < 0) {
 526 +                       dev_err(pcie->dev, "failed to read resource range\n");
 527 +                       return err;
 528 +               }
 529 +
 530 +               switch (res.flags & IORESOURCE_TYPE_BITS) {
 531 +               case IORESOURCE_IO:
 532 +                       memcpy(&pcie->pio, &res, sizeof(res));
 533 +                       pcie->pio.start = (resource_size_t)range.pci_addr;
 534 +                       pcie->pio.end = (resource_size_t)
 535 +                                       (range.pci_addr + range.size - 1);
 536 +                       pcie->io_bus_addr = (resource_size_t)range.cpu_addr;
 537 +                       break;
 538 +
 539 +               case IORESOURCE_MEM:
 540 +                       if (res.flags & IORESOURCE_PREFETCH) {
 541 +                               memcpy(&pcie->prefetch, &res, sizeof(res));
 542 +                               pcie->prefetch.name = "prefetchable";
 543 +                               pcie->prefetch.start =
 544 +                                       (resource_size_t)range.pci_addr;
 545 +                               pcie->prefetch.end = (resource_size_t)
 546 +                                       (range.pci_addr + range.size - 1);
 547 +                       } else {
 548 +                               memcpy(&pcie->mem, &res, sizeof(res));
 549 +                               pcie->mem.name = "non-prefetchable";
 550 +                               pcie->mem.start = (resource_size_t)
 551 +                                       range.pci_addr;
 552 +                               pcie->prefetch.end = (resource_size_t)
 553 +                                       (range.pci_addr + range.size - 1);
 554 +                               pcie->mem_bus_addr = (resource_size_t)
 555 +                                       range.cpu_addr;
 556 +                       }
 557 +                       break;
 558 +               }
 559 +       }
 560 +
 561 +       err = of_pci_parse_bus_range(np, &pcie->busn);
 562 +       if (err < 0) {
 563 +               dev_err(pcie->dev, "failed to parse ranges property: %d\n",
 564 +                       err);
 565 +               pcie->busn.name = np->name;
 566 +               pcie->busn.start = 0;
 567 +               pcie->busn.end = 0xff;
 568 +               pcie->busn.flags = IORESOURCE_BUS;
 569 +       }
 570 +
 571 +       /* parse root ports */
 572 +       for_each_child_of_node(np, port) {
 573 +               unsigned int index;
 574 +               char rst[] = "pcie0";
 575 +
 576 +               err = of_pci_get_devfn(port);
 577 +               if (err < 0) {
 578 +                       dev_err(pcie->dev, "failed to parse address: %d\n",
 579 +                               err);
 580 +                       return err;
 581 +               }
 582 +
 583 +               index = PCI_SLOT(err);
 584 +               if (index > MAX_PORT_NUM) {
 585 +                       dev_err(pcie->dev, "invalid port number: %d\n", index);
 586 +                       continue;
 587 +               }
 588 +               index--;
 589 +               pcie->port[index].id = index;
 590 +
 591 +               if (!of_device_is_available(port))
 592 +                       continue;
 593 +
 594 +               rst[4] += index;
 595 +               pcie->port[index].rstc = devm_reset_control_get(pcie->dev,
 596 +                                                                  rst);
 597 +               if (!IS_ERR(pcie->port[index].rstc))
 598 +                       pcie->port[index].enable = 1;
 599 +       }
 600 +       return 0;
 601 +}
 602 +
 603 +static int mtk_pcie_get_resources(struct mtk_pcie *pcie)
 604 +{
 605 +       struct platform_device *pdev = to_platform_device(pcie->dev);
 606 +       struct mtk_pcie_port *port;
 607 +       struct resource *res;
 608 +
 609 +       pcie->clk = devm_clk_get(&pdev->dev, "pcie");
 610 +       if (IS_ERR(pcie->clk)) {
 611 +               dev_err(&pdev->dev, "Failed to get pcie clk\n");
 612 +               return PTR_ERR(pcie->clk);
 613 +       }
 614 +
 615 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 616 +       pcie->pcie_base = devm_ioremap_resource(&pdev->dev, res);
 617 +       if (IS_ERR(pcie->pcie_base)) {
 618 +               dev_err(&pdev->dev, "Failed to get pcie range\n");
 619 +               return PTR_ERR(pcie->pcie_base);
 620 +       }
 621 +
 622 +       mtk_foreach_port(pcie, port) {
 623 +               if (!port->enable)
 624 +                       continue;
 625 +               res = platform_get_resource(pdev, IORESOURCE_MEM, port->id + 1);
 626 +               port->phy_base = devm_ioremap_resource(&pdev->dev, res);
 627 +               if (IS_ERR(port->phy_base)) {
 628 +                       dev_err(&pdev->dev, "Failed to get pcie phy%d range %p\n",
 629 +                               port->id, port->phy_base);
 630 +                       return PTR_ERR(port->phy_base);
 631 +               }
 632 +               port->irq = platform_get_irq(pdev, port->id);
 633 +       }
 634 +
 635 +       return clk_prepare_enable(pcie->clk);
 636 +}
 637 +
 638 +static int mtk_pcie_probe(struct platform_device *pdev)
 639 +{
 640 +       struct mtk_pcie *pcie;
 641 +       struct hw_pci hw;
 642 +       int ret;
 643 +
 644 +       pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
 645 +       if (!pcie)
 646 +               return -ENOMEM;
 647 +
 648 +       pcie->dev = &pdev->dev;
 649 +       ret = mtk_pcie_parse_dt(pcie);
 650 +       if (ret < 0)
 651 +               return ret;
 652 +
 653 +       pm_runtime_enable(&pdev->dev);
 654 +       pm_runtime_get_sync(&pdev->dev);
 655 +
 656 +       ret = mtk_pcie_get_resources(pcie);
 657 +       if (ret < 0) {
 658 +               dev_err(&pdev->dev, "failed to request resources: %d\n", ret);
 659 +               goto err_out;
 660 +       }
 661 +
 662 +       ret = mtk_pcie_preinit(pcie);
 663 +       if (ret)
 664 +               return ret;
 665 +
 666 +       memset(&hw, 0, sizeof(hw));
 667 +       hw.nr_controllers = 1;
 668 +       hw.private_data = (void **)&pcie;
 669 +       hw.setup = mtk_pcie_setup;
 670 +       hw.map_irq = mtk_pcie_map_irq;
 671 +       hw.scan = mtk_pcie_scan_bus;
 672 +
 673 +       pci_common_init_dev(pcie->dev, &hw);
 674 +       platform_set_drvdata(pdev, pcie);
 675 +
 676 +       return 0;
 677 +
 678 +err_out:
 679 +       clk_disable_unprepare(pcie->clk);
 680 +       pm_runtime_put_sync(&pdev->dev);
 681 +       pm_runtime_disable(&pdev->dev);
 682 +
 683 +       return ret;
 684 +}
 685 +
 686 +static const struct of_device_id mtk_pcie_ids[] = {
 687 +       { .compatible = "mediatek,mt2701-pcie" },
 688 +       { .compatible = "mediatek,mt7623-pcie" },
 689 +       {},
 690 +};
 691 +MODULE_DEVICE_TABLE(of, mtk_pcie_ids);
 692 +
 693 +static struct platform_driver mtk_pcie_driver = {
 694 +       .probe = mtk_pcie_probe,
 695 +       .driver = {
 696 +               .name = "mediatek-pcie",
 697 +               .owner = THIS_MODULE,
 698 +               .of_match_table = of_match_ptr(mtk_pcie_ids),
 699 +       },
 700 +};
 701 +
 702 +static int __init mtk_pcie_init(void)
 703 +{
 704 +       return platform_driver_register(&mtk_pcie_driver);
 705 +}
 706 +
 707 +module_init(mtk_pcie_init);
 708 --
 709 1.7.10.4
 710