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ramips: fix the number of uarts for MT7688
[openwrt/openwrt.git] / target / linux / mediatek / patches-4.4 / 0045-mfd-mt6397-add-MT6323-support-to-MT6397-driver.patch
1 From 0ae7153c9f00361c3e6dac9da0c2d994557953f5 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Fri, 8 Jan 2016 04:09:43 +0100
4 Subject: [PATCH 045/102] mfd: mt6397: add MT6323 support to MT6397 driver
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 drivers/mfd/mt6397-core.c | 20 ++
9 include/linux/mfd/mt6323/core.h | 36 +++
10 include/linux/mfd/mt6323/registers.h | 408 ++++++++++++++++++++++++++++++++++
11 3 files changed, 464 insertions(+)
12 create mode 100644 include/linux/mfd/mt6323/core.h
13 create mode 100644 include/linux/mfd/mt6323/registers.h
14
15 --- a/drivers/mfd/mt6397-core.c
16 +++ b/drivers/mfd/mt6397-core.c
17 @@ -19,11 +19,14 @@
18 #include <linux/regmap.h>
19 #include <linux/mfd/core.h>
20 #include <linux/mfd/mt6397/core.h>
21 +#include <linux/mfd/mt6323/core.h>
22 #include <linux/mfd/mt6397/registers.h>
23 +#include <linux/mfd/mt6323/registers.h>
24
25 #define MT6397_RTC_BASE 0xe000
26 #define MT6397_RTC_SIZE 0x3e
27
28 +#define MT6323_CID_CODE 0x23
29 #define MT6391_CID_CODE 0x91
30 #define MT6397_CID_CODE 0x97
31
32 @@ -40,6 +43,13 @@ static const struct resource mt6397_rtc_
33 },
34 };
35
36 +static const struct mfd_cell mt6323_devs[] = {
37 + {
38 + .name = "mt6323-regulator",
39 + .of_compatible = "mediatek,mt6323-regulator"
40 + },
41 +};
42 +
43 static const struct mfd_cell mt6397_devs[] = {
44 {
45 .name = "mt6397-rtc",
46 @@ -261,6 +271,15 @@ static int mt6397_probe(struct platform_
47 }
48
49 switch (id & 0xff) {
50 + case MT6323_CID_CODE:
51 + pmic->int_con[0] = MT6323_INT_CON0;
52 + pmic->int_con[1] = MT6323_INT_CON1;
53 + pmic->int_status[0] = MT6323_INT_STATUS0;
54 + pmic->int_status[1] = MT6323_INT_STATUS1;
55 + ret = mfd_add_devices(&pdev->dev, -1, mt6323_devs,
56 + ARRAY_SIZE(mt6323_devs), NULL, 0, NULL);
57 + break;
58 +
59 case MT6397_CID_CODE:
60 case MT6391_CID_CODE:
61 pmic->int_con[0] = MT6397_INT_CON0;
62 @@ -302,6 +321,7 @@ static int mt6397_remove(struct platform
63
64 static const struct of_device_id mt6397_of_match[] = {
65 { .compatible = "mediatek,mt6397" },
66 + { .compatible = "mediatek,mt6323" },
67 { }
68 };
69 MODULE_DEVICE_TABLE(of, mt6397_of_match);
70 --- /dev/null
71 +++ b/include/linux/mfd/mt6323/core.h
72 @@ -0,0 +1,36 @@
73 +/*
74 + * Copyright (c) 2016 Chen Zhong <chen.zhong@mediatek.com>
75 + *
76 + * This program is free software; you can redistribute it and/or modify
77 + * it under the terms of the GNU General Public License version 2 as
78 + * published by the Free Software Foundation.
79 + */
80 +
81 +#ifndef __MFD_MT6323_CORE_H__
82 +#define __MFD_MT6323_CORE_H__
83 +
84 +enum MT6323_IRQ_STATUS_numbers {
85 + MT6323_IRQ_STATUS_SPKL_AB = 0,
86 + MT6323_IRQ_STATUS_SPKL,
87 + MT6323_IRQ_STATUS_BAT_L,
88 + MT6323_IRQ_STATUS_BAT_H,
89 + MT6323_IRQ_STATUS_WATCHDOG,
90 + MT6323_IRQ_STATUS_PWRKEY,
91 + MT6323_IRQ_STATUS_THR_L,
92 + MT6323_IRQ_STATUS_THR_H,
93 + MT6323_IRQ_STATUS_VBATON_UNDET,
94 + MT6323_IRQ_STATUS_BVALID_DET,
95 + MT6323_IRQ_STATUS_CHRDET,
96 + MT6323_IRQ_STATUS_OV,
97 + MT6323_IRQ_STATUS_LDO = 16,
98 + MT6323_IRQ_STATUS_FCHRKEY,
99 + MT6323_IRQ_STATUS_ACCDET,
100 + MT6323_IRQ_STATUS_AUDIO,
101 + MT6323_IRQ_STATUS_RTC,
102 + MT6323_IRQ_STATUS_VPROC,
103 + MT6323_IRQ_STATUS_VSYS,
104 + MT6323_IRQ_STATUS_VPA,
105 + MT6323_IRQ_STATUS_NR,
106 +};
107 +
108 +#endif /* __MFD_MT6323_CORE_H__ */
109 --- /dev/null
110 +++ b/include/linux/mfd/mt6323/registers.h
111 @@ -0,0 +1,408 @@
112 +/*
113 + * Copyright (c) 2016 Chen Zhong <chen.zhong@mediatek.com>
114 + *
115 + * This program is free software; you can redistribute it and/or modify
116 + * it under the terms of the GNU General Public License version 2 as
117 + * published by the Free Software Foundation.
118 + */
119 +
120 +#ifndef __MFD_MT6323_REGISTERS_H__
121 +#define __MFD_MT6323_REGISTERS_H__
122 +
123 +/* PMIC Registers */
124 +#define MT6323_CHR_CON0 0x0000
125 +#define MT6323_CHR_CON1 0x0002
126 +#define MT6323_CHR_CON2 0x0004
127 +#define MT6323_CHR_CON3 0x0006
128 +#define MT6323_CHR_CON4 0x0008
129 +#define MT6323_CHR_CON5 0x000A
130 +#define MT6323_CHR_CON6 0x000C
131 +#define MT6323_CHR_CON7 0x000E
132 +#define MT6323_CHR_CON8 0x0010
133 +#define MT6323_CHR_CON9 0x0012
134 +#define MT6323_CHR_CON10 0x0014
135 +#define MT6323_CHR_CON11 0x0016
136 +#define MT6323_CHR_CON12 0x0018
137 +#define MT6323_CHR_CON13 0x001A
138 +#define MT6323_CHR_CON14 0x001C
139 +#define MT6323_CHR_CON15 0x001E
140 +#define MT6323_CHR_CON16 0x0020
141 +#define MT6323_CHR_CON17 0x0022
142 +#define MT6323_CHR_CON18 0x0024
143 +#define MT6323_CHR_CON19 0x0026
144 +#define MT6323_CHR_CON20 0x0028
145 +#define MT6323_CHR_CON21 0x002A
146 +#define MT6323_CHR_CON22 0x002C
147 +#define MT6323_CHR_CON23 0x002E
148 +#define MT6323_CHR_CON24 0x0030
149 +#define MT6323_CHR_CON25 0x0032
150 +#define MT6323_CHR_CON26 0x0034
151 +#define MT6323_CHR_CON27 0x0036
152 +#define MT6323_CHR_CON28 0x0038
153 +#define MT6323_CHR_CON29 0x003A
154 +#define MT6323_STRUP_CON0 0x003C
155 +#define MT6323_STRUP_CON2 0x003E
156 +#define MT6323_STRUP_CON3 0x0040
157 +#define MT6323_STRUP_CON4 0x0042
158 +#define MT6323_STRUP_CON5 0x0044
159 +#define MT6323_STRUP_CON6 0x0046
160 +#define MT6323_STRUP_CON7 0x0048
161 +#define MT6323_STRUP_CON8 0x004A
162 +#define MT6323_STRUP_CON9 0x004C
163 +#define MT6323_STRUP_CON10 0x004E
164 +#define MT6323_STRUP_CON11 0x0050
165 +#define MT6323_SPK_CON0 0x0052
166 +#define MT6323_SPK_CON1 0x0054
167 +#define MT6323_SPK_CON2 0x0056
168 +#define MT6323_SPK_CON6 0x005E
169 +#define MT6323_SPK_CON7 0x0060
170 +#define MT6323_SPK_CON8 0x0062
171 +#define MT6323_SPK_CON9 0x0064
172 +#define MT6323_SPK_CON10 0x0066
173 +#define MT6323_SPK_CON11 0x0068
174 +#define MT6323_SPK_CON12 0x006A
175 +#define MT6323_CID 0x0100
176 +#define MT6323_TOP_CKPDN0 0x0102
177 +#define MT6323_TOP_CKPDN0_SET 0x0104
178 +#define MT6323_TOP_CKPDN0_CLR 0x0106
179 +#define MT6323_TOP_CKPDN1 0x0108
180 +#define MT6323_TOP_CKPDN1_SET 0x010A
181 +#define MT6323_TOP_CKPDN1_CLR 0x010C
182 +#define MT6323_TOP_CKPDN2 0x010E
183 +#define MT6323_TOP_CKPDN2_SET 0x0110
184 +#define MT6323_TOP_CKPDN2_CLR 0x0112
185 +#define MT6323_TOP_RST_CON 0x0114
186 +#define MT6323_TOP_RST_CON_SET 0x0116
187 +#define MT6323_TOP_RST_CON_CLR 0x0118
188 +#define MT6323_TOP_RST_MISC 0x011A
189 +#define MT6323_TOP_RST_MISC_SET 0x011C
190 +#define MT6323_TOP_RST_MISC_CLR 0x011E
191 +#define MT6323_TOP_CKCON0 0x0120
192 +#define MT6323_TOP_CKCON0_SET 0x0122
193 +#define MT6323_TOP_CKCON0_CLR 0x0124
194 +#define MT6323_TOP_CKCON1 0x0126
195 +#define MT6323_TOP_CKCON1_SET 0x0128
196 +#define MT6323_TOP_CKCON1_CLR 0x012A
197 +#define MT6323_TOP_CKTST0 0x012C
198 +#define MT6323_TOP_CKTST1 0x012E
199 +#define MT6323_TOP_CKTST2 0x0130
200 +#define MT6323_TEST_OUT 0x0132
201 +#define MT6323_TEST_CON0 0x0134
202 +#define MT6323_TEST_CON1 0x0136
203 +#define MT6323_EN_STATUS0 0x0138
204 +#define MT6323_EN_STATUS1 0x013A
205 +#define MT6323_OCSTATUS0 0x013C
206 +#define MT6323_OCSTATUS1 0x013E
207 +#define MT6323_PGSTATUS 0x0140
208 +#define MT6323_CHRSTATUS 0x0142
209 +#define MT6323_TDSEL_CON 0x0144
210 +#define MT6323_RDSEL_CON 0x0146
211 +#define MT6323_SMT_CON0 0x0148
212 +#define MT6323_SMT_CON1 0x014A
213 +#define MT6323_SMT_CON2 0x014C
214 +#define MT6323_SMT_CON3 0x014E
215 +#define MT6323_SMT_CON4 0x0150
216 +#define MT6323_DRV_CON0 0x0152
217 +#define MT6323_DRV_CON1 0x0154
218 +#define MT6323_DRV_CON2 0x0156
219 +#define MT6323_DRV_CON3 0x0158
220 +#define MT6323_DRV_CON4 0x015A
221 +#define MT6323_SIMLS1_CON 0x015C
222 +#define MT6323_SIMLS2_CON 0x015E
223 +#define MT6323_INT_CON0 0x0160
224 +#define MT6323_INT_CON0_SET 0x0162
225 +#define MT6323_INT_CON0_CLR 0x0164
226 +#define MT6323_INT_CON1 0x0166
227 +#define MT6323_INT_CON1_SET 0x0168
228 +#define MT6323_INT_CON1_CLR 0x016A
229 +#define MT6323_INT_MISC_CON 0x016C
230 +#define MT6323_INT_MISC_CON_SET 0x016E
231 +#define MT6323_INT_MISC_CON_CLR 0x0170
232 +#define MT6323_INT_STATUS0 0x0172
233 +#define MT6323_INT_STATUS1 0x0174
234 +#define MT6323_OC_GEAR_0 0x0176
235 +#define MT6323_OC_GEAR_1 0x0178
236 +#define MT6323_OC_GEAR_2 0x017A
237 +#define MT6323_OC_CTL_VPROC 0x017C
238 +#define MT6323_OC_CTL_VSYS 0x017E
239 +#define MT6323_OC_CTL_VPA 0x0180
240 +#define MT6323_FQMTR_CON0 0x0182
241 +#define MT6323_FQMTR_CON1 0x0184
242 +#define MT6323_FQMTR_CON2 0x0186
243 +#define MT6323_RG_SPI_CON 0x0188
244 +#define MT6323_DEW_DIO_EN 0x018A
245 +#define MT6323_DEW_READ_TEST 0x018C
246 +#define MT6323_DEW_WRITE_TEST 0x018E
247 +#define MT6323_DEW_CRC_SWRST 0x0190
248 +#define MT6323_DEW_CRC_EN 0x0192
249 +#define MT6323_DEW_CRC_VAL 0x0194
250 +#define MT6323_DEW_DBG_MON_SEL 0x0196
251 +#define MT6323_DEW_CIPHER_KEY_SEL 0x0198
252 +#define MT6323_DEW_CIPHER_IV_SEL 0x019A
253 +#define MT6323_DEW_CIPHER_EN 0x019C
254 +#define MT6323_DEW_CIPHER_RDY 0x019E
255 +#define MT6323_DEW_CIPHER_MODE 0x01A0
256 +#define MT6323_DEW_CIPHER_SWRST 0x01A2
257 +#define MT6323_DEW_RDDMY_NO 0x01A4
258 +#define MT6323_DEW_RDATA_DLY_SEL 0x01A6
259 +#define MT6323_BUCK_CON0 0x0200
260 +#define MT6323_BUCK_CON1 0x0202
261 +#define MT6323_BUCK_CON2 0x0204
262 +#define MT6323_BUCK_CON3 0x0206
263 +#define MT6323_BUCK_CON4 0x0208
264 +#define MT6323_BUCK_CON5 0x020A
265 +#define MT6323_VPROC_CON0 0x020C
266 +#define MT6323_VPROC_CON1 0x020E
267 +#define MT6323_VPROC_CON2 0x0210
268 +#define MT6323_VPROC_CON3 0x0212
269 +#define MT6323_VPROC_CON4 0x0214
270 +#define MT6323_VPROC_CON5 0x0216
271 +#define MT6323_VPROC_CON7 0x021A
272 +#define MT6323_VPROC_CON8 0x021C
273 +#define MT6323_VPROC_CON9 0x021E
274 +#define MT6323_VPROC_CON10 0x0220
275 +#define MT6323_VPROC_CON11 0x0222
276 +#define MT6323_VPROC_CON12 0x0224
277 +#define MT6323_VPROC_CON13 0x0226
278 +#define MT6323_VPROC_CON14 0x0228
279 +#define MT6323_VPROC_CON15 0x022A
280 +#define MT6323_VPROC_CON18 0x0230
281 +#define MT6323_VSYS_CON0 0x0232
282 +#define MT6323_VSYS_CON1 0x0234
283 +#define MT6323_VSYS_CON2 0x0236
284 +#define MT6323_VSYS_CON3 0x0238
285 +#define MT6323_VSYS_CON4 0x023A
286 +#define MT6323_VSYS_CON5 0x023C
287 +#define MT6323_VSYS_CON7 0x0240
288 +#define MT6323_VSYS_CON8 0x0242
289 +#define MT6323_VSYS_CON9 0x0244
290 +#define MT6323_VSYS_CON10 0x0246
291 +#define MT6323_VSYS_CON11 0x0248
292 +#define MT6323_VSYS_CON12 0x024A
293 +#define MT6323_VSYS_CON13 0x024C
294 +#define MT6323_VSYS_CON14 0x024E
295 +#define MT6323_VSYS_CON15 0x0250
296 +#define MT6323_VSYS_CON18 0x0256
297 +#define MT6323_VPA_CON0 0x0300
298 +#define MT6323_VPA_CON1 0x0302
299 +#define MT6323_VPA_CON2 0x0304
300 +#define MT6323_VPA_CON3 0x0306
301 +#define MT6323_VPA_CON4 0x0308
302 +#define MT6323_VPA_CON5 0x030A
303 +#define MT6323_VPA_CON7 0x030E
304 +#define MT6323_VPA_CON8 0x0310
305 +#define MT6323_VPA_CON9 0x0312
306 +#define MT6323_VPA_CON10 0x0314
307 +#define MT6323_VPA_CON11 0x0316
308 +#define MT6323_VPA_CON12 0x0318
309 +#define MT6323_VPA_CON14 0x031C
310 +#define MT6323_VPA_CON16 0x0320
311 +#define MT6323_VPA_CON17 0x0322
312 +#define MT6323_VPA_CON18 0x0324
313 +#define MT6323_VPA_CON19 0x0326
314 +#define MT6323_VPA_CON20 0x0328
315 +#define MT6323_BUCK_K_CON0 0x032A
316 +#define MT6323_BUCK_K_CON1 0x032C
317 +#define MT6323_BUCK_K_CON2 0x032E
318 +#define MT6323_ISINK0_CON0 0x0330
319 +#define MT6323_ISINK0_CON1 0x0332
320 +#define MT6323_ISINK0_CON2 0x0334
321 +#define MT6323_ISINK0_CON3 0x0336
322 +#define MT6323_ISINK1_CON0 0x0338
323 +#define MT6323_ISINK1_CON1 0x033A
324 +#define MT6323_ISINK1_CON2 0x033C
325 +#define MT6323_ISINK1_CON3 0x033E
326 +#define MT6323_ISINK2_CON0 0x0340
327 +#define MT6323_ISINK2_CON1 0x0342
328 +#define MT6323_ISINK2_CON2 0x0344
329 +#define MT6323_ISINK2_CON3 0x0346
330 +#define MT6323_ISINK3_CON0 0x0348
331 +#define MT6323_ISINK3_CON1 0x034A
332 +#define MT6323_ISINK3_CON2 0x034C
333 +#define MT6323_ISINK3_CON3 0x034E
334 +#define MT6323_ISINK_ANA0 0x0350
335 +#define MT6323_ISINK_ANA1 0x0352
336 +#define MT6323_ISINK_PHASE_DLY 0x0354
337 +#define MT6323_ISINK_EN_CTRL 0x0356
338 +#define MT6323_ANALDO_CON0 0x0400
339 +#define MT6323_ANALDO_CON1 0x0402
340 +#define MT6323_ANALDO_CON2 0x0404
341 +#define MT6323_ANALDO_CON3 0x0406
342 +#define MT6323_ANALDO_CON4 0x0408
343 +#define MT6323_ANALDO_CON5 0x040A
344 +#define MT6323_ANALDO_CON6 0x040C
345 +#define MT6323_ANALDO_CON7 0x040E
346 +#define MT6323_ANALDO_CON8 0x0410
347 +#define MT6323_ANALDO_CON10 0x0412
348 +#define MT6323_ANALDO_CON15 0x0414
349 +#define MT6323_ANALDO_CON16 0x0416
350 +#define MT6323_ANALDO_CON17 0x0418
351 +#define MT6323_ANALDO_CON18 0x041A
352 +#define MT6323_ANALDO_CON19 0x041C
353 +#define MT6323_ANALDO_CON20 0x041E
354 +#define MT6323_ANALDO_CON21 0x0420
355 +#define MT6323_DIGLDO_CON0 0x0500
356 +#define MT6323_DIGLDO_CON2 0x0502
357 +#define MT6323_DIGLDO_CON3 0x0504
358 +#define MT6323_DIGLDO_CON5 0x0506
359 +#define MT6323_DIGLDO_CON6 0x0508
360 +#define MT6323_DIGLDO_CON7 0x050A
361 +#define MT6323_DIGLDO_CON8 0x050C
362 +#define MT6323_DIGLDO_CON9 0x050E
363 +#define MT6323_DIGLDO_CON10 0x0510
364 +#define MT6323_DIGLDO_CON11 0x0512
365 +#define MT6323_DIGLDO_CON12 0x0514
366 +#define MT6323_DIGLDO_CON13 0x0516
367 +#define MT6323_DIGLDO_CON14 0x0518
368 +#define MT6323_DIGLDO_CON15 0x051A
369 +#define MT6323_DIGLDO_CON16 0x051C
370 +#define MT6323_DIGLDO_CON17 0x051E
371 +#define MT6323_DIGLDO_CON18 0x0520
372 +#define MT6323_DIGLDO_CON19 0x0522
373 +#define MT6323_DIGLDO_CON20 0x0524
374 +#define MT6323_DIGLDO_CON21 0x0526
375 +#define MT6323_DIGLDO_CON23 0x0528
376 +#define MT6323_DIGLDO_CON24 0x052A
377 +#define MT6323_DIGLDO_CON26 0x052C
378 +#define MT6323_DIGLDO_CON27 0x052E
379 +#define MT6323_DIGLDO_CON28 0x0530
380 +#define MT6323_DIGLDO_CON29 0x0532
381 +#define MT6323_DIGLDO_CON30 0x0534
382 +#define MT6323_DIGLDO_CON31 0x0536
383 +#define MT6323_DIGLDO_CON32 0x0538
384 +#define MT6323_DIGLDO_CON33 0x053A
385 +#define MT6323_DIGLDO_CON34 0x053C
386 +#define MT6323_DIGLDO_CON35 0x053E
387 +#define MT6323_DIGLDO_CON36 0x0540
388 +#define MT6323_DIGLDO_CON39 0x0542
389 +#define MT6323_DIGLDO_CON40 0x0544
390 +#define MT6323_DIGLDO_CON41 0x0546
391 +#define MT6323_DIGLDO_CON42 0x0548
392 +#define MT6323_DIGLDO_CON43 0x054A
393 +#define MT6323_DIGLDO_CON44 0x054C
394 +#define MT6323_DIGLDO_CON45 0x054E
395 +#define MT6323_DIGLDO_CON46 0x0550
396 +#define MT6323_DIGLDO_CON47 0x0552
397 +#define MT6323_DIGLDO_CON48 0x0554
398 +#define MT6323_DIGLDO_CON49 0x0556
399 +#define MT6323_DIGLDO_CON50 0x0558
400 +#define MT6323_DIGLDO_CON51 0x055A
401 +#define MT6323_DIGLDO_CON52 0x055C
402 +#define MT6323_DIGLDO_CON53 0x055E
403 +#define MT6323_DIGLDO_CON54 0x0560
404 +#define MT6323_EFUSE_CON0 0x0600
405 +#define MT6323_EFUSE_CON1 0x0602
406 +#define MT6323_EFUSE_CON2 0x0604
407 +#define MT6323_EFUSE_CON3 0x0606
408 +#define MT6323_EFUSE_CON4 0x0608
409 +#define MT6323_EFUSE_CON5 0x060A
410 +#define MT6323_EFUSE_CON6 0x060C
411 +#define MT6323_EFUSE_VAL_0_15 0x060E
412 +#define MT6323_EFUSE_VAL_16_31 0x0610
413 +#define MT6323_EFUSE_VAL_32_47 0x0612
414 +#define MT6323_EFUSE_VAL_48_63 0x0614
415 +#define MT6323_EFUSE_VAL_64_79 0x0616
416 +#define MT6323_EFUSE_VAL_80_95 0x0618
417 +#define MT6323_EFUSE_VAL_96_111 0x061A
418 +#define MT6323_EFUSE_VAL_112_127 0x061C
419 +#define MT6323_EFUSE_VAL_128_143 0x061E
420 +#define MT6323_EFUSE_VAL_144_159 0x0620
421 +#define MT6323_EFUSE_VAL_160_175 0x0622
422 +#define MT6323_EFUSE_VAL_176_191 0x0624
423 +#define MT6323_EFUSE_DOUT_0_15 0x0626
424 +#define MT6323_EFUSE_DOUT_16_31 0x0628
425 +#define MT6323_EFUSE_DOUT_32_47 0x062A
426 +#define MT6323_EFUSE_DOUT_48_63 0x062C
427 +#define MT6323_EFUSE_DOUT_64_79 0x062E
428 +#define MT6323_EFUSE_DOUT_80_95 0x0630
429 +#define MT6323_EFUSE_DOUT_96_111 0x0632
430 +#define MT6323_EFUSE_DOUT_112_127 0x0634
431 +#define MT6323_EFUSE_DOUT_128_143 0x0636
432 +#define MT6323_EFUSE_DOUT_144_159 0x0638
433 +#define MT6323_EFUSE_DOUT_160_175 0x063A
434 +#define MT6323_EFUSE_DOUT_176_191 0x063C
435 +#define MT6323_EFUSE_CON7 0x063E
436 +#define MT6323_EFUSE_CON8 0x0640
437 +#define MT6323_EFUSE_CON9 0x0642
438 +#define MT6323_RTC_MIX_CON0 0x0644
439 +#define MT6323_RTC_MIX_CON1 0x0646
440 +#define MT6323_AUDTOP_CON0 0x0700
441 +#define MT6323_AUDTOP_CON1 0x0702
442 +#define MT6323_AUDTOP_CON2 0x0704
443 +#define MT6323_AUDTOP_CON3 0x0706
444 +#define MT6323_AUDTOP_CON4 0x0708
445 +#define MT6323_AUDTOP_CON5 0x070A
446 +#define MT6323_AUDTOP_CON6 0x070C
447 +#define MT6323_AUDTOP_CON7 0x070E
448 +#define MT6323_AUDTOP_CON8 0x0710
449 +#define MT6323_AUDTOP_CON9 0x0712
450 +#define MT6323_AUXADC_ADC0 0x0714
451 +#define MT6323_AUXADC_ADC1 0x0716
452 +#define MT6323_AUXADC_ADC2 0x0718
453 +#define MT6323_AUXADC_ADC3 0x071A
454 +#define MT6323_AUXADC_ADC4 0x071C
455 +#define MT6323_AUXADC_ADC5 0x071E
456 +#define MT6323_AUXADC_ADC6 0x0720
457 +#define MT6323_AUXADC_ADC7 0x0722
458 +#define MT6323_AUXADC_ADC8 0x0724
459 +#define MT6323_AUXADC_ADC9 0x0726
460 +#define MT6323_AUXADC_ADC10 0x0728
461 +#define MT6323_AUXADC_ADC11 0x072A
462 +#define MT6323_AUXADC_ADC12 0x072C
463 +#define MT6323_AUXADC_ADC13 0x072E
464 +#define MT6323_AUXADC_ADC14 0x0730
465 +#define MT6323_AUXADC_ADC15 0x0732
466 +#define MT6323_AUXADC_ADC16 0x0734
467 +#define MT6323_AUXADC_ADC17 0x0736
468 +#define MT6323_AUXADC_ADC18 0x0738
469 +#define MT6323_AUXADC_ADC19 0x073A
470 +#define MT6323_AUXADC_ADC20 0x073C
471 +#define MT6323_AUXADC_RSV1 0x073E
472 +#define MT6323_AUXADC_RSV2 0x0740
473 +#define MT6323_AUXADC_CON0 0x0742
474 +#define MT6323_AUXADC_CON1 0x0744
475 +#define MT6323_AUXADC_CON2 0x0746
476 +#define MT6323_AUXADC_CON3 0x0748
477 +#define MT6323_AUXADC_CON4 0x074A
478 +#define MT6323_AUXADC_CON5 0x074C
479 +#define MT6323_AUXADC_CON6 0x074E
480 +#define MT6323_AUXADC_CON7 0x0750
481 +#define MT6323_AUXADC_CON8 0x0752
482 +#define MT6323_AUXADC_CON9 0x0754
483 +#define MT6323_AUXADC_CON10 0x0756
484 +#define MT6323_AUXADC_CON11 0x0758
485 +#define MT6323_AUXADC_CON12 0x075A
486 +#define MT6323_AUXADC_CON13 0x075C
487 +#define MT6323_AUXADC_CON14 0x075E
488 +#define MT6323_AUXADC_CON15 0x0760
489 +#define MT6323_AUXADC_CON16 0x0762
490 +#define MT6323_AUXADC_CON17 0x0764
491 +#define MT6323_AUXADC_CON18 0x0766
492 +#define MT6323_AUXADC_CON19 0x0768
493 +#define MT6323_AUXADC_CON20 0x076A
494 +#define MT6323_AUXADC_CON21 0x076C
495 +#define MT6323_AUXADC_CON22 0x076E
496 +#define MT6323_AUXADC_CON23 0x0770
497 +#define MT6323_AUXADC_CON24 0x0772
498 +#define MT6323_AUXADC_CON25 0x0774
499 +#define MT6323_AUXADC_CON26 0x0776
500 +#define MT6323_AUXADC_CON27 0x0778
501 +#define MT6323_ACCDET_CON0 0x077A
502 +#define MT6323_ACCDET_CON1 0x077C
503 +#define MT6323_ACCDET_CON2 0x077E
504 +#define MT6323_ACCDET_CON3 0x0780
505 +#define MT6323_ACCDET_CON4 0x0782
506 +#define MT6323_ACCDET_CON5 0x0784
507 +#define MT6323_ACCDET_CON6 0x0786
508 +#define MT6323_ACCDET_CON7 0x0788
509 +#define MT6323_ACCDET_CON8 0x078A
510 +#define MT6323_ACCDET_CON9 0x078C
511 +#define MT6323_ACCDET_CON10 0x078E
512 +#define MT6323_ACCDET_CON11 0x0790
513 +#define MT6323_ACCDET_CON12 0x0792
514 +#define MT6323_ACCDET_CON13 0x0794
515 +#define MT6323_ACCDET_CON14 0x0796
516 +#define MT6323_ACCDET_CON15 0x0798
517 +#define MT6323_ACCDET_CON16 0x079A
518 +
519 +#endif /* __MFD_MT6323_REGISTERS_H__ */
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