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kernel: update kernel 4.4 to version 4.4.7
[openwrt/openwrt.git] / target / linux / mediatek / patches-4.4 / 0058-mtd-mediatek-driver-for-MTK-Smart-Device-Gen1-NAND.patch
1 From cc1959d5bc9a709729fcd02d78f4c27394393109 Mon Sep 17 00:00:00 2001
2 From: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
3 Date: Wed, 2 Mar 2016 12:00:12 -0500
4 Subject: [PATCH 58/81] mtd: mediatek: driver for MTK Smart Device Gen1 NAND
5
6 This patch adds support for mediatek's SDG1 NFC nand controller
7 embedded in SoC 2701.
8
9 UBIFS support has been successfully tested.
10
11 Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
12 ---
13 drivers/mtd/nand/Kconfig | 6 +
14 drivers/mtd/nand/Makefile | 1 +
15 drivers/mtd/nand/mtksdg1_nand.c | 1535 +++++++++++++++++++++++++++++++++++
16 drivers/mtd/nand/mtksdg1_nand_ecc.h | 75 ++
17 drivers/mtd/nand/mtksdg1_nand_nfi.h | 119 +++
18 5 files changed, 1736 insertions(+)
19 create mode 100644 drivers/mtd/nand/mtksdg1_nand.c
20 create mode 100644 drivers/mtd/nand/mtksdg1_nand_ecc.h
21 create mode 100644 drivers/mtd/nand/mtksdg1_nand_nfi.h
22
23 --- a/drivers/mtd/nand/Kconfig
24 +++ b/drivers/mtd/nand/Kconfig
25 @@ -546,4 +546,10 @@ config MTD_NAND_HISI504
26 help
27 Enables support for NAND controller on Hisilicon SoC Hip04.
28
29 +config MTD_NAND_MTKSDG1
30 + tristate "Support for NAND controller on MTK Smart Device SoCs"
31 + depends on HAS_DMA
32 + help
33 + Enables support for NAND controller on MTK Smart Device SoCs.
34 +
35 endif # MTD_NAND
36 --- a/drivers/mtd/nand/Makefile
37 +++ b/drivers/mtd/nand/Makefile
38 @@ -55,5 +55,6 @@ obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) +=
39 obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_nand.o
40 obj-$(CONFIG_MTD_NAND_HISI504) += hisi504_nand.o
41 obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/
42 +obj-$(CONFIG_MTD_NAND_MTKSDG1) += mtksdg1_nand.o
43
44 nand-objs := nand_base.o nand_bbt.o nand_timings.o
45 --- /dev/null
46 +++ b/drivers/mtd/nand/mtksdg1_nand.c
47 @@ -0,0 +1,1535 @@
48 +/*
49 + * MTK smart device NAND Flash controller driver.
50 + * Copyright (C) 2015-2016 MediaTek Inc.
51 + * Authors: Xiaolei Li <xiaolei.li@mediatek.com>
52 + * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
53 + *
54 + * This program is free software; you can redistribute it and/or modify
55 + * it under the terms of the GNU General Public License version 2 as
56 + * published by the Free Software Foundation.
57 + *
58 + * This program is distributed in the hope that it will be useful,
59 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
60 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
61 + * GNU General Public License for more details.
62 + */
63 +
64 +#include <linux/platform_device.h>
65 +#include <linux/dma-mapping.h>
66 +#include <linux/interrupt.h>
67 +#include <linux/of_mtd.h>
68 +#include <linux/delay.h>
69 +#include <linux/clk.h>
70 +#include <linux/mtd/partitions.h>
71 +#include <linux/mtd/nand.h>
72 +#include <linux/mtd/mtd.h>
73 +#include <linux/module.h>
74 +
75 +#include "mtksdg1_nand_nfi.h"
76 +#include "mtksdg1_nand_ecc.h"
77 +
78 +#define MTK_IRQ_ECC "mtksdg1-nand-ecc"
79 +#define MTK_IRQ_NFI "mtksdg1-nand-nfi"
80 +#define MTK_NAME "mtksdg1-nand"
81 +
82 +#define KB(x) ((x) * 1024UL)
83 +#define MB(x) (KB(x) * 1024UL)
84 +
85 +#define SECTOR_SHIFT (10)
86 +#define SECTOR_SIZE (1UL << SECTOR_SHIFT)
87 +#define BYTES_TO_SECTORS(x) ((x) >> SECTOR_SHIFT)
88 +#define SECTORS_TO_BYTES(x) ((x) << SECTOR_SHIFT)
89 +
90 +#define MTK_TIMEOUT (500)
91 +#define MTK_RESET_TIMEOUT (1 * HZ)
92 +
93 +#define MTK_ECC_PARITY_BITS (14)
94 +#define MTK_NAND_MAX_CHIP (2)
95 +
96 +#define MTK_OOB_ON (1)
97 +#define MTK_OOB_OFF (0)
98 +
99 +/* raw accesses do not use ECC (ecc = !raw) */
100 +#define MTK_ECC_OFF (1)
101 +#define MTK_ECC_ON (0)
102 +
103 +struct mtk_nfc_clk {
104 + struct clk *nfiecc_clk;
105 + struct clk *nfi_clk;
106 + struct clk *pad_clk;
107 +};
108 +
109 +struct mtk_nfc_saved_reg {
110 + struct {
111 + u32 enccnfg;
112 + u32 deccnfg;
113 + } ecc;
114 + struct {
115 + u32 emp_thresh;
116 + u16 pagefmt;
117 + u32 acccon;
118 + u16 cnrnb;
119 + u16 csel;
120 + } nfi;
121 +};
122 +
123 +struct mtk_nfc_host {
124 + struct mtk_nfc_clk clk;
125 + struct nand_chip chip;
126 + struct device *dev;
127 +
128 + struct {
129 + struct completion complete;
130 + void __iomem *base;
131 + } nfi;
132 +
133 + struct {
134 + struct completion complete;
135 + void __iomem *base;
136 + u32 dec_sec;
137 + } ecc;
138 +
139 + u32 fdm_reg[MTKSDG1_NFI_FDM_REG_SIZE / sizeof(u32)];
140 + bool switch_oob;
141 + u32 row_nob;
142 + u8 *buffer;
143 +
144 +#ifdef CONFIG_PM_SLEEP
145 + struct mtk_nfc_saved_reg saved_reg;
146 +#endif
147 +};
148 +
149 +static struct nand_ecclayout nand_2k_64 = {
150 + .oobfree = { {0, 16} },
151 +};
152 +
153 +static struct nand_ecclayout nand_4k_128 = {
154 + .oobfree = { {0, 32} },
155 +};
156 +
157 +/* NFI register access */
158 +static inline void mtk_nfi_writel(struct mtk_nfc_host *host, u32 val, u32 reg)
159 +{
160 + writel(val, host->nfi.base + reg);
161 +}
162 +static inline void mtk_nfi_writew(struct mtk_nfc_host *host, u16 val, u32 reg)
163 +{
164 + writew(val, host->nfi.base + reg);
165 +}
166 +static inline u32 mtk_nfi_readl(struct mtk_nfc_host *host, u32 reg)
167 +{
168 + return readl_relaxed(host->nfi.base + reg);
169 +}
170 +static inline u16 mtk_nfi_readw(struct mtk_nfc_host *host, u32 reg)
171 +{
172 + return readw_relaxed(host->nfi.base + reg);
173 +}
174 +static inline u8 mtk_nfi_readb(struct mtk_nfc_host *host, u32 reg)
175 +{
176 + return readb_relaxed(host->nfi.base + reg);
177 +}
178 +
179 +/* ECC register access */
180 +static inline void mtk_ecc_writel(struct mtk_nfc_host *host, u32 val, u32 reg)
181 +{
182 + writel(val, host->ecc.base + reg);
183 +}
184 +static inline void mtk_ecc_writew(struct mtk_nfc_host *host, u16 val, u32 reg)
185 +{
186 + writew(val, host->ecc.base + reg);
187 +}
188 +static inline u32 mtk_ecc_readl(struct mtk_nfc_host *host, u32 reg)
189 +{
190 + return readl_relaxed(host->ecc.base + reg);
191 +}
192 +static inline u16 mtk_ecc_readw(struct mtk_nfc_host *host, u32 reg)
193 +{
194 + return readw_relaxed(host->ecc.base + reg);
195 +}
196 +
197 +static void mtk_nfc_hw_reset(struct mtk_nfc_host *host)
198 +{
199 + unsigned long timeout = MTK_RESET_TIMEOUT;
200 + struct device *dev = host->dev;
201 + u32 val;
202 +
203 + /* reset the state machine, data fifo and fdm data */
204 + mtk_nfi_writel(host, CON_FIFO_FLUSH | CON_NFI_RST, MTKSDG1_NFI_CON);
205 + timeout += jiffies;
206 + do {
207 + val = mtk_nfi_readl(host, MTKSDG1_NFI_MASTER_STA);
208 + val &= MASTER_STA_MASK;
209 + if (!val)
210 + return;
211 + usleep_range(50, 100);
212 +
213 + } while (time_before(jiffies, timeout));
214 +
215 + dev_warn(dev, "nfi master active after in reset [0x%x] = 0x%x\n",
216 + MTKSDG1_NFI_MASTER_STA, val);
217 +};
218 +
219 +static int mtk_nfc_set_command(struct mtk_nfc_host *host, u8 command)
220 +{
221 + unsigned long timeout = msecs_to_jiffies(MTK_TIMEOUT);
222 + struct device *dev = host->dev;
223 + u32 val;
224 +
225 + mtk_nfi_writel(host, command, MTKSDG1_NFI_CMD);
226 +
227 + /* wait for the NFI core to enter command mode */
228 + timeout += jiffies;
229 + do {
230 + val = mtk_nfi_readl(host, MTKSDG1_NFI_STA);
231 + val &= STA_CMD;
232 + if (!val)
233 + return 0;
234 + cpu_relax();
235 +
236 + } while (time_before(jiffies, timeout));
237 + dev_warn(dev, "nfi core timed out entering command mode\n");
238 +
239 + return -EIO;
240 +}
241 +
242 +static int mtk_nfc_set_address(struct mtk_nfc_host *host, u32 column, u32 row,
243 + u8 colnob, u8 row_nob)
244 +{
245 + unsigned long timeout = msecs_to_jiffies(MTK_TIMEOUT);
246 + struct device *dev = host->dev;
247 + u32 addr_nob, val;
248 +
249 + addr_nob = colnob | (row_nob << ADDR_ROW_NOB_SHIFT);
250 + mtk_nfi_writel(host, column, MTKSDG1_NFI_COLADDR);
251 + mtk_nfi_writel(host, row, MTKSDG1_NFI_ROWADDR);
252 + mtk_nfi_writel(host, addr_nob, MTKSDG1_NFI_ADDRNOB);
253 +
254 + /* wait for the NFI core to enter address mode */
255 + timeout += jiffies;
256 + do {
257 + val = mtk_nfi_readl(host, MTKSDG1_NFI_STA);
258 + val &= STA_ADDR;
259 + if (!val)
260 + return 0;
261 + cpu_relax();
262 +
263 + } while (time_before(jiffies, timeout));
264 +
265 + dev_warn(dev, "nfi core timed out entering address mode\n");
266 +
267 + return -EIO;
268 +}
269 +
270 +static inline void mtk_ecc_encoder_idle(struct mtk_nfc_host *host)
271 +{
272 + unsigned long timeout = msecs_to_jiffies(MTK_TIMEOUT);
273 + struct device *dev = host->dev;
274 + u32 val;
275 +
276 + timeout += jiffies;
277 + do {
278 + val = mtk_ecc_readl(host, MTKSDG1_ECC_ENCIDLE);
279 + val &= ENC_IDLE;
280 + if (val)
281 + return;
282 + cpu_relax();
283 +
284 + } while (time_before(jiffies, timeout));
285 +
286 + dev_warn(dev, "hw init ecc encoder not idle\n");
287 +}
288 +
289 +static inline void mtk_ecc_decoder_idle(struct mtk_nfc_host *host)
290 +{
291 + unsigned long timeout = msecs_to_jiffies(MTK_TIMEOUT);
292 + struct device *dev = host->dev;
293 + u32 val;
294 +
295 + timeout += jiffies;
296 + do {
297 + val = mtk_ecc_readw(host, MTKSDG1_ECC_DECIDLE);
298 + val &= DEC_IDLE;
299 + if (val)
300 + return;
301 + cpu_relax();
302 +
303 + } while (time_before(jiffies, timeout));
304 +
305 + dev_warn(dev, "hw init ecc decoder not idle\n");
306 +}
307 +
308 +static int mtk_nfc_transfer_done(struct mtk_nfc_host *host, u32 sectors)
309 +{
310 + unsigned long timeout = msecs_to_jiffies(MTK_TIMEOUT);
311 + u32 cnt;
312 +
313 + /* wait for the sector count */
314 + timeout += jiffies;
315 + do {
316 + cnt = mtk_nfi_readl(host, MTKSDG1_NFI_ADDRCNTR);
317 + cnt &= CNTR_MASK;
318 + if (cnt >= sectors)
319 + return 0;
320 + cpu_relax();
321 +
322 + } while (time_before(jiffies, timeout));
323 +
324 + return -EIO;
325 +}
326 +
327 +static int mtk_nfc_subpage_done(struct mtk_nfc_host *host, int sectors)
328 +{
329 + unsigned long timeout = msecs_to_jiffies(MTK_TIMEOUT);
330 + u32 val;
331 +
332 + timeout += jiffies;
333 + do {
334 + val = mtk_nfi_readl(host, MTKSDG1_NFI_BYTELEN);
335 + val &= CNTR_MASK;
336 + if (val >= sectors)
337 + return 0;
338 + cpu_relax();
339 +
340 + } while (time_before(jiffies, timeout));
341 +
342 + return -EIO;
343 +}
344 +
345 +static inline int mtk_nfc_data_ready(struct mtk_nfc_host *host)
346 +{
347 + unsigned long timeout = msecs_to_jiffies(MTK_TIMEOUT);
348 + u8 val;
349 +
350 + timeout += jiffies;
351 + do {
352 + val = mtk_nfi_readw(host, MTKSDG1_NFI_PIO_DIRDY);
353 + val &= PIO_DI_RDY;
354 + if (val)
355 + return 0;
356 + cpu_relax();
357 +
358 + } while (time_before(jiffies, timeout));
359 +
360 + /* data _MUST_ not be accessed */
361 + return -EIO;
362 +}
363 +
364 +static int mtk_nfc_hw_runtime_config(struct mtd_info *mtd)
365 +{
366 + struct nand_chip *chip = mtd_to_nand(mtd);
367 + struct mtk_nfc_host *host = nand_get_controller_data(chip);
368 + struct device *dev = host->dev;
369 + u32 dec_size, enc_size;
370 + u32 ecc_bit, ecc_level;
371 + u32 spare, fmt;
372 + u32 reg;
373 +
374 + host->row_nob = 1;
375 + if (chip->chipsize > MB(32))
376 + host->row_nob = chip->chipsize > MB(128) ? 3 : 2;
377 +
378 + spare = mtd->oobsize / BYTES_TO_SECTORS(mtd->writesize);
379 + switch (spare) {
380 + case 16:
381 + ecc_bit = ECC_CNFG_4BIT;
382 + ecc_level = 4;
383 + break;
384 + case 32:
385 + ecc_bit = ECC_CNFG_12BIT;
386 + ecc_level = 12;
387 + break;
388 + default:
389 + dev_err(dev, "invalid spare size per sector: %d\n", spare);
390 + return -EINVAL;
391 + }
392 +
393 + chip->ecc.strength = ecc_level;
394 + chip->ecc.size = SECTOR_SIZE;
395 +
396 + switch (mtd->writesize) {
397 + case KB(2):
398 + fmt = PAGEFMT_512_2K;
399 + chip->ecc.layout = &nand_2k_64;
400 + break;
401 + case KB(4):
402 + fmt = PAGEFMT_2K_4K;
403 + chip->ecc.layout = &nand_4k_128;
404 + break;
405 + case KB(8):
406 + fmt = PAGEFMT_4K_8K;
407 + break;
408 + default:
409 + dev_err(dev, "invalid page size: %d\n", mtd->writesize);
410 + return -EINVAL;
411 + }
412 +
413 + /* configure PAGE FMT */
414 + reg = fmt;
415 + reg |= PAGEFMT_SPARE_16 << PAGEFMT_SPARE_SHIFT;
416 + reg |= MTKSDG1_NFI_FDM_REG_SIZE << PAGEFMT_FDM_SHIFT;
417 + reg |= MTKSDG1_NFI_FDM_REG_SIZE << PAGEFMT_FDM_ECC_SHIFT;
418 + mtk_nfi_writew(host, reg, MTKSDG1_NFI_PAGEFMT);
419 +
420 + /* configure ECC encoder (in bits) */
421 + enc_size = (SECTOR_SIZE + MTKSDG1_NFI_FDM_REG_SIZE) << 3;
422 + reg = ecc_bit | ECC_NFI_MODE | (enc_size << ECC_MS_SHIFT);
423 + mtk_ecc_writel(host, reg, MTKSDG1_ECC_ENCCNFG);
424 +
425 + /* configure ECC decoder (inbits) */
426 + dec_size = enc_size + ecc_level * MTK_ECC_PARITY_BITS;
427 + reg = ecc_bit | ECC_NFI_MODE | (dec_size << ECC_MS_SHIFT);
428 + reg |= (DEC_CNFG_CORRECT | DEC_EMPTY_EN);
429 + mtk_ecc_writel(host, reg, MTKSDG1_ECC_DECCNFG);
430 +
431 + return 0;
432 +}
433 +
434 +static void mtk_nfc_device_reset(struct mtk_nfc_host *host)
435 +{
436 + unsigned long timeout = msecs_to_jiffies(MTK_TIMEOUT);
437 + struct device *dev = host->dev;
438 + u16 chip;
439 + int rc;
440 +
441 + mtk_nfc_hw_reset(host);
442 +
443 + /* enable reset done interrupt */
444 + mtk_nfi_writew(host, INTR_RST_DONE_EN, MTKSDG1_NFI_INTR_EN);
445 +
446 + /* configure FSM for reset operation */
447 + mtk_nfi_writew(host, CNFG_OP_RESET, MTKSDG1_NFI_CNFG);
448 +
449 + init_completion(&host->nfi.complete);
450 +
451 + mtk_nfc_set_command(host, NAND_CMD_RESET);
452 + rc = wait_for_completion_timeout(&host->nfi.complete, timeout);
453 + if (!rc) {
454 + chip = mtk_nfi_readw(host, MTKSDG1_NFI_CSEL);
455 + dev_err(dev, "device(%d) reset timeout\n", chip);
456 + }
457 +}
458 +
459 +static void mtk_nfc_select_chip(struct mtd_info *mtd, int chip)
460 +{
461 + struct nand_chip *nand = mtd_to_nand(mtd);
462 + struct mtk_nfc_host *host = nand_get_controller_data(nand);
463 +
464 + if (chip < 0)
465 + return;
466 +
467 + mtk_nfi_writel(host, chip, MTKSDG1_NFI_CSEL);
468 +}
469 +
470 +static inline bool mtk_nfc_cmd_supported(unsigned command)
471 +{
472 + switch (command) {
473 + case NAND_CMD_RESET:
474 + case NAND_CMD_READID:
475 + case NAND_CMD_STATUS:
476 + case NAND_CMD_READOOB:
477 + case NAND_CMD_ERASE1:
478 + case NAND_CMD_ERASE2:
479 + case NAND_CMD_SEQIN:
480 + case NAND_CMD_PAGEPROG:
481 + case NAND_CMD_CACHEDPROG:
482 + case NAND_CMD_READ0:
483 + return true;
484 + default:
485 + return false;
486 + }
487 +}
488 +
489 +static void mtk_nfc_cmdfunc(struct mtd_info *mtd, unsigned command, int column,
490 + int page_addr)
491 +{
492 + struct mtk_nfc_host *host = nand_get_controller_data(mtd_to_nand(mtd));
493 + unsigned long const cmd_timeout = msecs_to_jiffies(MTK_TIMEOUT);
494 + struct completion *p = &host->nfi.complete;
495 + u32 val;
496 + int rc;
497 +
498 + if (mtk_nfc_cmd_supported(command))
499 + mtk_nfc_hw_reset(host);
500 +
501 + switch (command) {
502 + case NAND_CMD_RESET:
503 + mtk_nfc_device_reset(host);
504 + break;
505 + case NAND_CMD_READID:
506 + val = CNFG_READ_EN | CNFG_BYTE_RW | CNFG_OP_SRD;
507 + mtk_nfi_writew(host, val, MTKSDG1_NFI_CNFG);
508 + mtk_nfc_set_command(host, NAND_CMD_READID);
509 + mtk_nfc_set_address(host, column, 0, 1, 0);
510 + mtk_nfi_writel(host, CON_SRD, MTKSDG1_NFI_CON);
511 + break;
512 + case NAND_CMD_STATUS:
513 + val = CNFG_READ_EN | CNFG_BYTE_RW | CNFG_OP_SRD;
514 + mtk_nfi_writew(host, val, MTKSDG1_NFI_CNFG);
515 + mtk_nfc_set_command(host, NAND_CMD_STATUS);
516 + mtk_nfi_writel(host, CON_SRD, MTKSDG1_NFI_CON);
517 + break;
518 + case NAND_CMD_READOOB:
519 + val = CNFG_READ_EN | CNFG_BYTE_RW | CNFG_OP_READ;
520 + mtk_nfi_writew(host, val, MTKSDG1_NFI_CNFG);
521 + mtk_nfc_set_command(host, NAND_CMD_READ0);
522 + column += mtd->writesize;
523 + mtk_nfc_set_address(host, column, page_addr, 2, host->row_nob);
524 + val = CON_BRD | (1 << CON_SEC_SHIFT);
525 + mtk_nfi_writel(host, val, MTKSDG1_NFI_CON);
526 + break;
527 + case NAND_CMD_ERASE1:
528 + mtk_nfi_writew(host, INTR_ERS_DONE_EN, MTKSDG1_NFI_INTR_EN);
529 + mtk_nfi_writew(host, CNFG_OP_ERASE, MTKSDG1_NFI_CNFG);
530 + mtk_nfc_set_command(host, NAND_CMD_ERASE1);
531 + mtk_nfc_set_address(host, 0, page_addr, 0, host->row_nob);
532 + break;
533 + case NAND_CMD_ERASE2:
534 + init_completion(p);
535 + mtk_nfc_set_command(host, NAND_CMD_ERASE2);
536 + rc = wait_for_completion_timeout(p, cmd_timeout);
537 + if (!rc)
538 + dev_err(host->dev, "erase command timeout\n");
539 + break;
540 + case NAND_CMD_SEQIN:
541 + mtk_nfi_writew(host, CNFG_OP_PRGM, MTKSDG1_NFI_CNFG);
542 + mtk_nfc_set_command(host, NAND_CMD_SEQIN);
543 + mtk_nfc_set_address(host, column, page_addr, 2, host->row_nob);
544 + break;
545 + case NAND_CMD_PAGEPROG:
546 + case NAND_CMD_CACHEDPROG:
547 + mtk_nfi_writew(host, INTR_BUSY_RT_EN, MTKSDG1_NFI_INTR_EN);
548 + init_completion(p);
549 + mtk_nfc_set_command(host, command);
550 + rc = wait_for_completion_timeout(p, cmd_timeout);
551 + if (!rc)
552 + dev_err(host->dev, "pageprogr command timeout\n");
553 + break;
554 + case NAND_CMD_READ0:
555 + val = CNFG_OP_READ | CNFG_READ_EN;
556 + mtk_nfi_writew(host, val, MTKSDG1_NFI_CNFG);
557 + mtk_nfc_set_command(host, NAND_CMD_READ0);
558 + break;
559 + default:
560 + dev_warn(host->dev, "command 0x%x not supported\n", command);
561 + break;
562 + }
563 +}
564 +
565 +static uint8_t mtk_nfc_read_byte(struct mtd_info *mtd)
566 +{
567 + struct nand_chip *chip = mtd_to_nand(mtd);
568 + struct mtk_nfc_host *host = nand_get_controller_data(chip);
569 + int rc;
570 +
571 + rc = mtk_nfc_data_ready(host);
572 + if (rc < 0) {
573 + dev_err(host->dev, "data not ready\n");
574 + return NAND_STATUS_FAIL;
575 + }
576 +
577 + return mtk_nfi_readb(host, MTKSDG1_NFI_DATAR);
578 +}
579 +
580 +static void mtk_nfc_write_fdm(struct nand_chip *chip, u32 sectors)
581 +{
582 + struct mtk_nfc_host *host = nand_get_controller_data(chip);
583 + u8 *src, *dst;
584 + int i, j, reg;
585 +
586 + for (i = 0; i < sectors ; i++) {
587 + /* read FDM from OOB into private area */
588 + src = chip->oob_poi + i * MTKSDG1_NFI_FDM_REG_SIZE;
589 + dst = (u8 *)host->fdm_reg;
590 + memcpy(dst, src, MTKSDG1_NFI_FDM_REG_SIZE);
591 +
592 + /* write FDM to registers */
593 + for (j = 0; j < ARRAY_SIZE(host->fdm_reg); j++) {
594 + reg = MTKSDG1_NFI_FDM0L + i * MTKSDG1_NFI_FDM_REG_SIZE;
595 + reg += j * sizeof(host->fdm_reg[0]);
596 + mtk_nfi_writel(host, host->fdm_reg[j], reg);
597 + }
598 + }
599 +}
600 +
601 +static int mtk_nfc_write_page(struct mtd_info *mtd,
602 + struct nand_chip *chip, const uint8_t *buf,
603 + int oob_on, int page, int raw)
604 +{
605 +
606 + struct mtk_nfc_host *host = nand_get_controller_data(chip);
607 + struct completion *nfi = &host->nfi.complete;
608 + struct device *dev = host->dev;
609 + const bool use_ecc = !raw;
610 + void *q = (void *) buf;
611 + dma_addr_t dma_addr;
612 + size_t dmasize;
613 + u32 reg;
614 + int ret;
615 +
616 + dmasize = mtd->writesize + (raw ? mtd->oobsize : 0);
617 +
618 + dma_addr = dma_map_single(dev, q, dmasize, DMA_TO_DEVICE);
619 + if (dma_mapping_error(host->dev, dma_addr)) {
620 + dev_err(host->dev, "dma mapping error\n");
621 + return -EINVAL;
622 + }
623 +
624 + reg = mtk_nfi_readw(host, MTKSDG1_NFI_CNFG);
625 + reg |= CNFG_AHB | CNFG_DMA_BURST_EN;
626 + if (use_ecc) {
627 + /**
628 + * OOB will be generated
629 + * - FDM: from register
630 + * - ECC: from HW
631 + */
632 + reg |= CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN;
633 + mtk_nfi_writew(host, reg, MTKSDG1_NFI_CNFG);
634 +
635 + mtk_ecc_encoder_idle(host);
636 + mtk_ecc_writew(host, ENC_EN, MTKSDG1_ECC_ENCCON);
637 +
638 + /* write OOB into the FDM registers (OOB area in MTK NAND) */
639 + if (oob_on)
640 + mtk_nfc_write_fdm(chip, chip->ecc.steps);
641 + } else {
642 + /* OOB is part of the DMA transfer */
643 + mtk_nfi_writew(host, reg, MTKSDG1_NFI_CNFG);
644 + }
645 +
646 + mtk_nfi_writel(host, chip->ecc.steps << CON_SEC_SHIFT, MTKSDG1_NFI_CON);
647 + mtk_nfi_writel(host, lower_32_bits(dma_addr), MTKSDG1_NFI_STRADDR);
648 + mtk_nfi_writew(host, INTR_AHB_DONE_EN, MTKSDG1_NFI_INTR_EN);
649 +
650 + init_completion(nfi);
651 +
652 + /* start DMA */
653 + reg = mtk_nfi_readl(host, MTKSDG1_NFI_CON) | CON_BWR;
654 + mtk_nfi_writel(host, reg, MTKSDG1_NFI_CON);
655 +
656 + ret = wait_for_completion_timeout(nfi, msecs_to_jiffies(MTK_TIMEOUT));
657 + if (!ret) {
658 + dev_err(dev, "program ahb done timeout\n");
659 + mtk_nfi_writew(host, 0, MTKSDG1_NFI_INTR_EN);
660 + ret = -ETIMEDOUT;
661 + goto timeout;
662 + }
663 +
664 + ret = mtk_nfc_transfer_done(host, chip->ecc.steps);
665 + if (ret < 0)
666 + dev_err(dev, "hwecc write timeout\n");
667 +timeout:
668 + dma_unmap_single(host->dev, dma_addr, dmasize, DMA_TO_DEVICE);
669 +
670 + if (use_ecc) {
671 + mtk_ecc_encoder_idle(host);
672 + mtk_ecc_writew(host, ENC_DE, MTKSDG1_ECC_ENCCON);
673 + }
674 +
675 + mtk_nfi_writel(host, 0, MTKSDG1_NFI_CON);
676 +
677 + return ret;
678 +}
679 +
680 +static int mtk_nfc_write_page_hwecc(struct mtd_info *mtd,
681 + struct nand_chip *chip, const uint8_t *buf,
682 + int oob_on, int page)
683 +{
684 + return mtk_nfc_write_page(mtd, chip, buf, oob_on, page, MTK_ECC_ON);
685 +}
686 +
687 +static int mtk_nfc_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
688 + const uint8_t *buf, int oob_on, int pg)
689 +{
690 + struct mtk_nfc_host *host = nand_get_controller_data(chip);
691 + uint8_t *src, *dst;
692 + size_t len;
693 + u32 i;
694 +
695 + memset(host->buffer, 0xff, mtd->writesize + mtd->oobsize);
696 +
697 + /* MTK internal 4KB page data layout:
698 + * ----------------------------------
699 + * PAGE = 4KB, SECTOR = 1KB, OOB=128B
700 + * page = sector_oob1 + sector_oob2 + sector_oob3 + sector_oob4
701 + * sector_oob = data (1KB) + FDM (8B) + ECC parity (21B) + free (3B)
702 + *
703 + */
704 + len = SECTOR_SIZE + mtd->oobsize / chip->ecc.steps;
705 +
706 + for (i = 0; i < chip->ecc.steps; i++) {
707 +
708 + if (buf) {
709 + src = (uint8_t *) buf + i * SECTOR_SIZE;
710 + dst = host->buffer + i * len;
711 + memcpy(dst, src, SECTOR_SIZE);
712 + }
713 +
714 + if (oob_on) {
715 + src = chip->oob_poi + i * MTKSDG1_NFI_FDM_REG_SIZE;
716 + dst = host->buffer + i * len + SECTOR_SIZE;
717 + memcpy(dst, src, MTKSDG1_NFI_FDM_REG_SIZE);
718 + }
719 + }
720 +
721 + return mtk_nfc_write_page(mtd, chip, host->buffer, MTK_OOB_OFF, pg,
722 + MTK_ECC_OFF);
723 +}
724 +
725 +static int mtk_nfc_sector_encode(struct nand_chip *chip, u8 *data)
726 +{
727 + struct mtk_nfc_host *host = nand_get_controller_data(chip);
728 + struct completion *ecc = &host->ecc.complete;
729 + u32 reg, parity_bytes, i;
730 + dma_addr_t dma_addr;
731 + u32 *parity_region;
732 + int rc, ret = 0;
733 + size_t dmasize;
734 +
735 + dmasize = SECTOR_SIZE + MTKSDG1_NFI_FDM_REG_SIZE;
736 + dma_addr = dma_map_single(host->dev, data, dmasize, DMA_TO_DEVICE);
737 + if (dma_mapping_error(host->dev, dma_addr)) {
738 + dev_err(host->dev, "dma mapping error\n");
739 + return -EINVAL;
740 + }
741 +
742 + /* enable the encoder in DMA mode to calculate the ECC bytes */
743 + reg = mtk_ecc_readl(host, MTKSDG1_ECC_ENCCNFG);
744 + reg &= (~ECC_ENC_MODE_MASK);
745 + reg |= ECC_DMA_MODE;
746 + mtk_ecc_writel(host, reg, MTKSDG1_ECC_ENCCNFG);
747 +
748 + mtk_ecc_writel(host, ENC_IRQEN, MTKSDG1_ECC_ENCIRQ_EN);
749 + mtk_ecc_writel(host, lower_32_bits(dma_addr), MTKSDG1_ECC_ENCDIADDR);
750 +
751 + init_completion(ecc);
752 + mtk_ecc_writew(host, ENC_EN, MTKSDG1_ECC_ENCCON);
753 +
754 + rc = wait_for_completion_timeout(ecc, msecs_to_jiffies(MTK_TIMEOUT));
755 + if (!rc) {
756 + dev_err(host->dev, "ecc encode done timeout\n");
757 + mtk_ecc_writel(host, 0, MTKSDG1_ECC_ENCIRQ_EN);
758 + ret = -ETIMEDOUT;
759 + goto timeout;
760 + }
761 +
762 + mtk_ecc_encoder_idle(host);
763 +
764 + /**
765 + * Program ECC bytes to OOB
766 + * per sector oob = FDM + ECC + SPARE
767 + */
768 +
769 + parity_region = (u32 *) (data + SECTOR_SIZE + MTKSDG1_NFI_FDM_REG_SIZE);
770 + parity_bytes = (chip->ecc.strength * MTK_ECC_PARITY_BITS + 7) >> 3;
771 +
772 + /* write the parity bytes generated by the ECC back to the OOB region */
773 + for (i = 0; i < parity_bytes; i += sizeof(u32))
774 + *parity_region++ = mtk_ecc_readl(host, MTKSDG1_ECC_ENCPAR0 + i);
775 +
776 +timeout:
777 +
778 + dma_unmap_single(host->dev, dma_addr, dmasize, DMA_TO_DEVICE);
779 +
780 + mtk_ecc_writew(host, 0, MTKSDG1_ECC_ENCCON);
781 + reg = mtk_ecc_readl(host, MTKSDG1_ECC_ENCCNFG);
782 + reg &= (~ECC_ENC_MODE_MASK);
783 + reg |= ECC_NFI_MODE;
784 + mtk_ecc_writel(host, reg, MTKSDG1_ECC_ENCCNFG);
785 +
786 + return ret;
787 +}
788 +
789 +static int mtk_nfc_write_subpage_hwecc(struct mtd_info *mtd,
790 + struct nand_chip *chip, uint32_t offset, uint32_t data_len,
791 + const uint8_t *buf, int oob_on, int pg)
792 +{
793 + struct mtk_nfc_host *host = nand_get_controller_data(chip);
794 + uint8_t *src, *dst;
795 + u32 start, end;
796 + size_t len;
797 + int i, ret;
798 +
799 + start = BYTES_TO_SECTORS(offset);
800 + end = BYTES_TO_SECTORS(offset + data_len + SECTOR_SIZE - 1);
801 +
802 + len = SECTOR_SIZE + mtd->oobsize / chip->ecc.steps;
803 +
804 + memset(host->buffer, 0xff, mtd->writesize + mtd->oobsize);
805 + for (i = 0; i < chip->ecc.steps; i++) {
806 +
807 + /* write data */
808 + src = (uint8_t *) buf + i * SECTOR_SIZE;
809 + dst = host->buffer + i * len;
810 + memcpy(dst, src, SECTOR_SIZE);
811 +
812 + if (i < start)
813 + continue;
814 +
815 + if (i >= end)
816 + continue;
817 +
818 + /* write fdm */
819 + if (oob_on) {
820 + src = chip->oob_poi + i * MTKSDG1_NFI_FDM_REG_SIZE;
821 + dst = host->buffer + i * len + SECTOR_SIZE;
822 + memcpy(dst, src, MTKSDG1_NFI_FDM_REG_SIZE);
823 + }
824 +
825 + /* point to the start of data */
826 + src = host->buffer + i * len;
827 +
828 + /* program the CRC back to the OOB */
829 + ret = mtk_nfc_sector_encode(chip, src);
830 + if (ret < 0)
831 + return ret;
832 + }
833 +
834 + /* use the data in the private buffer (now with FDM and CRC) to perform
835 + * a raw write
836 + */
837 + src = host->buffer;
838 + return mtk_nfc_write_page(mtd, chip, src, MTK_OOB_OFF, pg, MTK_ECC_OFF);
839 +}
840 +
841 +static int mtk_nfc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
842 + int page)
843 +{
844 + u8 *buf = chip->buffers->databuf;
845 + int ret;
846 +
847 + memset(buf, 0xff, mtd->writesize);
848 + chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
849 + ret = mtk_nfc_write_page_hwecc(mtd, chip, buf, MTK_OOB_ON, page);
850 + if (ret < 0)
851 + return -EIO;
852 +
853 + chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
854 + ret = chip->waitfunc(mtd, chip);
855 +
856 + return ret & NAND_STATUS_FAIL ? -EIO : 0;
857 +}
858 +
859 +static int mtk_nfc_write_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
860 + int page)
861 +{
862 + int ret;
863 +
864 + chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
865 + ret = mtk_nfc_write_page_raw(mtd, chip, NULL, MTK_OOB_ON, page);
866 + if (ret < 0)
867 + return -EIO;
868 +
869 + chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
870 + ret = chip->waitfunc(mtd, chip);
871 +
872 + return ret & NAND_STATUS_FAIL ? -EIO : 0;
873 +}
874 +
875 +static int mtk_nfc_ecc_check(struct mtd_info *mtd, struct nand_chip *chip,
876 + u32 sectors)
877 +{
878 + struct mtk_nfc_host *host = nand_get_controller_data(chip);
879 + u32 offset, i, err, max_bitflip;
880 +
881 + max_bitflip = 0;
882 +
883 + for (i = 0; i < sectors; i++) {
884 + offset = (i >> 2) << 2;
885 + err = mtk_ecc_readl(host, MTKSDG1_ECC_DECENUM0 + offset);
886 + err = err >> ((i % 4) * 8);
887 + err &= ERR_MASK;
888 + if (err == ERR_MASK) {
889 + /* uncorrectable errors */
890 + mtd->ecc_stats.failed++;
891 + continue;
892 + }
893 +
894 + mtd->ecc_stats.corrected += err;
895 + max_bitflip = max_t(u32, max_bitflip, err);
896 + }
897 +
898 + return max_bitflip;
899 +}
900 +
901 +static void mtk_nfc_read_fdm(struct nand_chip *chip, u32 sectors)
902 +{
903 + struct mtk_nfc_host *host = nand_get_controller_data(chip);
904 + int i, j, reg;
905 + u8 *dst, *src;
906 +
907 + for (i = 0; i < sectors; i++) {
908 + /* read FDM register into host memory */
909 + for (j = 0; j < ARRAY_SIZE(host->fdm_reg); j++) {
910 + reg = MTKSDG1_NFI_FDM0L + i * MTKSDG1_NFI_FDM_REG_SIZE;
911 + reg += j * sizeof(host->fdm_reg[0]);
912 + host->fdm_reg[j] = mtk_nfi_readl(host, reg);
913 + }
914 +
915 + /* copy FDM register from host to OOB */
916 + src = (u8 *)host->fdm_reg;
917 + dst = chip->oob_poi + i * MTKSDG1_NFI_FDM_REG_SIZE;
918 + memcpy(dst, src, MTKSDG1_NFI_FDM_REG_SIZE);
919 + }
920 +}
921 +
922 +static int mtk_nfc_update_oob(struct mtd_info *mtd, struct nand_chip *chip,
923 + u8 *buf, u32 sectors)
924 +{
925 + struct mtk_nfc_host *host = nand_get_controller_data(chip);
926 + int i, bitflips = 0;
927 +
928 + /* if the page is empty, no bitflips and clear data and oob */
929 + if (mtk_nfi_readl(host, MTKSDG1_NFI_STA) & STA_EMP_PAGE) {
930 + memset(buf, 0xff, SECTORS_TO_BYTES(sectors));
931 +
932 + /* empty page: update OOB with 0xFF */
933 + for (i = 0; i < sectors; i++) {
934 + memset(chip->oob_poi + i * MTKSDG1_NFI_FDM_REG_SIZE,
935 + 0xff, MTKSDG1_NFI_FDM_REG_SIZE);
936 + }
937 + } else {
938 + /* update OOB with HW info */
939 + mtk_nfc_read_fdm(chip, sectors);
940 +
941 + /* return the bitflips */
942 + bitflips = mtk_nfc_ecc_check(mtd, chip, sectors);
943 + }
944 +
945 + return bitflips;
946 +}
947 +
948 +static int mtk_nfc_block_markbad(struct mtd_info *mtd, loff_t ofs)
949 +{
950 + struct nand_chip *chip = mtd_to_nand(mtd);
951 + u8 *buf = chip->buffers->databuf;
952 + int rc, i, pg;
953 +
954 + /* block_markbad writes 0x00 at data and OOB */
955 + memset(buf, 0x00, mtd->writesize + mtd->oobsize);
956 +
957 + /* Write to first/last page(s) if necessary */
958 + if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
959 + ofs += mtd->erasesize - mtd->writesize;
960 +
961 + i = 0;
962 + do {
963 + pg = (int)(ofs >> chip->page_shift);
964 +
965 + /**
966 + * write 0x00 to DATA & OOB in flash
967 + * No need to reorganize the page since it is all 0x00
968 + */
969 + chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, pg);
970 + rc = mtk_nfc_write_page(mtd, chip, buf, MTK_OOB_OFF, pg,
971 + MTK_ECC_OFF);
972 + if (rc < 0)
973 + return rc;
974 +
975 + chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
976 + rc = chip->waitfunc(mtd, chip);
977 + rc = rc & NAND_STATUS_FAIL ? -EIO : 0;
978 + if (rc < 0)
979 + return rc;
980 +
981 + ofs += mtd->writesize;
982 + i++;
983 +
984 + } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
985 +
986 + return 0;
987 +}
988 +
989 +static int mtk_nfc_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
990 + uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi,
991 + int page, int raw)
992 +{
993 + struct mtk_nfc_host *host = nand_get_controller_data(chip);
994 + unsigned long timeout = msecs_to_jiffies(MTK_TIMEOUT);
995 + u32 reg, column, spare, sectors, start, end;
996 + struct completion *nfi, *ecc;
997 + const bool use_ecc = !raw;
998 + int bitflips = -EIO;
999 + dma_addr_t dma_addr;
1000 + size_t len;
1001 + u8 *buf;
1002 + int rc;
1003 +
1004 + nfi = &host->nfi.complete;
1005 + ecc = &host->ecc.complete;
1006 +
1007 + start = BYTES_TO_SECTORS(data_offs);
1008 + end = BYTES_TO_SECTORS(data_offs + readlen + SECTOR_SIZE - 1);
1009 + sectors = end - start;
1010 +
1011 + spare = mtd->oobsize / chip->ecc.steps;
1012 + column = start * (SECTOR_SIZE + spare);
1013 +
1014 + len = SECTORS_TO_BYTES(sectors) + (raw ? sectors * spare : 0);
1015 + buf = bufpoi + SECTORS_TO_BYTES(start);
1016 +
1017 + /* map the device memory */
1018 + dma_addr = dma_map_single(host->dev, buf, len, DMA_FROM_DEVICE);
1019 + if (dma_mapping_error(host->dev, dma_addr)) {
1020 + dev_err(host->dev, "dma mapping error\n");
1021 + return -EINVAL;
1022 + }
1023 +
1024 + /* configure the transfer */
1025 + reg = mtk_nfi_readw(host, MTKSDG1_NFI_CNFG);
1026 + reg |= CNFG_DMA_BURST_EN | CNFG_AHB;
1027 + if (use_ecc) {
1028 + reg |= CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN;
1029 + mtk_nfi_writew(host, reg, MTKSDG1_NFI_CNFG);
1030 +
1031 + /* enable encoder */
1032 + mtk_ecc_decoder_idle(host);
1033 + mtk_ecc_writel(host, DEC_EN, MTKSDG1_ECC_DECCON);
1034 + } else
1035 + mtk_nfi_writew(host, reg, MTKSDG1_NFI_CNFG);
1036 +
1037 + mtk_nfi_writel(host, sectors << CON_SEC_SHIFT, MTKSDG1_NFI_CON);
1038 + mtk_nfi_writew(host, INTR_BUSY_RT_EN, MTKSDG1_NFI_INTR_EN);
1039 +
1040 + init_completion(nfi);
1041 +
1042 + mtk_nfc_set_address(host, column, page, 2, host->row_nob);
1043 + mtk_nfc_set_command(host, NAND_CMD_READSTART);
1044 + rc = wait_for_completion_timeout(nfi, timeout);
1045 + if (!rc) {
1046 + dev_err(host->dev, "read busy return timeout\n");
1047 + goto error;
1048 + }
1049 +
1050 + mtk_nfi_writew(host, INTR_AHB_DONE_EN, MTKSDG1_NFI_INTR_EN);
1051 + mtk_nfi_writel(host, lower_32_bits(dma_addr), MTKSDG1_NFI_STRADDR);
1052 +
1053 + if (use_ecc) {
1054 + /* program ECC with sector count */
1055 + host->ecc.dec_sec = sectors;
1056 + init_completion(ecc);
1057 + mtk_ecc_writew(host, DEC_IRQEN, MTKSDG1_ECC_DECIRQ_EN);
1058 + }
1059 +
1060 + init_completion(nfi);
1061 +
1062 + /* start DMA */
1063 + reg = mtk_nfi_readl(host, MTKSDG1_NFI_CON) | CON_BRD;
1064 + mtk_nfi_writel(host, reg, MTKSDG1_NFI_CON);
1065 +
1066 + rc = wait_for_completion_timeout(nfi, timeout);
1067 + if (!rc)
1068 + dev_warn(host->dev, "read ahb/dma done timeout\n");
1069 +
1070 + /* DMA interrupt didn't trigger, check page done just in case */
1071 + rc = mtk_nfc_subpage_done(host, sectors);
1072 + if (rc < 0) {
1073 + dev_err(host->dev, "subpage done timeout\n");
1074 + goto error;
1075 + }
1076 +
1077 + /* raw transfer successful */
1078 + bitflips = 0;
1079 +
1080 + if (use_ecc) {
1081 + rc = wait_for_completion_timeout(ecc, timeout);
1082 + if (!rc) {
1083 + dev_err(host->dev, "ecc decode timeout\n");
1084 + host->ecc.dec_sec = 0;
1085 + bitflips = -ETIMEDOUT;
1086 + goto error;
1087 + }
1088 + bitflips = mtk_nfc_update_oob(mtd, chip, buf, sectors);
1089 + }
1090 +
1091 +error:
1092 + dma_unmap_single(host->dev, dma_addr, len, DMA_FROM_DEVICE);
1093 +
1094 + if (use_ecc) {
1095 + /* make sure the ECC dec irq is disabled */
1096 + mtk_ecc_writew(host, 0, MTKSDG1_ECC_DECIRQ_EN);
1097 + mtk_ecc_decoder_idle(host);
1098 +
1099 + /* disable ECC dec */
1100 + mtk_ecc_writew(host, 0, MTKSDG1_ECC_DECCON);
1101 + }
1102 +
1103 + mtk_nfi_writel(host, 0, MTKSDG1_NFI_CON);
1104 +
1105 + return bitflips;
1106 +}
1107 +
1108 +static int mtk_nfc_read_subpage_hwecc(struct mtd_info *mtd,
1109 + struct nand_chip *chip, uint32_t data_offs,
1110 + uint32_t readlen, uint8_t *bufpoi, int page)
1111 +{
1112 + return mtk_nfc_read_subpage(mtd, chip, data_offs, readlen,
1113 + bufpoi, page, MTK_ECC_ON);
1114 +}
1115 +
1116 +static int mtk_nfc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1117 + uint8_t *buf, int oob_on, int page)
1118 +{
1119 + return mtk_nfc_read_subpage_hwecc(mtd, chip, 0, mtd->writesize,
1120 + buf, page);
1121 +}
1122 +
1123 +static int mtk_nfc_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1124 + uint8_t *buf, int oob_on, int page)
1125 +{
1126 + struct mtk_nfc_host *host = nand_get_controller_data(chip);
1127 + uint8_t *src, *dst;
1128 + int i, ret;
1129 + size_t len;
1130 +
1131 + dst = host->buffer;
1132 + memset(dst, 0xff, mtd->writesize + mtd->oobsize);
1133 + ret = mtk_nfc_read_subpage(mtd, chip, 0, mtd->writesize, dst, page, 1);
1134 + if (ret < 0)
1135 + return ret;
1136 +
1137 + len = SECTOR_SIZE + mtd->oobsize / chip->ecc.steps;
1138 +
1139 + /* copy to the output buffer */
1140 + for (i = 0; i < chip->ecc.steps; i++) {
1141 +
1142 + /* copy sector data */
1143 + if (buf) {
1144 + src = host->buffer + i * len;
1145 + dst = buf + i * SECTOR_SIZE;
1146 + memcpy(dst, src, SECTOR_SIZE);
1147 + }
1148 +
1149 + /* copy FDM data to OOB */
1150 + if (oob_on) {
1151 + src = host->buffer + i * len + SECTOR_SIZE;
1152 + dst = chip->oob_poi + i * MTKSDG1_NFI_FDM_REG_SIZE;
1153 + memcpy(dst, src, MTKSDG1_NFI_FDM_REG_SIZE);
1154 + }
1155 + }
1156 +
1157 + return ret;
1158 +}
1159 +
1160 +static void mtk_nfc_switch_oob(struct mtd_info *mtd, struct nand_chip *chip,
1161 + uint8_t *buf)
1162 +{
1163 + struct mtk_nfc_host *host = nand_get_controller_data(chip);
1164 + size_t spare;
1165 + u32 sectors;
1166 + u8 *bufpoi;
1167 + int len;
1168 +
1169 + spare = mtd->oobsize / chip->ecc.steps;
1170 + sectors = mtd->writesize / (SECTOR_SIZE + spare);
1171 +
1172 + /**
1173 + * MTK: DATA+oob1, DATA+oob2, DATA+oob3 ...
1174 + * LNX: DATA+OOB
1175 + */
1176 + /* point to the last oob_i from the NAND device*/
1177 + bufpoi = buf + mtd->writesize - (sectors * spare);
1178 + len = sizeof(host->fdm_reg);
1179 +
1180 + /* copy NAND oob to private area */
1181 + memcpy(host->fdm_reg, bufpoi, len);
1182 +
1183 + /* copy oob_poi to NAND */
1184 + memcpy(bufpoi, chip->oob_poi, len);
1185 +
1186 + /* copy NAND oob to oob_poi */
1187 + memcpy(chip->oob_poi, host->fdm_reg, sizeof(host->fdm_reg));
1188 + memset(host->fdm_reg, 0x00, len);
1189 +}
1190 +
1191 +static int mtk_nfc_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
1192 + int page)
1193 +{
1194 + struct mtk_nfc_host *host = nand_get_controller_data(chip);
1195 + u8 *buf = chip->buffers->databuf;
1196 + struct mtd_ecc_stats stats;
1197 + int ret;
1198 +
1199 + stats = mtd->ecc_stats;
1200 +
1201 + memset(buf, 0xff, mtd->writesize);
1202 + chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1203 +
1204 + ret = mtk_nfc_read_page_hwecc(mtd, chip, buf, 1, page);
1205 +
1206 + if (host->switch_oob)
1207 + mtk_nfc_switch_oob(mtd, chip, buf);
1208 +
1209 + if (ret < mtd->bitflip_threshold)
1210 + mtd->ecc_stats.corrected = stats.corrected;
1211 +
1212 + return ret;
1213 +}
1214 +
1215 +static int mtk_nfc_read_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
1216 + int page)
1217 +{
1218 + chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1219 +
1220 + return mtk_nfc_read_page_raw(mtd, chip, NULL, MTK_OOB_ON, page);
1221 +}
1222 +
1223 +static inline void mtk_nfc_hw_init(struct mtk_nfc_host *host)
1224 +{
1225 + mtk_nfi_writel(host, 0x10804211, MTKSDG1_NFI_ACCCON);
1226 + mtk_nfi_writew(host, 0xf1, MTKSDG1_NFI_CNRNB);
1227 + mtk_nfc_hw_reset(host);
1228 +
1229 + /* clear interrupt */
1230 + mtk_nfi_readl(host, MTKSDG1_NFI_INTR_STA);
1231 + mtk_nfi_writel(host, 0, MTKSDG1_NFI_INTR_EN);
1232 +
1233 + /* ECC encoder init */
1234 + mtk_ecc_encoder_idle(host);
1235 + mtk_ecc_writew(host, ENC_DE, MTKSDG1_ECC_ENCCON);
1236 +
1237 + /* ECC decoder init */
1238 + mtk_ecc_decoder_idle(host);
1239 + mtk_ecc_writel(host, DEC_DE, MTKSDG1_ECC_DECCON);
1240 +}
1241 +
1242 +static irqreturn_t mtk_nfi_irq(int irq, void *devid)
1243 +{
1244 + struct mtk_nfc_host *host = devid;
1245 + u16 sta, ien;
1246 +
1247 + sta = mtk_nfi_readw(host, MTKSDG1_NFI_INTR_STA);
1248 + ien = mtk_nfi_readw(host, MTKSDG1_NFI_INTR_EN);
1249 +
1250 + if (!(sta & ien))
1251 + return IRQ_NONE;
1252 +
1253 + mtk_nfi_writew(host, ~sta & ien, MTKSDG1_NFI_INTR_EN);
1254 + complete(&host->nfi.complete);
1255 +
1256 + return IRQ_HANDLED;
1257 +}
1258 +
1259 +static irqreturn_t mtk_ecc_irq(int irq, void *devid)
1260 +{
1261 + struct mtk_nfc_host *host = devid;
1262 + u32 reg_val, mask;
1263 +
1264 + reg_val = mtk_ecc_readw(host, MTKSDG1_ECC_DECIRQ_STA);
1265 + if (reg_val & DEC_IRQEN) {
1266 + if (host->ecc.dec_sec) {
1267 + mask = 1 << (host->ecc.dec_sec - 1);
1268 + reg_val = mtk_ecc_readw(host, MTKSDG1_ECC_DECDONE);
1269 + if (mask & reg_val) {
1270 + host->ecc.dec_sec = 0;
1271 + complete(&host->ecc.complete);
1272 + mtk_ecc_writew(host, 0, MTKSDG1_ECC_DECIRQ_EN);
1273 + }
1274 + } else
1275 + dev_warn(host->dev, "spurious DEC_IRQ\n");
1276 +
1277 + return IRQ_HANDLED;
1278 + }
1279 +
1280 + reg_val = mtk_ecc_readl(host, MTKSDG1_ECC_ENCIRQ_STA);
1281 + if (reg_val & ENC_IRQEN) {
1282 + complete(&host->ecc.complete);
1283 + mtk_ecc_writel(host, 0, MTKSDG1_ECC_ENCIRQ_EN);
1284 +
1285 + return IRQ_HANDLED;
1286 + }
1287 +
1288 + return IRQ_NONE;
1289 +}
1290 +
1291 +static int mtk_nfc_enable_clk(struct device *dev, struct mtk_nfc_clk *clk)
1292 +{
1293 + int ret;
1294 +
1295 + ret = clk_prepare_enable(clk->nfi_clk);
1296 + if (ret) {
1297 + dev_err(dev, "failed to enable nfi clk\n");
1298 + return ret;
1299 + }
1300 +
1301 + ret = clk_prepare_enable(clk->nfiecc_clk);
1302 + if (ret) {
1303 + dev_err(dev, "failed to enable nfiecc clk\n");
1304 + goto out_nfiecc_clk_disable;
1305 + }
1306 +
1307 + ret = clk_prepare_enable(clk->pad_clk);
1308 + if (ret) {
1309 + dev_err(dev, "failed to enable pad clk\n");
1310 + goto out_pad_clk_disable;
1311 + }
1312 +
1313 + return 0;
1314 +
1315 +out_pad_clk_disable:
1316 + clk_disable_unprepare(clk->nfiecc_clk);
1317 +
1318 +out_nfiecc_clk_disable:
1319 + clk_disable_unprepare(clk->nfi_clk);
1320 +
1321 + return ret;
1322 +}
1323 +
1324 +static void mtk_nfc_disable_clk(struct mtk_nfc_clk *clk)
1325 +{
1326 + clk_disable_unprepare(clk->nfi_clk);
1327 + clk_disable_unprepare(clk->nfiecc_clk);
1328 + clk_disable_unprepare(clk->pad_clk);
1329 +}
1330 +
1331 +static int mtk_nfc_probe(struct platform_device *pdev)
1332 +{
1333 + struct device *dev = &pdev->dev;
1334 + struct device_node *np = dev->of_node;
1335 + struct mtk_nfc_host *host;
1336 + struct nand_chip *chip;
1337 + struct mtd_info *mtd;
1338 + struct resource *res;
1339 + int ret, irq;
1340 + size_t len;
1341 +
1342 + host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
1343 + if (!host)
1344 + return -ENOMEM;
1345 +
1346 + chip = &host->chip;
1347 + mtd = nand_to_mtd(chip);
1348 + host->dev = dev;
1349 +
1350 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1351 + host->nfi.base = devm_ioremap_resource(dev, res);
1352 + if (IS_ERR(host->nfi.base)) {
1353 + ret = PTR_ERR(host->nfi.base);
1354 + dev_err(dev, "no nfi base\n");
1355 + return ret;
1356 + }
1357 +
1358 + res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1359 + host->ecc.base = devm_ioremap_resource(dev, res);
1360 + if (IS_ERR(host->ecc.base)) {
1361 + ret = PTR_ERR(host->ecc.base);
1362 + dev_err(dev, "no ecc base\n");
1363 + return ret;
1364 + }
1365 +
1366 + host->clk.nfi_clk = devm_clk_get(dev, "nfi_clk");
1367 + if (IS_ERR(host->clk.nfi_clk)) {
1368 + dev_err(dev, "no clk\n");
1369 + ret = PTR_ERR(host->clk.nfi_clk);
1370 + return ret;
1371 + }
1372 +
1373 + host->clk.nfiecc_clk = devm_clk_get(dev, "nfiecc_clk");
1374 + if (IS_ERR(host->clk.nfiecc_clk)) {
1375 + dev_err(dev, "no ecc clk\n");
1376 + ret = PTR_ERR(host->clk.nfiecc_clk);
1377 + return ret;
1378 + }
1379 +
1380 + host->clk.pad_clk = devm_clk_get(dev, "pad_clk");
1381 + if (IS_ERR(host->clk.pad_clk)) {
1382 + dev_err(dev, "no pad clk\n");
1383 + ret = PTR_ERR(host->clk.pad_clk);
1384 + return ret;
1385 + }
1386 +
1387 + ret = mtk_nfc_enable_clk(dev, &host->clk);
1388 + if (ret)
1389 + return ret;
1390 +
1391 + irq = platform_get_irq(pdev, 0);
1392 + if (irq < 0) {
1393 + dev_err(dev, "no nfi irq resource\n");
1394 + ret = -EINVAL;
1395 + goto clk_disable;
1396 + }
1397 +
1398 + ret = devm_request_irq(dev, irq, mtk_nfi_irq, 0x0, MTK_IRQ_NFI, host);
1399 + if (ret) {
1400 + dev_err(dev, "failed to request nfi irq\n");
1401 + goto clk_disable;
1402 + }
1403 +
1404 + irq = platform_get_irq(pdev, 1);
1405 + if (irq < 0) {
1406 + dev_err(dev, "no ecc irq resource\n");
1407 + ret = -EINVAL;
1408 + goto clk_disable;
1409 + }
1410 +
1411 + ret = devm_request_irq(dev, irq, mtk_ecc_irq, 0x0, MTK_IRQ_ECC, host);
1412 + if (ret) {
1413 + dev_err(dev, "failed to request ecc irq\n");
1414 + goto clk_disable;
1415 + }
1416 +
1417 + ret = dma_set_mask(dev, DMA_BIT_MASK(32));
1418 + if (ret) {
1419 + dev_err(dev, "failed to set dma mask\n");
1420 + goto clk_disable;
1421 + }
1422 +
1423 + platform_set_drvdata(pdev, host);
1424 +
1425 + mtd_set_of_node(mtd, np);
1426 + mtd->owner = THIS_MODULE;
1427 + mtd->dev.parent = dev;
1428 + mtd->name = MTK_NAME;
1429 +
1430 + nand_set_controller_data(chip, host);
1431 + chip->options |= NAND_USE_BOUNCE_BUFFER | NAND_SUBPAGE_READ;
1432 + chip->block_markbad = mtk_nfc_block_markbad;
1433 + chip->select_chip = mtk_nfc_select_chip;
1434 + chip->read_byte = mtk_nfc_read_byte;
1435 + chip->cmdfunc = mtk_nfc_cmdfunc;
1436 + chip->ecc.mode = NAND_ECC_HW;
1437 + chip->ecc.write_subpage = mtk_nfc_write_subpage_hwecc;
1438 + chip->ecc.write_page_raw = mtk_nfc_write_page_raw;
1439 + chip->ecc.write_page = mtk_nfc_write_page_hwecc;
1440 + chip->ecc.write_oob_raw = mtk_nfc_write_oob_raw;
1441 + chip->ecc.write_oob = mtk_nfc_write_oob;
1442 + chip->ecc.read_subpage = mtk_nfc_read_subpage_hwecc;
1443 + chip->ecc.read_page_raw = mtk_nfc_read_page_raw;
1444 + chip->ecc.read_oob_raw = mtk_nfc_read_oob_raw;
1445 + chip->ecc.read_page = mtk_nfc_read_page_hwecc;
1446 + chip->ecc.read_oob = mtk_nfc_read_oob;
1447 +
1448 + mtk_nfc_hw_init(host);
1449 +
1450 + ret = nand_scan_ident(mtd, MTK_NAND_MAX_CHIP, NULL);
1451 + if (ret) {
1452 + ret = -ENODEV;
1453 + goto clk_disable;
1454 + }
1455 +
1456 + ret = mtk_nfc_hw_runtime_config(mtd);
1457 + if (ret < 0) {
1458 + dev_err(dev, "nand device not supported\n");
1459 + goto clk_disable;
1460 + }
1461 +
1462 + len = mtd->writesize + mtd->oobsize;
1463 + host->buffer = devm_kzalloc(dev, len, GFP_KERNEL);
1464 + if (!host->buffer) {
1465 + ret = -ENOMEM;
1466 + goto clk_disable;
1467 + }
1468 +
1469 + /* required to create bbt table if not present */
1470 + host->switch_oob = true;
1471 + ret = nand_scan_tail(mtd);
1472 + if (ret) {
1473 + ret = -ENODEV;
1474 + goto clk_disable;
1475 + }
1476 + host->switch_oob = false;
1477 +
1478 + ret = mtd_device_parse_register(mtd, NULL, NULL, NULL, 0);
1479 + if (ret) {
1480 + dev_err(dev, "mtd parse partition error\n");
1481 + goto nand_free;
1482 + }
1483 +
1484 + return 0;
1485 +
1486 +nand_free:
1487 + nand_release(mtd);
1488 +
1489 +clk_disable:
1490 + mtk_nfc_disable_clk(&host->clk);
1491 +
1492 + return ret;
1493 +}
1494 +
1495 +static int mtk_nfc_remove(struct platform_device *pdev)
1496 +{
1497 + struct mtk_nfc_host *host = platform_get_drvdata(pdev);
1498 + struct mtd_info *mtd = nand_to_mtd(&host->chip);
1499 +
1500 + nand_release(mtd);
1501 + mtk_nfc_disable_clk(&host->clk);
1502 +
1503 + return 0;
1504 +}
1505 +
1506 +#ifdef CONFIG_PM_SLEEP
1507 +static int mtk_nfc_suspend(struct device *dev)
1508 +{
1509 + struct mtk_nfc_host *host = dev_get_drvdata(dev);
1510 + struct mtk_nfc_saved_reg *reg = &host->saved_reg;
1511 +
1512 + reg->nfi.emp_thresh = mtk_nfi_readl(host, MTKSDG1_NFI_EMPTY_THRESH);
1513 + reg->ecc.enccnfg = mtk_ecc_readl(host, MTKSDG1_ECC_ENCCNFG);
1514 + reg->ecc.deccnfg = mtk_ecc_readl(host, MTKSDG1_ECC_DECCNFG);
1515 + reg->nfi.pagefmt = mtk_nfi_readw(host, MTKSDG1_NFI_PAGEFMT);
1516 + reg->nfi.acccon = mtk_nfi_readl(host, MTKSDG1_NFI_ACCCON);
1517 + reg->nfi.cnrnb = mtk_nfi_readw(host, MTKSDG1_NFI_CNRNB);
1518 + reg->nfi.csel = mtk_nfi_readw(host, MTKSDG1_NFI_CSEL);
1519 +
1520 + mtk_nfc_disable_clk(&host->clk);
1521 +
1522 + return 0;
1523 +}
1524 +
1525 +static int mtk_nfc_resume(struct device *dev)
1526 +{
1527 + struct mtk_nfc_host *host = dev_get_drvdata(dev);
1528 + struct mtk_nfc_saved_reg *reg = &host->saved_reg;
1529 + struct nand_chip *chip = &host->chip;
1530 + struct mtd_info *mtd = nand_to_mtd(chip);
1531 + int ret;
1532 + u32 i;
1533 +
1534 + udelay(200);
1535 +
1536 + ret = mtk_nfc_enable_clk(dev, &host->clk);
1537 + if (ret)
1538 + return ret;
1539 +
1540 + for (i = 0; i < chip->numchips; i++) {
1541 + chip->select_chip(mtd, i);
1542 + chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1543 + }
1544 +
1545 + mtk_nfi_writel(host, reg->nfi.emp_thresh, MTKSDG1_NFI_EMPTY_THRESH);
1546 + mtk_nfi_writew(host, reg->nfi.pagefmt, MTKSDG1_NFI_PAGEFMT);
1547 + mtk_ecc_writel(host, reg->ecc.enccnfg, MTKSDG1_ECC_ENCCNFG);
1548 + mtk_ecc_writel(host, reg->ecc.deccnfg, MTKSDG1_ECC_DECCNFG);
1549 + mtk_nfi_writel(host, reg->nfi.acccon, MTKSDG1_NFI_ACCCON);
1550 + mtk_nfi_writew(host, reg->nfi.cnrnb, MTKSDG1_NFI_CNRNB);
1551 + mtk_nfi_writew(host, reg->nfi.csel, MTKSDG1_NFI_CSEL);
1552 +
1553 + return 0;
1554 +}
1555 +
1556 +static SIMPLE_DEV_PM_OPS(mtk_nfc_pm_ops, mtk_nfc_suspend, mtk_nfc_resume);
1557 +#endif
1558 +
1559 +static const struct of_device_id mtk_nfc_id_table[] = {
1560 + { .compatible = "mediatek,mt2701-nfc" },
1561 + {}
1562 +};
1563 +MODULE_DEVICE_TABLE(of, mtk_nfc_id_table);
1564 +
1565 +static struct platform_driver mtk_nfc_driver = {
1566 + .probe = mtk_nfc_probe,
1567 + .remove = mtk_nfc_remove,
1568 + .driver = {
1569 + .name = MTK_NAME,
1570 + .of_match_table = mtk_nfc_id_table,
1571 +#ifdef CONFIG_PM_SLEEP
1572 + .pm = &mtk_nfc_pm_ops,
1573 +#endif
1574 + },
1575 +};
1576 +
1577 +module_platform_driver(mtk_nfc_driver);
1578 +
1579 +MODULE_LICENSE("GPL");
1580 +MODULE_AUTHOR("Xiaolei Li <xiaolei.li@mediatek.com>");
1581 +MODULE_DESCRIPTION("MTK Nand Flash Controller Driver");
1582 +
1583 --- /dev/null
1584 +++ b/drivers/mtd/nand/mtksdg1_nand_ecc.h
1585 @@ -0,0 +1,75 @@
1586 +/*
1587 + * MTK smart device ECC engine register.
1588 + * Copyright (C) 2015-2016 MediaTek Inc.
1589 + * Author: Xiaolei.Li <xiaolei.li@mediatek.com>
1590 + *
1591 + * This program is free software; you can redistribute it and/or modify
1592 + * it under the terms of the GNU General Public License version 2 as
1593 + * published by the Free Software Foundation.
1594 + *
1595 + * This program is distributed in the hope that it will be useful,
1596 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1597 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1598 + * GNU General Public License for more details.
1599 + */
1600 +
1601 +#ifndef MTKSDG1_NAND_ECC_H
1602 +#define MTKSDG1_NAND_ECC_H
1603 +
1604 +/* ECC engine register definition */
1605 +#define MTKSDG1_ECC_ENCCON (0x00)
1606 +#define ENC_EN (1)
1607 +#define ENC_DE (0)
1608 +
1609 +#define MTKSDG1_ECC_ENCCNFG (0x04)
1610 +#define ECC_CNFG_4BIT (0)
1611 +#define ECC_CNFG_12BIT (4)
1612 +#define ECC_NFI_MODE BIT(5)
1613 +#define ECC_DMA_MODE (0)
1614 +#define ECC_ENC_MODE_MASK (0x3 << 5)
1615 +#define ECC_MS_SHIFT (16)
1616 +
1617 +#define MTKSDG1_ECC_ENCDIADDR (0x08)
1618 +
1619 +#define MTKSDG1_ECC_ENCIDLE (0x0C)
1620 +#define ENC_IDLE BIT(0)
1621 +
1622 +#define MTKSDG1_ECC_ENCPAR0 (0x10)
1623 +#define MTKSDG1_ECC_ENCSTA (0x7C)
1624 +
1625 +#define MTKSDG1_ECC_ENCIRQ_EN (0x80)
1626 +#define ENC_IRQEN BIT(0)
1627 +
1628 +#define MTKSDG1_ECC_ENCIRQ_STA (0x84)
1629 +
1630 +#define MTKSDG1_ECC_DECCON (0x100)
1631 +#define DEC_EN (1)
1632 +#define DEC_DE (0)
1633 +
1634 +#define MTKSDG1_ECC_DECCNFG (0x104)
1635 +#define DEC_EMPTY_EN BIT(31)
1636 +#define DEC_CNFG_FER (0x1 << 12)
1637 +#define DEC_CNFG_EL (0x2 << 12)
1638 +#define DEC_CNFG_CORRECT (0x3 << 12)
1639 +
1640 +#define MTKSDG1_ECC_DECIDLE (0x10C)
1641 +#define DEC_IDLE BIT(0)
1642 +
1643 +#define MTKSDG1_ECC_DECFER (0x110)
1644 +
1645 +#define MTKSDG1_ECC_DECENUM0 (0x114)
1646 +#define ERR_MASK (0x3f)
1647 +
1648 +#define MTKSDG1_ECC_DECDONE (0x124)
1649 +
1650 +#define MTKSDG1_ECC_DECEL0 (0x128)
1651 +
1652 +#define MTKSDG1_ECC_DECIRQ_EN (0x200)
1653 +#define DEC_IRQEN BIT(0)
1654 +
1655 +#define MTKSDG1_ECC_DECIRQ_STA (0x204)
1656 +
1657 +#define MTKSDG1_ECC_DECFSM (0x208)
1658 +#define DECFSM_MASK (0x7f0f0f0f)
1659 +#define DECFSM_IDLE (0x01010101)
1660 +#endif
1661 --- /dev/null
1662 +++ b/drivers/mtd/nand/mtksdg1_nand_nfi.h
1663 @@ -0,0 +1,119 @@
1664 +/*
1665 + * MTK smart device NAND Flash controller register.
1666 + * Copyright (C) 2015-2016 MediaTek Inc.
1667 + * Author: Xiaolei.Li <xiaolei.li@mediatek.com>
1668 + *
1669 + * This program is free software; you can redistribute it and/or modify
1670 + * it under the terms of the GNU General Public License version 2 as
1671 + * published by the Free Software Foundation.
1672 + *
1673 + * This program is distributed in the hope that it will be useful,
1674 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1675 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1676 + * GNU General Public License for more details.
1677 + */
1678 +
1679 +#ifndef MTKSDG1_NAND_NFI_H
1680 +#define MTKSDG1_NAND_NFI_H
1681 +
1682 +/* NAND controller register definition */
1683 +#define MTKSDG1_NFI_CNFG (0x00)
1684 +#define CNFG_AHB BIT(0)
1685 +#define CNFG_READ_EN BIT(1)
1686 +#define CNFG_DMA_BURST_EN BIT(2)
1687 +#define CNFG_BYTE_RW BIT(6)
1688 +#define CNFG_HW_ECC_EN BIT(8)
1689 +#define CNFG_AUTO_FMT_EN BIT(9)
1690 +#define CNFG_OP_IDLE (0 << 12)
1691 +#define CNFG_OP_READ (1 << 12)
1692 +#define CNFG_OP_SRD (2 << 12)
1693 +#define CNFG_OP_PRGM (3 << 12)
1694 +#define CNFG_OP_ERASE (4 << 12)
1695 +#define CNFG_OP_RESET (5 << 12)
1696 +#define CNFG_OP_CUST (6 << 12)
1697 +
1698 +#define MTKSDG1_NFI_PAGEFMT (0x04)
1699 +#define PAGEFMT_FDM_ECC_SHIFT (12)
1700 +#define PAGEFMT_FDM_SHIFT (8)
1701 +#define PAGEFMT_SPARE_16 (0)
1702 +#define PAGEFMT_SPARE_32 (4)
1703 +#define PAGEFMT_SPARE_SHIFT (4)
1704 +#define PAGEFMT_SEC_SEL_512 BIT(2)
1705 +#define PAGEFMT_512_2K (0)
1706 +#define PAGEFMT_2K_4K (1)
1707 +#define PAGEFMT_4K_8K (2)
1708 +
1709 +/* NFI control */
1710 +#define MTKSDG1_NFI_CON (0x08)
1711 +#define CON_FIFO_FLUSH BIT(0)
1712 +#define CON_NFI_RST BIT(1)
1713 +#define CON_SRD BIT(4) /* single read */
1714 +#define CON_BRD BIT(8) /* burst read */
1715 +#define CON_BWR BIT(9) /* burst write */
1716 +#define CON_SEC_SHIFT (12)
1717 +
1718 +/* Timming control register */
1719 +#define MTKSDG1_NFI_ACCCON (0x0C)
1720 +
1721 +#define MTKSDG1_NFI_INTR_EN (0x10)
1722 +#define INTR_RD_DONE_EN BIT(0)
1723 +#define INTR_WR_DONE_EN BIT(1)
1724 +#define INTR_RST_DONE_EN BIT(2)
1725 +#define INTR_ERS_DONE_EN BIT(3)
1726 +#define INTR_BUSY_RT_EN BIT(4)
1727 +#define INTR_AHB_DONE_EN BIT(6)
1728 +
1729 +#define MTKSDG1_NFI_INTR_STA (0x14)
1730 +
1731 +#define MTKSDG1_NFI_CMD (0x20)
1732 +
1733 +#define MTKSDG1_NFI_ADDRNOB (0x30)
1734 +#define ADDR_ROW_NOB_SHIFT (4)
1735 +
1736 +#define MTKSDG1_NFI_COLADDR (0x34)
1737 +#define MTKSDG1_NFI_ROWADDR (0x38)
1738 +#define MTKSDG1_NFI_STRDATA (0x40)
1739 +#define MTKSDG1_NFI_CNRNB (0x44)
1740 +#define MTKSDG1_NFI_DATAW (0x50)
1741 +#define MTKSDG1_NFI_DATAR (0x54)
1742 +#define MTKSDG1_NFI_PIO_DIRDY (0x58)
1743 +#define PIO_DI_RDY (0x01)
1744 +
1745 +/* NFI state*/
1746 +#define MTKSDG1_NFI_STA (0x60)
1747 +#define STA_CMD BIT(0)
1748 +#define STA_ADDR BIT(1)
1749 +#define STA_DATAR BIT(2)
1750 +#define STA_DATAW BIT(3)
1751 +#define STA_EMP_PAGE BIT(12)
1752 +
1753 +#define MTKSDG1_NFI_FIFOSTA (0x64)
1754 +
1755 +#define MTKSDG1_NFI_ADDRCNTR (0x70)
1756 +#define CNTR_MASK GENMASK(16, 12)
1757 +
1758 +#define MTKSDG1_NFI_STRADDR (0x80)
1759 +#define MTKSDG1_NFI_BYTELEN (0x84)
1760 +#define MTKSDG1_NFI_CSEL (0x90)
1761 +#define MTKSDG1_NFI_IOCON (0x94)
1762 +
1763 +/* FDM data for sector: FDM0[L,H] - FDMF[L,H] */
1764 +#define MTKSDG1_NFI_FDM_MAX_SEC (0x10)
1765 +#define MTKSDG1_NFI_FDM_REG_SIZE (8)
1766 +#define MTKSDG1_NFI_FDM0L (0xA0)
1767 +#define MTKSDG1_NFI_FDM0M (0xA4)
1768 +
1769 +
1770 +#define MTKSDG1_NFI_FIFODATA0 (0x190)
1771 +#define MTKSDG1_NFI_DEBUG_CON1 (0x220)
1772 +#define MTKSDG1_NFI_MASTER_STA (0x224)
1773 +#define MASTER_STA_MASK (0x0FFF)
1774 +
1775 +#define MTKSDG1_NFI_RANDOM_CNFG (0x238)
1776 +#define MTKSDG1_NFI_EMPTY_THRESH (0x23C)
1777 +#define MTKSDG1_NFI_NAND_TYPE (0x240)
1778 +#define MTKSDG1_NFI_ACCCON1 (0x244)
1779 +#define MTKSDG1_NFI_DELAY_CTRL (0x248)
1780 +
1781 +#endif
1782 +
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