kernel: update kernel 4.4 to version 4.4.9
[openwrt/openwrt.git] / target / linux / mediatek / patches-4.4 / 0062-clk-mediatek-Export-CPU-mux-clocks-for-CPU-frequency.patch
1 From 2ed6efcef399d15910ff60eef72b4cf8e5265c47 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Thu, 31 Mar 2016 02:26:37 +0200
4 Subject: [PATCH 62/91] clk: mediatek: Export CPU mux clocks for CPU frequency
5 control
6
7 This patch adds CPU mux clocks which are used by Mediatek cpufreq driver
8 for intermediate clock source switching.
9
10 Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
11 ---
12 drivers/clk/mediatek/Makefile | 2 +-
13 drivers/clk/mediatek/clk-cpumux.c | 127 ++++++++++++++++++++++++++++++++
14 drivers/clk/mediatek/clk-cpumux.h | 22 ++++++
15 drivers/clk/mediatek/clk-mt2701.c | 8 ++
16 drivers/clk/mediatek/clk-mt8173.c | 23 ++++++
17 include/dt-bindings/clock/mt2701-clk.h | 3 +-
18 include/dt-bindings/clock/mt8173-clk.h | 4 +-
19 7 files changed, 186 insertions(+), 3 deletions(-)
20 create mode 100644 drivers/clk/mediatek/clk-cpumux.c
21 create mode 100644 drivers/clk/mediatek/clk-cpumux.h
22
23 --- a/drivers/clk/mediatek/Makefile
24 +++ b/drivers/clk/mediatek/Makefile
25 @@ -1,4 +1,4 @@
26 -obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o
27 +obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o
28 obj-$(CONFIG_RESET_CONTROLLER) += reset.o
29 obj-$(CONFIG_COMMON_CLK_MT2701) += clk-mt2701.o
30 obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
31 --- /dev/null
32 +++ b/drivers/clk/mediatek/clk-cpumux.c
33 @@ -0,0 +1,127 @@
34 +/*
35 + * Copyright (c) 2015 Linaro Ltd.
36 + * Author: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
37 + *
38 + * This program is free software; you can redistribute it and/or modify
39 + * it under the terms of the GNU General Public License version 2 as
40 + * published by the Free Software Foundation.
41 + *
42 + * This program is distributed in the hope that it will be useful,
43 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
44 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
45 + * GNU General Public License for more details.
46 + */
47 +
48 +#include <linux/clk-provider.h>
49 +#include <linux/mfd/syscon.h>
50 +#include <linux/slab.h>
51 +
52 +#include "clk-mtk.h"
53 +#include "clk-cpumux.h"
54 +
55 +struct mtk_clk_cpumux {
56 + struct clk_hw hw;
57 + struct regmap *regmap;
58 + u32 reg;
59 + u32 mask;
60 + u8 shift;
61 +};
62 +
63 +static inline struct mtk_clk_cpumux *to_clk_mux(struct clk_hw *_hw)
64 +{
65 + return container_of(_hw, struct mtk_clk_cpumux, hw);
66 +}
67 +
68 +static u8 clk_cpumux_get_parent(struct clk_hw *hw)
69 +{
70 + struct mtk_clk_cpumux *mux = to_clk_mux(hw);
71 + int num_parents = clk_hw_get_num_parents(hw);
72 + unsigned int val;
73 +
74 + regmap_read(mux->regmap, mux->reg, &val);
75 +
76 + val >>= mux->shift;
77 + val &= mux->mask;
78 +
79 + if (val >= num_parents)
80 + return -EINVAL;
81 +
82 + return val;
83 +}
84 +
85 +static int clk_cpumux_set_parent(struct clk_hw *hw, u8 index)
86 +{
87 + struct mtk_clk_cpumux *mux = to_clk_mux(hw);
88 + u32 mask, val;
89 +
90 + val = index << mux->shift;
91 + mask = mux->mask << mux->shift;
92 +
93 + return regmap_update_bits(mux->regmap, mux->reg, mask, val);
94 +}
95 +
96 +static const struct clk_ops clk_cpumux_ops = {
97 + .get_parent = clk_cpumux_get_parent,
98 + .set_parent = clk_cpumux_set_parent,
99 +};
100 +
101 +static struct clk __init *mtk_clk_register_cpumux(const struct mtk_composite *mux,
102 + struct regmap *regmap)
103 +{
104 + struct mtk_clk_cpumux *cpumux;
105 + struct clk *clk;
106 + struct clk_init_data init;
107 +
108 + cpumux = kzalloc(sizeof(*cpumux), GFP_KERNEL);
109 + if (!cpumux)
110 + return ERR_PTR(-ENOMEM);
111 +
112 + init.name = mux->name;
113 + init.ops = &clk_cpumux_ops;
114 + init.parent_names = mux->parent_names;
115 + init.num_parents = mux->num_parents;
116 + init.flags = mux->flags;
117 +
118 + cpumux->reg = mux->mux_reg;
119 + cpumux->shift = mux->mux_shift;
120 + cpumux->mask = BIT(mux->mux_width) - 1;
121 + cpumux->regmap = regmap;
122 + cpumux->hw.init = &init;
123 +
124 + clk = clk_register(NULL, &cpumux->hw);
125 + if (IS_ERR(clk))
126 + kfree(cpumux);
127 +
128 + return clk;
129 +}
130 +
131 +int __init mtk_clk_register_cpumuxes(struct device_node *node,
132 + const struct mtk_composite *clks, int num,
133 + struct clk_onecell_data *clk_data)
134 +{
135 + int i;
136 + struct clk *clk;
137 + struct regmap *regmap;
138 +
139 + regmap = syscon_node_to_regmap(node);
140 + if (IS_ERR(regmap)) {
141 + pr_err("Cannot find regmap for %s: %ld\n", node->full_name,
142 + PTR_ERR(regmap));
143 + return PTR_ERR(regmap);
144 + }
145 +
146 + for (i = 0; i < num; i++) {
147 + const struct mtk_composite *mux = &clks[i];
148 +
149 + clk = mtk_clk_register_cpumux(mux, regmap);
150 + if (IS_ERR(clk)) {
151 + pr_err("Failed to register clk %s: %ld\n",
152 + mux->name, PTR_ERR(clk));
153 + continue;
154 + }
155 +
156 + clk_data->clks[mux->id] = clk;
157 + }
158 +
159 + return 0;
160 +}
161 --- /dev/null
162 +++ b/drivers/clk/mediatek/clk-cpumux.h
163 @@ -0,0 +1,22 @@
164 +/*
165 + * Copyright (c) 2015 Linaro Ltd.
166 + * Author: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
167 + *
168 + * This program is free software; you can redistribute it and/or modify
169 + * it under the terms of the GNU General Public License version 2 as
170 + * published by the Free Software Foundation.
171 + *
172 + * This program is distributed in the hope that it will be useful,
173 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
174 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
175 + * GNU General Public License for more details.
176 + */
177 +
178 +#ifndef __DRV_CLK_CPUMUX_H
179 +#define __DRV_CLK_CPUMUX_H
180 +
181 +int mtk_clk_register_cpumuxes(struct device_node *node,
182 + const struct mtk_composite *clks, int num,
183 + struct clk_onecell_data *clk_data);
184 +
185 +#endif /* __DRV_CLK_CPUMUX_H */
186 --- a/drivers/clk/mediatek/clk-mt2701.c
187 +++ b/drivers/clk/mediatek/clk-mt2701.c
188 @@ -18,6 +18,7 @@
189
190 #include "clk-mtk.h"
191 #include "clk-gate.h"
192 +#include "clk-cpumux.h"
193
194 #include <dt-bindings/clock/mt2701-clk.h>
195
196 @@ -465,6 +466,10 @@ static const char * const cpu_parents[]
197 "mmpll"
198 };
199
200 +static const struct mtk_composite cpu_muxes[] __initconst = {
201 + MUX(CLK_INFRA_CPUSEL, "infra_cpu_sel", cpu_parents, 0x0000, 2, 2),
202 +};
203 +
204 static const struct mtk_composite top_muxes[] __initconst = {
205 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
206 0x0040, 0, 3, INVALID_MUX_GATE_BIT),
207 @@ -677,6 +682,9 @@ static void __init mtk_infrasys_init(str
208 mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
209 clk_data);
210
211 + mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
212 + clk_data);
213 +
214 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
215 if (r)
216 pr_err("%s(): could not register clock provider: %d\n",
217 --- a/drivers/clk/mediatek/clk-mt8173.c
218 +++ b/drivers/clk/mediatek/clk-mt8173.c
219 @@ -18,6 +18,7 @@
220
221 #include "clk-mtk.h"
222 #include "clk-gate.h"
223 +#include "clk-cpumux.h"
224
225 #include <dt-bindings/clock/mt8173-clk.h>
226
227 @@ -526,6 +527,25 @@ static const char * const i2s3_b_ck_pare
228 "apll2_div5"
229 };
230
231 +static const char * const ca53_parents[] __initconst = {
232 + "clk26m",
233 + "armca7pll",
234 + "mainpll",
235 + "univpll"
236 +};
237 +
238 +static const char * const ca57_parents[] __initconst = {
239 + "clk26m",
240 + "armca15pll",
241 + "mainpll",
242 + "univpll"
243 +};
244 +
245 +static const struct mtk_composite cpu_muxes[] __initconst = {
246 + MUX(CLK_INFRA_CA53SEL, "infra_ca53_sel", ca53_parents, 0x0000, 0, 2),
247 + MUX(CLK_INFRA_CA57SEL, "infra_ca57_sel", ca57_parents, 0x0000, 2, 2),
248 +};
249 +
250 static const struct mtk_composite top_muxes[] __initconst = {
251 /* CLK_CFG_0 */
252 MUX(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3),
253 @@ -945,6 +965,9 @@ static void __init mtk_infrasys_init(str
254 clk_data);
255 mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
256
257 + mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
258 + clk_data);
259 +
260 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
261 if (r)
262 pr_err("%s(): could not register clock provider: %d\n",
263 --- a/include/dt-bindings/clock/mt2701-clk.h
264 +++ b/include/dt-bindings/clock/mt2701-clk.h
265 @@ -217,7 +217,8 @@
266 #define CLK_INFRA_PMICWRAP 17
267 #define CLK_INFRA_DDCCI 18
268 #define CLK_INFRA_CLK_13M 19
269 -#define CLK_INFRA_NR 20
270 +#define CLK_INFRA_CPUSEL 20
271 +#define CLK_INFRA_NR 21
272
273 /* PERICFG */
274
275 --- a/include/dt-bindings/clock/mt8173-clk.h
276 +++ b/include/dt-bindings/clock/mt8173-clk.h
277 @@ -192,7 +192,9 @@
278 #define CLK_INFRA_PMICSPI 10
279 #define CLK_INFRA_PMICWRAP 11
280 #define CLK_INFRA_CLK_13M 12
281 -#define CLK_INFRA_NR_CLK 13
282 +#define CLK_INFRA_CA53SEL 13
283 +#define CLK_INFRA_CA57SEL 14
284 +#define CLK_INFRA_NR_CLK 15
285
286 /* PERI_SYS */
287