target/linux/mediatek/patches-4.4/0070-net-mediatek-update-the-IRQ-part-of-the-binding-docu.patch

   1 From 297ef52cd21e28da671996d7b4f39f268d2d0ec1 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Tue, 29 Mar 2016 14:32:07 +0200
   4 Subject: [PATCH 070/102] net: mediatek: update the IRQ part of the binding
   5  document
   6
   7 The current binding document only describes a single interrupt. Update the
   8 document by adding the 2 other interrupts.
   9
  10 The driver currently only uses a single interrupt. The HW is however able
  11 to using IRQ grouping to split TX and RX onto separate GIC irqs.
  12
  13 Signed-off-by: John Crispin <blogic@openwrt.org>
  14  Acked-by: Rob Herring <robh@kernel.org>
  15 ---
  16  Documentation/devicetree/bindings/net/mediatek-net.txt |    7 +++++--
  17  1 file changed, 5 insertions(+), 2 deletions(-)
  18
  19 --- a/Documentation/devicetree/bindings/net/mediatek-net.txt
  20 +++ b/Documentation/devicetree/bindings/net/mediatek-net.txt
  21 @@ -9,7 +9,8 @@ have dual GMAC each represented by a chi
  22  Required properties:
  23  - compatible: Should be "mediatek,mt7623-eth"
  24  - reg: Address and length of the register set for the device
  25 -- interrupts: Should contain the frame engines interrupt
  26 +- interrupts: Should contain the three frame engines interrupts in numeric
  27 +       order. These are fe_int0, fe_int1 and fe_int2.
  28  - clocks: the clock used by the core
  29  - clock-names: the names of the clock listed in the clocks property. These are
  30         "ethif", "esw", "gp2", "gp1"
  31 @@ -42,7 +43,9 @@ eth: ethernet@1b100000 {
  32                  <&ethsys CLK_ETHSYS_GP2>,
  33                  <&ethsys CLK_ETHSYS_GP1>;
  34         clock-names = "ethif", "esw", "gp2", "gp1";
  35 -       interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>;
  36 +       interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW
  37 +                     GIC_SPI 199 IRQ_TYPE_LEVEL_LOW
  38 +                     GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
  39         power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
  40         resets = <&ethsys MT2701_ETHSYS_ETH_RST>;
  41         reset-names = "eth";