target/linux/mediatek/patches-4.4/0071-pwm-add-pwm-mediatek.patch

   1 From 6f5941c93bdf7649f392f1263b9068d360ceab4d Mon Sep 17 00:00:00 2001
   2 From: John Crispin <john@phrozen.org>
   3 Date: Fri, 6 May 2016 02:55:48 +0200
   4 Subject: [PATCH 071/102] pwm: add pwm-mediatek
   5
   6 Signed-off-by: John Crispin <john@phrozen.org>
   7 ---
   8  arch/arm/boot/dts/mt7623-evb.dts |   17 +++
   9  arch/arm/boot/dts/mt7623.dtsi    |   22 ++++
  10  drivers/pwm/Kconfig              |    9 ++
  11  drivers/pwm/Makefile             |    1 +
  12  drivers/pwm/pwm-mediatek.c       |  230 ++++++++++++++++++++++++++++++++++++++
  13  5 files changed, 279 insertions(+)
  14  create mode 100644 drivers/pwm/pwm-mediatek.c
  15
  16 diff --git a/arch/arm/boot/dts/mt7623-evb.dts b/arch/arm/boot/dts/mt7623-evb.dts
  17 index 5ad1448..70bc6b1 100644
  18 --- a/arch/arm/boot/dts/mt7623-evb.dts
  19 +++ b/arch/arm/boot/dts/mt7623-evb.dts
  20 @@ -341,6 +341,17 @@
  21                         output-low;
  22                 };
  23         };
  24 +
  25 +       pwm_pins: pwm {
  26 +               pins_pwm1 {
  27 +                       pinmux = <MT7623_PIN_204_PWM1_FUNC_PWM1>;
  28 +               };
  29 +
  30 +               pins_pwm2 {
  31 +                       pinmux = <MT7623_PIN_205_PWM2_FUNC_PWM2>;
  32 +               };
  33 +       };
  34 +
  35  };
  36
  37  &nandc {
  38 @@ -419,3 +430,9 @@
  39         mediatek,reset-pin = <&pio 15 0>;
  40         status = "okay";
  41  };
  42 +
  43 +&pwm {
  44 +       pinctrl-names = "default";
  45 +       pinctrl-0 = <&pwm_pins>;
  46 +       status = "okay";
  47 +};
  48 diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
  49 index cbbdf16..3f50e7e 100644
  50 --- a/arch/arm/boot/dts/mt7623.dtsi
  51 +++ b/arch/arm/boot/dts/mt7623.dtsi
  52 @@ -324,6 +324,28 @@
  53                 status = "disabled";
  54         };
  55
  56 +       pwm: pwm@11006000 {
  57 +               compatible = "mediatek,mt7623-pwm";
  58 +
  59 +               reg = <0 0x11006000 0 0x1000>;
  60 +
  61 +               resets = <&pericfg MT2701_PERI_PWM_SW_RST>;
  62 +               reset-names = "pwm";
  63 +
  64 +               #pwm-cells = <2>;
  65 +               clocks = <&topckgen CLK_TOP_PWM_SEL>,
  66 +                        <&pericfg CLK_PERI_PWM>,
  67 +                        <&pericfg CLK_PERI_PWM1>,
  68 +                        <&pericfg CLK_PERI_PWM2>,
  69 +                        <&pericfg CLK_PERI_PWM3>,
  70 +                        <&pericfg CLK_PERI_PWM4>,
  71 +                        <&pericfg CLK_PERI_PWM5>;
  72 +               clock-names = "top", "main", "pwm1", "pwm2",
  73 +                             "pwm3", "pwm4", "pwm5";
  74 +
  75 +               status = "disabled";
  76 +       };
  77 +
  78         spi: spi@1100a000 {
  79                 compatible = "mediatek,mt7623-spi", "mediatek,mt6589-spi";
  80                 reg = <0 0x1100a000 0 0x1000>;
  81 diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
  82 index 2f4641a..5860b1f 100644
  83 --- a/drivers/pwm/Kconfig
  84 +++ b/drivers/pwm/Kconfig
  85 @@ -260,6 +260,15 @@ config PWM_MTK_DISP
  86           To compile this driver as a module, choose M here: the module
  87           will be called pwm-mtk-disp.
  88
  89 +config PWM_MEDIATEK
  90 +       tristate "MediaTek PWM support"
  91 +       depends on ARCH_MEDIATEK || COMPILE_TEST
  92 +       help
  93 +         Generic PWM framework driver for Mediatek ARM SoC.
  94 +
  95 +         To compile this driver as a module, choose M here: the module
  96 +         will be called pwm-mxs.
  97 +
  98  config PWM_MXS
  99         tristate "Freescale MXS PWM support"
 100         depends on ARCH_MXS && OF
 101 diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
 102 index 69b8275..a90d5de 100644
 103 --- a/drivers/pwm/Makefile
 104 +++ b/drivers/pwm/Makefile
 105 @@ -22,6 +22,7 @@ obj-$(CONFIG_PWM_LPC32XX)     += pwm-lpc32xx.o
 106  obj-$(CONFIG_PWM_LPSS)         += pwm-lpss.o
 107  obj-$(CONFIG_PWM_LPSS_PCI)     += pwm-lpss-pci.o
 108  obj-$(CONFIG_PWM_LPSS_PLATFORM)        += pwm-lpss-platform.o
 109 +obj-$(CONFIG_PWM_MEDIATEK)     += pwm-mediatek.o
 110  obj-$(CONFIG_PWM_MTK_DISP)     += pwm-mtk-disp.o
 111  obj-$(CONFIG_PWM_MXS)          += pwm-mxs.o
 112  obj-$(CONFIG_PWM_PCA9685)      += pwm-pca9685.o
 113 diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c
 114 new file mode 100644
 115 index 0000000..9d8d16d
 116 --- /dev/null
 117 +++ b/drivers/pwm/pwm-mediatek.c
 118 @@ -0,0 +1,230 @@
 119 +/*
 120 + * Mediatek Pulse Width Modulator driver
 121 + *
 122 + * Copyright (C) 2015 John Crispin <blogic@openwrt.org>
 123 + *
 124 + * This file is licensed under the terms of the GNU General Public
 125 + * License version 2. This program is licensed "as is" without any
 126 + * warranty of any kind, whether express or implied.
 127 + */
 128 +
 129 +#include <linux/err.h>
 130 +#include <linux/io.h>
 131 +#include <linux/ioport.h>
 132 +#include <linux/kernel.h>
 133 +#include <linux/module.h>
 134 +#include <linux/clk.h>
 135 +#include <linux/of.h>
 136 +#include <linux/platform_device.h>
 137 +#include <linux/pwm.h>
 138 +#include <linux/slab.h>
 139 +#include <linux/types.h>
 140 +
 141 +#define NUM_PWM                5
 142 +
 143 +/* PWM registers and bits definitions */
 144 +#define PWMCON                 0x00
 145 +#define PWMHDUR                        0x04
 146 +#define PWMLDUR                        0x08
 147 +#define PWMGDUR                        0x0c
 148 +#define PWMWAVENUM             0x28
 149 +#define PWMDWIDTH              0x2c
 150 +#define PWMTHRES               0x30
 151 +
 152 +/**
 153 + * struct mtk_pwm_chip - struct representing pwm chip
 154 + *
 155 + * @mmio_base: base address of pwm chip
 156 + * @chip: linux pwm chip representation
 157 + */
 158 +struct mtk_pwm_chip {
 159 +       void __iomem *mmio_base;
 160 +       struct pwm_chip chip;
 161 +       struct clk *clk_top;
 162 +       struct clk *clk_main;
 163 +       struct clk *clk_pwm[NUM_PWM];
 164 +};
 165 +
 166 +static inline struct mtk_pwm_chip *to_mtk_pwm_chip(struct pwm_chip *chip)
 167 +{
 168 +       return container_of(chip, struct mtk_pwm_chip, chip);
 169 +}
 170 +
 171 +static inline u32 mtk_pwm_readl(struct mtk_pwm_chip *chip, unsigned int num,
 172 +                                 unsigned long offset)
 173 +{
 174 +       return ioread32(chip->mmio_base + 0x10 + (num * 0x40) + offset);
 175 +}
 176 +
 177 +static inline void mtk_pwm_writel(struct mtk_pwm_chip *chip,
 178 +                                   unsigned int num, unsigned long offset,
 179 +                                   unsigned long val)
 180 +{
 181 +       iowrite32(val, chip->mmio_base + 0x10 + (num * 0x40) + offset);
 182 +}
 183 +
 184 +static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 185 +                           int duty_ns, int period_ns)
 186 +{
 187 +       struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
 188 +       u32 resolution = 100 / 4;
 189 +       u32 clkdiv = 0;
 190 +
 191 +       resolution = 1000000000 / (clk_get_rate(pc->clk_pwm[pwm->hwpwm]));
 192 +
 193 +       while (period_ns / resolution  > 8191) {
 194 +               clkdiv++;
 195 +               resolution *= 2;
 196 +       }
 197 +
 198 +       if (clkdiv > 7)
 199 +               return -1;
 200 +
 201 +       mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | BIT(3) | clkdiv);
 202 +       mtk_pwm_writel(pc, pwm->hwpwm, PWMDWIDTH, period_ns / resolution);
 203 +       mtk_pwm_writel(pc, pwm->hwpwm, PWMTHRES, duty_ns / resolution);
 204 +       return 0;
 205 +}
 206 +
 207 +static int mtk_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 208 +{
 209 +       struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
 210 +       u32 val;
 211 +       int ret;
 212 +
 213 +       ret = clk_prepare(pc->clk_pwm[pwm->hwpwm]);
 214 +       if (ret < 0)
 215 +               return ret;
 216 +
 217 +       val = ioread32(pc->mmio_base);
 218 +       val |= BIT(pwm->hwpwm);
 219 +       iowrite32(val, pc->mmio_base);
 220 +
 221 +       return 0;
 222 +}
 223 +
 224 +static void mtk_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 225 +{
 226 +       struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
 227 +       u32 val;
 228 +
 229 +       val = ioread32(pc->mmio_base);
 230 +       val &= ~BIT(pwm->hwpwm);
 231 +       iowrite32(val, pc->mmio_base);
 232 +        clk_unprepare(pc->clk_pwm[pwm->hwpwm]);
 233 +}
 234 +
 235 +static const struct pwm_ops mtk_pwm_ops = {
 236 +       .config = mtk_pwm_config,
 237 +       .enable = mtk_pwm_enable,
 238 +       .disable = mtk_pwm_disable,
 239 +       .owner = THIS_MODULE,
 240 +};
 241 +
 242 +static int mtk_pwm_probe(struct platform_device *pdev)
 243 +{
 244 +       struct mtk_pwm_chip *pc;
 245 +       struct resource *r;
 246 +       int ret;
 247 +
 248 +       pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
 249 +       if (!pc)
 250 +               return -ENOMEM;
 251 +
 252 +       r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 253 +       pc->mmio_base = devm_ioremap_resource(&pdev->dev, r);
 254 +       if (IS_ERR(pc->mmio_base))
 255 +               return PTR_ERR(pc->mmio_base);
 256 +
 257 +       pc->clk_main = devm_clk_get(&pdev->dev, "main");
 258 +        if (IS_ERR(pc->clk_main))
 259 +               return PTR_ERR(pc->clk_main);
 260 +
 261 +       pc->clk_top = devm_clk_get(&pdev->dev, "top");
 262 +        if (IS_ERR(pc->clk_top))
 263 +               return PTR_ERR(pc->clk_top);
 264 +
 265 +       pc->clk_pwm[0] = devm_clk_get(&pdev->dev, "pwm1");
 266 +        if (IS_ERR(pc->clk_pwm[0]))
 267 +               return PTR_ERR(pc->clk_pwm[0]);
 268 +
 269 +       pc->clk_pwm[1] = devm_clk_get(&pdev->dev, "pwm2");
 270 +        if (IS_ERR(pc->clk_pwm[1]))
 271 +               return PTR_ERR(pc->clk_pwm[1]);
 272 +
 273 +       pc->clk_pwm[2] = devm_clk_get(&pdev->dev, "pwm3");
 274 +        if (IS_ERR(pc->clk_pwm[2]))
 275 +               return PTR_ERR(pc->clk_pwm[2]);
 276 +
 277 +       pc->clk_pwm[3] = devm_clk_get(&pdev->dev, "pwm4");
 278 +        if (IS_ERR(pc->clk_pwm[3]))
 279 +               return PTR_ERR(pc->clk_pwm[3]);
 280 +
 281 +       pc->clk_pwm[4] = devm_clk_get(&pdev->dev, "pwm5");
 282 +        if (IS_ERR(pc->clk_pwm[4]))
 283 +               return PTR_ERR(pc->clk_pwm[4]);
 284 +
 285 +       ret = clk_prepare(pc->clk_top);
 286 +        if (ret < 0)
 287 +               return ret;
 288 +
 289 +       ret = clk_prepare(pc->clk_main);
 290 +       if (ret < 0)
 291 +               goto disable_clk_top;
 292 +
 293 +       platform_set_drvdata(pdev, pc);
 294 +
 295 +       pc->chip.dev = &pdev->dev;
 296 +       pc->chip.ops = &mtk_pwm_ops;
 297 +       pc->chip.base = -1;
 298 +       pc->chip.npwm = NUM_PWM;
 299 +
 300 +       ret = pwmchip_add(&pc->chip);
 301 +       if (ret < 0) {
 302 +               dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
 303 +               goto disable_clk_main;
 304 +       }
 305 +
 306 +       return 0;
 307 +
 308 +disable_clk_main:
 309 +       clk_unprepare(pc->clk_main);
 310 +disable_clk_top:
 311 +       clk_unprepare(pc->clk_top);
 312 +
 313 +       return ret;
 314 +}
 315 +
 316 +static int mtk_pwm_remove(struct platform_device *pdev)
 317 +{
 318 +       struct mtk_pwm_chip *pc = platform_get_drvdata(pdev);
 319 +       int i;
 320 +
 321 +       for (i = 0; i < NUM_PWM; i++)
 322 +               pwm_disable(&pc->chip.pwms[i]);
 323 +
 324 +       return pwmchip_remove(&pc->chip);
 325 +}
 326 +
 327 +static const struct of_device_id mtk_pwm_of_match[] = {
 328 +       { .compatible = "mediatek,mt7623-pwm" },
 329 +       { }
 330 +};
 331 +
 332 +MODULE_DEVICE_TABLE(of, mtk_pwm_of_match);
 333 +
 334 +static struct platform_driver mtk_pwm_driver = {
 335 +       .driver = {
 336 +               .name = "mtk-pwm",
 337 +               .owner = THIS_MODULE,
 338 +               .of_match_table = mtk_pwm_of_match,
 339 +       },
 340 +       .probe = mtk_pwm_probe,
 341 +       .remove = mtk_pwm_remove,
 342 +};
 343 +
 344 +module_platform_driver(mtk_pwm_driver);
 345 +
 346 +MODULE_LICENSE("GPL");
 347 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
 348 +MODULE_ALIAS("platform:mtk-pwm");
 349 --
 350 1.7.10.4
 351