ramips: fix the number of uarts for MT7688
[openwrt/openwrt.git] / target / linux / mediatek / patches-4.4 / 0098-net-next-mediatek-only-trigger-the-tx-watchdog-reset.patch
1 From cd1343c14328a5de1a58c47b81b8a2febb31d542 Mon Sep 17 00:00:00 2001
2 From: John Crispin <john@phrozen.org>
3 Date: Tue, 10 May 2016 11:16:30 +0200
4 Subject: [PATCH 098/102] net-next: mediatek: only trigger the tx watchdog
5 reset when all devices are stalled
6
7 Signed-off-by: Sean Wang <keyhaede@gmail.com>
8 Signed-off-by: John Crispin <john@phrozen.org>
9 ---
10 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 14 ++++++++++++--
11 drivers/net/ethernet/mediatek/mtk_eth_soc.h | 1 +
12 2 files changed, 13 insertions(+), 2 deletions(-)
13
14 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
15 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
16 @@ -1267,11 +1267,21 @@ static void mtk_tx_timeout(struct net_de
17 {
18 struct mtk_mac *mac = netdev_priv(dev);
19 struct mtk_eth *eth = mac->hw;
20 + int i, reset = 0;
21
22 eth->netdev[mac->id]->stats.tx_errors++;
23 netif_err(eth, tx_err, dev,
24 "transmit timed out\n");
25 - schedule_work(&eth->pending_work);
26 +
27 + for (i = 0; i < MTK_MAC_COUNT; i++) {
28 + if (!eth->netdev[i] ||
29 + time_after(jiffies, dev_trans_start(eth->netdev[i]) +
30 + MTK_WDT_TIMEOUT))
31 + reset++;
32 + }
33 +
34 + if (reset == MTK_MAC_COUNT)
35 + schedule_work(&eth->pending_work);
36 }
37
38 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth)
39 @@ -1765,7 +1775,7 @@ static int mtk_add_mac(struct mtk_eth *e
40 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
41
42 SET_NETDEV_DEV(eth->netdev[id], eth->dev);
43 - eth->netdev[id]->watchdog_timeo = 5 * HZ;
44 + eth->netdev[id]->watchdog_timeo = MTK_WDT_TIMEOUT;
45 eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
46 eth->netdev[id]->base_addr = (unsigned long)eth->base;
47 eth->netdev[id]->vlan_features = MTK_HW_FEATURES &
48 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
49 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
50 @@ -15,6 +15,7 @@
51 #ifndef MTK_ETH_H
52 #define MTK_ETH_H
53
54 +#define MTK_WDT_TIMEOUT (4 * HZ)
55 #define MTK_QDMA_PAGE_SIZE 2048
56 #define MTK_MAX_RX_LENGTH 1536
57 #define MTK_TX_DMA_BUF_LEN 0x3fff