target/linux/mediatek/patches-4.9/0016-pwm-add-pwm-mediatek.patch

   1 From 201be68268eddb1568c41780a62868cc1666a2de Mon Sep 17 00:00:00 2001
   2 From: John Crispin <john@phrozen.org>
   3 Date: Fri, 6 May 2016 02:55:48 +0200
   4 Subject: [PATCH 16/57] pwm: add pwm-mediatek
   5
   6 Signed-off-by: John Crispin <john@phrozen.org>
   7 ---
   8  drivers/pwm/Kconfig        |   9 ++
   9  drivers/pwm/Makefile       |   1 +
  10  drivers/pwm/pwm-mediatek.c | 230 +++++++++++++++++++++++++++++++++++++++++++++
  11  3 files changed, 240 insertions(+)
  12  create mode 100644 drivers/pwm/pwm-mediatek.c
  13
  14 --- a/drivers/pwm/Kconfig
  15 +++ b/drivers/pwm/Kconfig
  16 @@ -282,6 +282,15 @@ config PWM_MTK_DISP
  17           To compile this driver as a module, choose M here: the module
  18           will be called pwm-mtk-disp.
  19
  20 +config PWM_MEDIATEK
  21 +       tristate "MediaTek PWM support"
  22 +       depends on ARCH_MEDIATEK || COMPILE_TEST
  23 +       help
  24 +         Generic PWM framework driver for Mediatek ARM SoC.
  25 +
  26 +         To compile this driver as a module, choose M here: the module
  27 +         will be called pwm-mxs.
  28 +
  29  config PWM_MXS
  30         tristate "Freescale MXS PWM support"
  31         depends on ARCH_MXS && OF
  32 --- a/drivers/pwm/Makefile
  33 +++ b/drivers/pwm/Makefile
  34 @@ -25,6 +25,7 @@ obj-$(CONFIG_PWM_LPSS)                += pwm-lpss.o
  35  obj-$(CONFIG_PWM_LPSS_PCI)     += pwm-lpss-pci.o
  36  obj-$(CONFIG_PWM_LPSS_PLATFORM)        += pwm-lpss-platform.o
  37  obj-$(CONFIG_PWM_MESON)                += pwm-meson.o
  38 +obj-$(CONFIG_PWM_MEDIATEK)     += pwm-mediatek.o
  39  obj-$(CONFIG_PWM_MTK_DISP)     += pwm-mtk-disp.o
  40  obj-$(CONFIG_PWM_MXS)          += pwm-mxs.o
  41  obj-$(CONFIG_PWM_OMAP_DMTIMER) += pwm-omap-dmtimer.o
  42 --- /dev/null
  43 +++ b/drivers/pwm/pwm-mediatek.c
  44 @@ -0,0 +1,230 @@
  45 +/*
  46 + * Mediatek Pulse Width Modulator driver
  47 + *
  48 + * Copyright (C) 2015 John Crispin <blogic@openwrt.org>
  49 + *
  50 + * This file is licensed under the terms of the GNU General Public
  51 + * License version 2. This program is licensed "as is" without any
  52 + * warranty of any kind, whether express or implied.
  53 + */
  54 +
  55 +#include <linux/err.h>
  56 +#include <linux/io.h>
  57 +#include <linux/ioport.h>
  58 +#include <linux/kernel.h>
  59 +#include <linux/module.h>
  60 +#include <linux/clk.h>
  61 +#include <linux/of.h>
  62 +#include <linux/platform_device.h>
  63 +#include <linux/pwm.h>
  64 +#include <linux/slab.h>
  65 +#include <linux/types.h>
  66 +
  67 +#define NUM_PWM                5
  68 +
  69 +/* PWM registers and bits definitions */
  70 +#define PWMCON                 0x00
  71 +#define PWMHDUR                        0x04
  72 +#define PWMLDUR                        0x08
  73 +#define PWMGDUR                        0x0c
  74 +#define PWMWAVENUM             0x28
  75 +#define PWMDWIDTH              0x2c
  76 +#define PWMTHRES               0x30
  77 +
  78 +/**
  79 + * struct mtk_pwm_chip - struct representing pwm chip
  80 + *
  81 + * @mmio_base: base address of pwm chip
  82 + * @chip: linux pwm chip representation
  83 + */
  84 +struct mtk_pwm_chip {
  85 +       void __iomem *mmio_base;
  86 +       struct pwm_chip chip;
  87 +       struct clk *clk_top;
  88 +       struct clk *clk_main;
  89 +       struct clk *clk_pwm[NUM_PWM];
  90 +};
  91 +
  92 +static inline struct mtk_pwm_chip *to_mtk_pwm_chip(struct pwm_chip *chip)
  93 +{
  94 +       return container_of(chip, struct mtk_pwm_chip, chip);
  95 +}
  96 +
  97 +static inline u32 mtk_pwm_readl(struct mtk_pwm_chip *chip, unsigned int num,
  98 +                                 unsigned long offset)
  99 +{
 100 +       return ioread32(chip->mmio_base + 0x10 + (num * 0x40) + offset);
 101 +}
 102 +
 103 +static inline void mtk_pwm_writel(struct mtk_pwm_chip *chip,
 104 +                                   unsigned int num, unsigned long offset,
 105 +                                   unsigned long val)
 106 +{
 107 +       iowrite32(val, chip->mmio_base + 0x10 + (num * 0x40) + offset);
 108 +}
 109 +
 110 +static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 111 +                           int duty_ns, int period_ns)
 112 +{
 113 +       struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
 114 +       u32 resolution = 100 / 4;
 115 +       u32 clkdiv = 0;
 116 +
 117 +       resolution = 1000000000 / (clk_get_rate(pc->clk_pwm[pwm->hwpwm]));
 118 +
 119 +       while (period_ns / resolution  > 8191) {
 120 +               clkdiv++;
 121 +               resolution *= 2;
 122 +       }
 123 +
 124 +       if (clkdiv > 7)
 125 +               return -1;
 126 +
 127 +       mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | BIT(3) | clkdiv);
 128 +       mtk_pwm_writel(pc, pwm->hwpwm, PWMDWIDTH, period_ns / resolution);
 129 +       mtk_pwm_writel(pc, pwm->hwpwm, PWMTHRES, duty_ns / resolution);
 130 +       return 0;
 131 +}
 132 +
 133 +static int mtk_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 134 +{
 135 +       struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
 136 +       u32 val;
 137 +       int ret;
 138 +
 139 +       ret = clk_prepare(pc->clk_pwm[pwm->hwpwm]);
 140 +       if (ret < 0)
 141 +               return ret;
 142 +
 143 +       val = ioread32(pc->mmio_base);
 144 +       val |= BIT(pwm->hwpwm);
 145 +       iowrite32(val, pc->mmio_base);
 146 +
 147 +       return 0;
 148 +}
 149 +
 150 +static void mtk_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 151 +{
 152 +       struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
 153 +       u32 val;
 154 +
 155 +       val = ioread32(pc->mmio_base);
 156 +       val &= ~BIT(pwm->hwpwm);
 157 +       iowrite32(val, pc->mmio_base);
 158 +        clk_unprepare(pc->clk_pwm[pwm->hwpwm]);
 159 +}
 160 +
 161 +static const struct pwm_ops mtk_pwm_ops = {
 162 +       .config = mtk_pwm_config,
 163 +       .enable = mtk_pwm_enable,
 164 +       .disable = mtk_pwm_disable,
 165 +       .owner = THIS_MODULE,
 166 +};
 167 +
 168 +static int mtk_pwm_probe(struct platform_device *pdev)
 169 +{
 170 +       struct mtk_pwm_chip *pc;
 171 +       struct resource *r;
 172 +       int ret;
 173 +
 174 +       pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
 175 +       if (!pc)
 176 +               return -ENOMEM;
 177 +
 178 +       r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 179 +       pc->mmio_base = devm_ioremap_resource(&pdev->dev, r);
 180 +       if (IS_ERR(pc->mmio_base))
 181 +               return PTR_ERR(pc->mmio_base);
 182 +
 183 +       pc->clk_main = devm_clk_get(&pdev->dev, "main");
 184 +        if (IS_ERR(pc->clk_main))
 185 +               return PTR_ERR(pc->clk_main);
 186 +
 187 +       pc->clk_top = devm_clk_get(&pdev->dev, "top");
 188 +        if (IS_ERR(pc->clk_top))
 189 +               return PTR_ERR(pc->clk_top);
 190 +
 191 +       pc->clk_pwm[0] = devm_clk_get(&pdev->dev, "pwm1");
 192 +        if (IS_ERR(pc->clk_pwm[0]))
 193 +               return PTR_ERR(pc->clk_pwm[0]);
 194 +
 195 +       pc->clk_pwm[1] = devm_clk_get(&pdev->dev, "pwm2");
 196 +        if (IS_ERR(pc->clk_pwm[1]))
 197 +               return PTR_ERR(pc->clk_pwm[1]);
 198 +
 199 +       pc->clk_pwm[2] = devm_clk_get(&pdev->dev, "pwm3");
 200 +        if (IS_ERR(pc->clk_pwm[2]))
 201 +               return PTR_ERR(pc->clk_pwm[2]);
 202 +
 203 +       pc->clk_pwm[3] = devm_clk_get(&pdev->dev, "pwm4");
 204 +        if (IS_ERR(pc->clk_pwm[3]))
 205 +               return PTR_ERR(pc->clk_pwm[3]);
 206 +
 207 +       pc->clk_pwm[4] = devm_clk_get(&pdev->dev, "pwm5");
 208 +        if (IS_ERR(pc->clk_pwm[4]))
 209 +               return PTR_ERR(pc->clk_pwm[4]);
 210 +
 211 +       ret = clk_prepare(pc->clk_top);
 212 +        if (ret < 0)
 213 +               return ret;
 214 +
 215 +       ret = clk_prepare(pc->clk_main);
 216 +       if (ret < 0)
 217 +               goto disable_clk_top;
 218 +
 219 +       platform_set_drvdata(pdev, pc);
 220 +
 221 +       pc->chip.dev = &pdev->dev;
 222 +       pc->chip.ops = &mtk_pwm_ops;
 223 +       pc->chip.base = -1;
 224 +       pc->chip.npwm = NUM_PWM;
 225 +
 226 +       ret = pwmchip_add(&pc->chip);
 227 +       if (ret < 0) {
 228 +               dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
 229 +               goto disable_clk_main;
 230 +       }
 231 +
 232 +       return 0;
 233 +
 234 +disable_clk_main:
 235 +       clk_unprepare(pc->clk_main);
 236 +disable_clk_top:
 237 +       clk_unprepare(pc->clk_top);
 238 +
 239 +       return ret;
 240 +}
 241 +
 242 +static int mtk_pwm_remove(struct platform_device *pdev)
 243 +{
 244 +       struct mtk_pwm_chip *pc = platform_get_drvdata(pdev);
 245 +       int i;
 246 +
 247 +       for (i = 0; i < NUM_PWM; i++)
 248 +               pwm_disable(&pc->chip.pwms[i]);
 249 +
 250 +       return pwmchip_remove(&pc->chip);
 251 +}
 252 +
 253 +static const struct of_device_id mtk_pwm_of_match[] = {
 254 +       { .compatible = "mediatek,mt7623-pwm" },
 255 +       { }
 256 +};
 257 +
 258 +MODULE_DEVICE_TABLE(of, mtk_pwm_of_match);
 259 +
 260 +static struct platform_driver mtk_pwm_driver = {
 261 +       .driver = {
 262 +               .name = "mtk-pwm",
 263 +               .owner = THIS_MODULE,
 264 +               .of_match_table = mtk_pwm_of_match,
 265 +       },
 266 +       .probe = mtk_pwm_probe,
 267 +       .remove = mtk_pwm_remove,
 268 +};
 269 +
 270 +module_platform_driver(mtk_pwm_driver);
 271 +
 272 +MODULE_LICENSE("GPL");
 273 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
 274 +MODULE_ALIAS("platform:mtk-pwm");