target/linux/mediatek/patches-4.9/0025-PCI-mediatek-add-support-for-PCIe-found-on-MT7623-MT.patch

   1 From 8ab1d4e0a9a68e03f472dee1c036a01d0198c20c Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Tue, 5 Jan 2016 20:20:04 +0100
   4 Subject: [PATCH 025/102] PCI: mediatek: add support for PCIe found on
   5  MT7623/MT2701
   6
   7 Add PCIe controller support on MediaTek MT2701/MT7623. The driver supports
   8 a single Root complex (RC) with 3 Root Ports. The SoCs supports a Gen2
   9 1-lan Link on each port.
  10
  11 Signed-off-by: John Crispin <blogic@openwrt.org>
  12 ---
  13  arch/arm/mach-mediatek/Kconfig   |    1 +
  14  drivers/pci/host/Kconfig         |   11 +
  15  drivers/pci/host/Makefile        |    1 +
  16  drivers/pci/host/pcie-mediatek.c |  641 ++++++++++++++++++++++++++++++++++++++
  17  4 files changed, 654 insertions(+)
  18  create mode 100644 drivers/pci/host/pcie-mediatek.c
  19
  20 --- a/arch/arm/mach-mediatek/Kconfig
  21 +++ b/arch/arm/mach-mediatek/Kconfig
  22 @@ -29,6 +29,7 @@ config MACH_MT6592
  23  config MACH_MT7623
  24         bool "MediaTek MT7623 SoCs support"
  25         default ARCH_MEDIATEK
  26 +       select MIGHT_HAVE_PCI
  27
  28  config MACH_MT8127
  29         bool "MediaTek MT8127 SoCs support"
  30 --- a/drivers/pci/host/Kconfig
  31 +++ b/drivers/pci/host/Kconfig
  32 @@ -301,4 +301,15 @@ config VMD
  33           To compile this driver as a module, choose M here: the
  34           module will be called vmd.
  35
  36 +config PCIE_MTK
  37 +       bool "Mediatek PCIe Controller"
  38 +       depends on MACH_MT2701 || MACH_MT7623
  39 +       depends on OF
  40 +       depends on PCI
  41 +       help
  42 +         Say Y here if you want to enable PCI controller support on Mediatek MT7623.
  43 +         MT7623 PCIe supports single Root complex (RC) with 3 Root Ports.
  44 +         Each port supports a Gen2 1-lan Link.
  45 +         PCIe include one Host/PCI bridge and 3 PCIe MAC.
  46 +
  47  endmenu
  48 --- a/drivers/pci/host/Makefile
  49 +++ b/drivers/pci/host/Makefile
  50 @@ -33,3 +33,4 @@ obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-arm
  51  obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
  52  obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
  53  obj-$(CONFIG_VMD) += vmd.o
  54 +obj-$(CONFIG_PCIE_MTK) += pcie-mediatek.o
  55 --- /dev/null
  56 +++ b/drivers/pci/host/pcie-mediatek.c
  57 @@ -0,0 +1,641 @@
  58 +/*
  59 + *  Mediatek MT2701/MT7623 SoC PCIE support
  60 + *
  61 + *  Copyright (C) 2015 Mediatek
  62 + *  Copyright (C) 2015 Ziv Huang <ziv.huang@mediatek.com>
  63 + *  Copyright (C) 2015 John Crispin <blogic@openwrt.org>
  64 + *
  65 + *  This program is free software; you can redistribute it and/or modify it
  66 + *  under the terms of the GNU General Public License version 2 as published
  67 + *  by the Free Software Foundation.
  68 + */
  69 +
  70 +#include <linux/kernel.h>
  71 +#include <linux/pci.h>
  72 +#include <linux/ioport.h>
  73 +#include <linux/interrupt.h>
  74 +#include <linux/spinlock.h>
  75 +#include <linux/init.h>
  76 +#include <linux/device.h>
  77 +#include <linux/io.h>
  78 +#include <linux/delay.h>
  79 +#include <asm/irq.h>
  80 +#include <asm/mach/pci.h>
  81 +#include <linux/module.h>
  82 +#include <linux/of.h>
  83 +#include <linux/of_address.h>
  84 +#include <linux/of_pci.h>
  85 +#include <linux/of_platform.h>
  86 +#include <linux/of_irq.h>
  87 +#include <linux/reset.h>
  88 +#include <linux/platform_device.h>
  89 +#include <linux/regulator/consumer.h>
  90 +#include <linux/pm_runtime.h>
  91 +#include <linux/clk.h>
  92 +#include <linux/regmap.h>
  93 +#include <linux/mfd/syscon.h>
  94 +
  95 +#define MEMORY_BASE                    0x80000000
  96 +
  97 +/* PCIE Registers */
  98 +#define PCICFG                         0x00
  99 +#define PCIINT                         0x08
 100 +#define PCIENA                         0x0c
 101 +#define CFGADDR                                0x20
 102 +#define CFGDATA                                0x24
 103 +#define MEMBASE                                0x28
 104 +#define IOBASE                         0x2c
 105 +
 106 +/* per Port Registers */
 107 +#define BAR0SETUP                      0x10
 108 +#define IMBASEBAR0                     0x18
 109 +#define PCIE_CLASS                     0x34
 110 +#define PCIE_SISTAT                    0x50
 111 +
 112 +#define MTK_PCIE_HIGH_PERF             BIT(14)
 113 +#define PCIEP0_BASE                    0x2000
 114 +#define PCIEP1_BASE                    0x3000
 115 +#define PCIEP2_BASE                    0x4000
 116 +
 117 +#define PHY_P0_CTL                     0x9000
 118 +#define PHY_P1_CTL                     0xa000
 119 +#define PHY_P2_CTL                     0x4000
 120 +
 121 +#define RSTCTL_PCIE0_RST               BIT(24)
 122 +#define RSTCTL_PCIE1_RST               BIT(25)
 123 +#define RSTCTL_PCIE2_RST               BIT(26)
 124 +
 125 +#define HIFSYS_SYSCFG1                 0x14
 126 +#define HIFSYS_SYSCFG1_PHY2_MASK       (0x3 << 20)
 127 +
 128 +#define MTK_PHY_CLK                    0xb00
 129 +#define MTK_PHY_CLKDRV_OFFSET          BIT(2)
 130 +#define MTK_PHY_CLKDRV_OFFSET_MASK     0xe
 131 +#define MTK_PHY_PLL                    0xb04
 132 +#define MTK_PHY_CLKDRV_AMP             BIT(30)
 133 +#define MTK_PHY_CLKDRV_AMP_MASK                0xe0000000
 134 +#define MTK_PHY_REFCLK_SEL             0xc00
 135 +#define MTK_PHY_XTAL_EXT_EN            (BIT(17) | BIT(12))
 136 +#define MTK_PHY_XTAL_EXT_EN_MASK       0x33000
 137 +#define MTK_PHY_PLL_BC                 0xc08
 138 +#define MTK_PHY_PLL_BC_PE2H            0xc0
 139 +#define MTK_PHY_PLL_BC_PE2H_MASK       0x380000
 140 +#define MTK_PHY_PLL_IC                 0xc0c
 141 +#define MTK_PHY_PLL_IC_BR_PE2H         BIT(28)
 142 +#define MTK_PHY_PLL_IC_BR_PE2H_MASK    0x30000000
 143 +#define MTK_PHY_PLL_IC_PE2H            BIT(12)
 144 +#define MTK_PHY_PLL_IC_PE2H_MASK       0xf000
 145 +#define MTK_PHY_PLL_IR                 0xc10
 146 +#define MTK_PHY_PLL_IR_PE2H            BIT(17)
 147 +#define MTK_PHY_PLL_IR_PE2H_MASK       0xf0000
 148 +#define MTK_PHY_PLL_BP                 0xc14
 149 +#define MTK_PHY_PLL_BP_PE2H            (BIT(19) | BIT(17))
 150 +#define MTK_PHY_PLL_BP_PE2H_MASK       0xf0000
 151 +#define MTK_PHY_SSC_DELTA1             0xc3c
 152 +#define MTK_PHY_SSC_DELTA1_PE2H                (0x3c << 16)
 153 +#define MTK_PHY_SSC_DELTA1_PE2H_MASK   0xffff0000
 154 +#define MTK_PHY_SSC_DELTA              0xc48
 155 +#define MTK_PHY_SSC_DELTA_PE2H         0x36
 156 +#define MTK_PHY_SSC_DELTA_PE2H_MASK    0xffff
 157 +
 158 +#define MAX_PORT_NUM                   3
 159 +
 160 +struct mtk_pcie_port {
 161 +       int id;
 162 +       int enable;
 163 +       int irq;
 164 +       u32 link;
 165 +       void __iomem *phy_base;
 166 +       struct reset_control *rstc;
 167 +};
 168 +
 169 +#define mtk_foreach_port(pcie, p)                      \
 170 +               for ((p) = pcie->port;  \
 171 +                    (p) != &pcie->port[MAX_PORT_NUM]; (p)++)
 172 +
 173 +struct mtk_pcie {
 174 +       struct device *dev;
 175 +       void __iomem *pcie_base;
 176 +       struct regmap *hifsys;
 177 +
 178 +       struct resource io;
 179 +       struct resource pio;
 180 +       struct resource mem;
 181 +       struct resource prefetch;
 182 +       struct resource busn;
 183 +
 184 +       u32 io_bus_addr;
 185 +       u32 mem_bus_addr;
 186 +
 187 +       struct clk *clk;
 188 +
 189 +       struct mtk_pcie_port port[MAX_PORT_NUM];
 190 +       int pcie_card_link;
 191 +};
 192 +
 193 +static struct mtk_pcie_port_data {
 194 +       u32 base;
 195 +       u32 perst_n;
 196 +       u32 interrupt_en;
 197 +} mtk_pcie_port_data[MAX_PORT_NUM] = {
 198 +       { PCIEP0_BASE, BIT(1), BIT(20) },
 199 +       { PCIEP1_BASE, BIT(2), BIT(21) },
 200 +       { PCIEP2_BASE, BIT(3), BIT(22) },
 201 +};
 202 +
 203 +static const struct mtk_phy_init {
 204 +       uint32_t reg;
 205 +       uint32_t mask;
 206 +       uint32_t val;
 207 +} mtk_phy_init[] = {
 208 +       { MTK_PHY_REFCLK_SEL, MTK_PHY_XTAL_EXT_EN_MASK, MTK_PHY_XTAL_EXT_EN },
 209 +       { MTK_PHY_PLL, MTK_PHY_CLKDRV_AMP_MASK, MTK_PHY_CLKDRV_AMP },
 210 +       { MTK_PHY_CLK, MTK_PHY_CLKDRV_OFFSET_MASK, MTK_PHY_CLKDRV_OFFSET },
 211 +       { MTK_PHY_SSC_DELTA1, MTK_PHY_SSC_DELTA1_PE2H_MASK, MTK_PHY_SSC_DELTA1_PE2H },
 212 +       { MTK_PHY_SSC_DELTA, MTK_PHY_SSC_DELTA_PE2H_MASK, MTK_PHY_SSC_DELTA_PE2H },
 213 +       { MTK_PHY_PLL_IC, MTK_PHY_PLL_IC_BR_PE2H_MASK, MTK_PHY_PLL_IC_BR_PE2H },
 214 +       { MTK_PHY_PLL_BC, MTK_PHY_PLL_BC_PE2H_MASK, MTK_PHY_PLL_BC_PE2H },
 215 +       { MTK_PHY_PLL_IR, MTK_PHY_PLL_IR_PE2H_MASK, MTK_PHY_PLL_IR_PE2H },
 216 +       { MTK_PHY_PLL_IC, MTK_PHY_PLL_IC_PE2H_MASK, MTK_PHY_PLL_IC_PE2H },
 217 +       { MTK_PHY_PLL_BP, MTK_PHY_PLL_BP_PE2H_MASK, MTK_PHY_PLL_BP_PE2H },
 218 +};
 219 +
 220 +static struct mtk_pcie *sys_to_pcie(struct pci_sys_data *sys)
 221 +{
 222 +       return sys->private_data;
 223 +}
 224 +
 225 +static void pcie_w32(struct mtk_pcie *pcie, u32 val, unsigned reg)
 226 +{
 227 +       iowrite32(val, pcie->pcie_base + reg);
 228 +}
 229 +
 230 +static u32 pcie_r32(struct mtk_pcie *pcie, unsigned reg)
 231 +{
 232 +       return ioread32(pcie->pcie_base + reg);
 233 +}
 234 +
 235 +static void pcie_m32(struct mtk_pcie *pcie, u32 mask, u32 val, unsigned reg)
 236 +{
 237 +       u32 v = pcie_r32(pcie, reg);
 238 +
 239 +       v &= mask;
 240 +       v |= val;
 241 +       pcie_w32(pcie, v, reg);
 242 +}
 243 +
 244 +static int pcie_config_read(struct pci_bus *bus, unsigned int devfn, int where,
 245 +                           int size, u32 *val)
 246 +{
 247 +       struct mtk_pcie *pcie = sys_to_pcie(bus->sysdata);
 248 +       unsigned int slot = PCI_SLOT(devfn);
 249 +       u8 func = PCI_FUNC(devfn);
 250 +       u32 address;
 251 +       u32 data;
 252 +       u32 num = 0;
 253 +
 254 +       if (bus)
 255 +               num = bus->number;
 256 +
 257 +       address = (((where & 0xf00) >> 8) << 24) |
 258 +                 (num << 16) |
 259 +                 (slot << 11) |
 260 +                 (func << 8) |
 261 +                 (where & 0xfc);
 262 +
 263 +       pcie_w32(pcie, address, CFGADDR);
 264 +       data = pcie_r32(pcie, CFGDATA);
 265 +
 266 +       switch (size) {
 267 +       case 1:
 268 +               *val = (data >> ((where & 3) << 3)) & 0xff;
 269 +               break;
 270 +       case 2:
 271 +               *val = (data >> ((where & 3) << 3)) & 0xffff;
 272 +               break;
 273 +       case 4:
 274 +               *val = data;
 275 +               break;
 276 +       }
 277 +
 278 +       return PCIBIOS_SUCCESSFUL;
 279 +}
 280 +
 281 +static int pcie_config_write(struct pci_bus *bus, unsigned int devfn, int where,
 282 +                            int size, u32 val)
 283 +{
 284 +       struct mtk_pcie *pcie = sys_to_pcie(bus->sysdata);
 285 +       unsigned int slot = PCI_SLOT(devfn);
 286 +       u8 func = PCI_FUNC(devfn);
 287 +       u32 address;
 288 +       u32 data;
 289 +       u32 num = 0;
 290 +
 291 +       if (bus)
 292 +               num = bus->number;
 293 +
 294 +       address = (((where & 0xf00) >> 8) << 24) |
 295 +                 (num << 16) | (slot << 11) | (func << 8) | (where & 0xfc);
 296 +       pcie_w32(pcie, address, CFGADDR);
 297 +       data = pcie_r32(pcie, CFGDATA);
 298 +
 299 +       switch (size) {
 300 +       case 1:
 301 +               data = (data & ~(0xff << ((where & 3) << 3))) |
 302 +                      (val << ((where & 3) << 3));
 303 +               break;
 304 +       case 2:
 305 +               data = (data & ~(0xffff << ((where & 3) << 3))) |
 306 +                      (val << ((where & 3) << 3));
 307 +               break;
 308 +       case 4:
 309 +               data = val;
 310 +               break;
 311 +       }
 312 +       pcie_w32(pcie, data, CFGDATA);
 313 +
 314 +       return PCIBIOS_SUCCESSFUL;
 315 +}
 316 +
 317 +static struct pci_ops mtk_pcie_ops = {
 318 +       .read   = pcie_config_read,
 319 +       .write  = pcie_config_write,
 320 +};
 321 +
 322 +static int __init mtk_pcie_setup(int nr, struct pci_sys_data *sys)
 323 +{
 324 +       struct mtk_pcie *pcie = sys_to_pcie(sys);
 325 +
 326 +       request_resource(&ioport_resource, &pcie->pio);
 327 +       request_resource(&iomem_resource, &pcie->mem);
 328 +
 329 +       pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
 330 +       pci_add_resource_offset(&sys->resources, &pcie->pio, sys->io_offset);
 331 +       pci_add_resource(&sys->resources, &pcie->busn);
 332 +
 333 +       return 1;
 334 +}
 335 +
 336 +static struct pci_bus * __init mtk_pcie_scan_bus(int nr,
 337 +                                               struct pci_sys_data *sys)
 338 +{
 339 +       struct mtk_pcie *pcie = sys_to_pcie(sys);
 340 +       struct pci_bus *bus;
 341 +
 342 +       bus = pci_create_root_bus(pcie->dev, sys->busnr, &mtk_pcie_ops, sys,
 343 +                                 &sys->resources);
 344 +       if (!bus)
 345 +               return NULL;
 346 +
 347 +       pci_scan_child_bus(bus);
 348 +
 349 +       return bus;
 350 +}
 351 +
 352 +static int __init mtk_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 353 +{
 354 +       struct mtk_pcie *pcie = sys_to_pcie(dev->bus->sysdata);
 355 +       struct mtk_pcie_port *port;
 356 +       int irq = -1;
 357 +
 358 +       mtk_foreach_port(pcie, port)
 359 +               if (port->id == slot)
 360 +                       irq = port->irq;
 361 +
 362 +       return irq;
 363 +}
 364 +
 365 +static void mtk_pcie_configure_phy(struct mtk_pcie *pcie,
 366 +                                  struct mtk_pcie_port *port)
 367 +{
 368 +       int i;
 369 +
 370 +       for (i = 0; i < ARRAY_SIZE(mtk_phy_init); i++) {
 371 +               void __iomem *phy_addr = port->phy_base + mtk_phy_init[i].reg;
 372 +               u32 val = ioread32(phy_addr);
 373 +
 374 +               val &= ~mtk_phy_init[i].mask;
 375 +               val |= mtk_phy_init[i].val;
 376 +               iowrite32(val, phy_addr);
 377 +       }
 378 +       usleep_range(5000, 6000);
 379 +}
 380 +
 381 +static void mtk_pcie_configure_rc(struct mtk_pcie *pcie,
 382 +                                 struct mtk_pcie_port *port,
 383 +                                 struct pci_bus *bus)
 384 +{
 385 +       u32 val = 0;
 386 +
 387 +       pcie_config_write(bus,
 388 +                         port->id << 3,
 389 +                         PCI_BASE_ADDRESS_0, 4, MEMORY_BASE);
 390 +
 391 +       pcie_config_read(bus,
 392 +                        port->id << 3, PCI_BASE_ADDRESS_0, 4, &val);
 393 +
 394 +       /* Configure RC Credit */
 395 +       pcie_config_read(bus, port->id << 3, 0x73c, 4, &val);
 396 +       val &= ~(0x9fff) << 16;
 397 +       val |= 0x806c << 16;
 398 +       pcie_config_write(bus, port->id << 3, 0x73c, 4, val);
 399 +
 400 +       /* Configure RC FTS number */
 401 +       pcie_config_read(bus, port->id << 3, 0x70c, 4, &val);
 402 +       val &= ~(0xff3) << 8;
 403 +       val |= 0x50 << 8;
 404 +       pcie_config_write(bus, port->id << 3, 0x70c, 4, val);
 405 +}
 406 +
 407 +static int mtk_pcie_preinit(struct mtk_pcie *pcie)
 408 +{
 409 +       struct mtk_pcie_port *port;
 410 +       u32 val = 0;
 411 +       struct pci_bus bus;
 412 +       struct pci_sys_data sys;
 413 +
 414 +       memset(&bus, 0, sizeof(bus));
 415 +       memset(&sys, 0, sizeof(sys));
 416 +       bus.sysdata = (void *)&sys;
 417 +       sys.private_data = (void *)pcie;
 418 +
 419 +       pcibios_min_io = 0;
 420 +       pcibios_min_mem = 0;
 421 +
 422 +       /* The PHY on Port 2 is shared with USB */
 423 +       if (pcie->port[2].enable)
 424 +               regmap_update_bits(pcie->hifsys, HIFSYS_SYSCFG1,
 425 +                                  HIFSYS_SYSCFG1_PHY2_MASK, 0x0);
 426 +
 427 +       /* PCIe RC Reset */
 428 +       mtk_foreach_port(pcie, port)
 429 +               if (port->enable)
 430 +                       reset_control_assert(port->rstc);
 431 +       usleep_range(1000, 2000);
 432 +       mtk_foreach_port(pcie, port)
 433 +               if (port->enable)
 434 +                       reset_control_deassert(port->rstc);
 435 +       usleep_range(1000, 2000);
 436 +
 437 +       /* Configure PCIe PHY */
 438 +       mtk_foreach_port(pcie, port)
 439 +               if (port->enable)
 440 +                       mtk_pcie_configure_phy(pcie, port);
 441 +
 442 +       /* PCIe EP reset */
 443 +       val = 0;
 444 +       mtk_foreach_port(pcie, port)
 445 +               if (port->enable)
 446 +                       val |= mtk_pcie_port_data[port->id].perst_n;
 447 +       pcie_w32(pcie, pcie_r32(pcie, PCICFG) | val, PCICFG);
 448 +       usleep_range(1000, 2000);
 449 +       pcie_w32(pcie, pcie_r32(pcie, PCICFG) & ~val, PCICFG);
 450 +       usleep_range(1000, 2000);
 451 +       msleep(100);
 452 +
 453 +       /* check the link status */
 454 +       val = 0;
 455 +       mtk_foreach_port(pcie, port) {
 456 +               if (port->enable) {
 457 +                       u32 base = mtk_pcie_port_data[port->id].base;
 458 +
 459 +                       if ((pcie_r32(pcie, base + PCIE_SISTAT) & 0x1))
 460 +                               port->link = 1;
 461 +                       else
 462 +                               reset_control_assert(port->rstc);
 463 +               }
 464 +       }
 465 +
 466 +       mtk_foreach_port(pcie, port)
 467 +               if (port->link)
 468 +                       pcie->pcie_card_link++;
 469 +
 470 +       if (!pcie->pcie_card_link)
 471 +               return -ENODEV;
 472 +
 473 +       pcie_w32(pcie, pcie->mem_bus_addr, MEMBASE);
 474 +       pcie_w32(pcie, pcie->io_bus_addr, IOBASE);
 475 +
 476 +       mtk_foreach_port(pcie, port) {
 477 +               if (port->link) {
 478 +                       u32 base = mtk_pcie_port_data[port->id].base;
 479 +                       u32 inte = mtk_pcie_port_data[port->id].interrupt_en;
 480 +
 481 +                       pcie_m32(pcie, 0, inte, PCIENA);
 482 +                       pcie_w32(pcie, 0x7fff0001, base + BAR0SETUP);
 483 +                       pcie_w32(pcie, MEMORY_BASE, base + IMBASEBAR0);
 484 +                       pcie_w32(pcie, 0x06040001, base + PCIE_CLASS);
 485 +               }
 486 +       }
 487 +
 488 +       mtk_foreach_port(pcie, port)
 489 +               if (port->link)
 490 +                       mtk_pcie_configure_rc(pcie, port, &bus);
 491 +
 492 +       return 0;
 493 +}
 494 +
 495 +static int mtk_pcie_parse_dt(struct mtk_pcie *pcie)
 496 +{
 497 +       struct device_node *np = pcie->dev->of_node, *port;
 498 +       struct of_pci_range_parser parser;
 499 +       struct of_pci_range range;
 500 +       struct resource res;
 501 +       int err;
 502 +
 503 +       pcie->hifsys = syscon_regmap_lookup_by_phandle(np, "mediatek,hifsys");
 504 +       if (IS_ERR(pcie->hifsys)) {
 505 +               dev_err(pcie->dev, "missing \"mediatek,hifsys\" phandle\n");
 506 +               return PTR_ERR(pcie->hifsys);
 507 +       }
 508 +
 509 +       if (of_pci_range_parser_init(&parser, np)) {
 510 +               dev_err(pcie->dev, "missing \"ranges\" property\n");
 511 +               return -EINVAL;
 512 +       }
 513 +
 514 +       for_each_of_pci_range(&parser, &range) {
 515 +               err = of_pci_range_to_resource(&range, np, &res);
 516 +               if (err < 0) {
 517 +                       dev_err(pcie->dev, "failed to read resource range\n");
 518 +                       return err;
 519 +               }
 520 +
 521 +               switch (res.flags & IORESOURCE_TYPE_BITS) {
 522 +               case IORESOURCE_IO:
 523 +                       memcpy(&pcie->pio, &res, sizeof(res));
 524 +                       pcie->pio.start = (resource_size_t)range.pci_addr;
 525 +                       pcie->pio.end = (resource_size_t)
 526 +                                       (range.pci_addr + range.size - 1);
 527 +                       pcie->io_bus_addr = (resource_size_t)range.cpu_addr;
 528 +                       break;
 529 +
 530 +               case IORESOURCE_MEM:
 531 +                       if (res.flags & IORESOURCE_PREFETCH) {
 532 +                               memcpy(&pcie->prefetch, &res, sizeof(res));
 533 +                               pcie->prefetch.name = "prefetchable";
 534 +                               pcie->prefetch.start =
 535 +                                       (resource_size_t)range.pci_addr;
 536 +                               pcie->prefetch.end = (resource_size_t)
 537 +                                       (range.pci_addr + range.size - 1);
 538 +                       } else {
 539 +                               memcpy(&pcie->mem, &res, sizeof(res));
 540 +                               pcie->mem.name = "non-prefetchable";
 541 +                               pcie->mem.start = (resource_size_t)
 542 +                                       range.pci_addr;
 543 +                               pcie->prefetch.end = (resource_size_t)
 544 +                                       (range.pci_addr + range.size - 1);
 545 +                               pcie->mem_bus_addr = (resource_size_t)
 546 +                                       range.cpu_addr;
 547 +                       }
 548 +                       break;
 549 +               }
 550 +       }
 551 +
 552 +       err = of_pci_parse_bus_range(np, &pcie->busn);
 553 +       if (err < 0) {
 554 +               dev_err(pcie->dev, "failed to parse ranges property: %d\n",
 555 +                       err);
 556 +               pcie->busn.name = np->name;
 557 +               pcie->busn.start = 0;
 558 +               pcie->busn.end = 0xff;
 559 +               pcie->busn.flags = IORESOURCE_BUS;
 560 +       }
 561 +
 562 +       /* parse root ports */
 563 +       for_each_child_of_node(np, port) {
 564 +               unsigned int index;
 565 +               char rst[] = "pcie0";
 566 +
 567 +               err = of_pci_get_devfn(port);
 568 +               if (err < 0) {
 569 +                       dev_err(pcie->dev, "failed to parse address: %d\n",
 570 +                               err);
 571 +                       return err;
 572 +               }
 573 +
 574 +               index = PCI_SLOT(err);
 575 +               if (index > MAX_PORT_NUM) {
 576 +                       dev_err(pcie->dev, "invalid port number: %d\n", index);
 577 +                       continue;
 578 +               }
 579 +               index--;
 580 +               pcie->port[index].id = index;
 581 +
 582 +               if (!of_device_is_available(port))
 583 +                       continue;
 584 +
 585 +               rst[4] += index;
 586 +               pcie->port[index].rstc = devm_reset_control_get(pcie->dev,
 587 +                                                                  rst);
 588 +               if (!IS_ERR(pcie->port[index].rstc))
 589 +                       pcie->port[index].enable = 1;
 590 +       }
 591 +       return 0;
 592 +}
 593 +
 594 +static int mtk_pcie_get_resources(struct mtk_pcie *pcie)
 595 +{
 596 +       struct platform_device *pdev = to_platform_device(pcie->dev);
 597 +       struct mtk_pcie_port *port;
 598 +       struct resource *res;
 599 +
 600 +       pcie->clk = devm_clk_get(&pdev->dev, "pcie");
 601 +       if (IS_ERR(pcie->clk)) {
 602 +               dev_err(&pdev->dev, "Failed to get pcie clk\n");
 603 +               return PTR_ERR(pcie->clk);
 604 +       }
 605 +
 606 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 607 +       pcie->pcie_base = devm_ioremap_resource(&pdev->dev, res);
 608 +       if (IS_ERR(pcie->pcie_base)) {
 609 +               dev_err(&pdev->dev, "Failed to get pcie range\n");
 610 +               return PTR_ERR(pcie->pcie_base);
 611 +       }
 612 +
 613 +       mtk_foreach_port(pcie, port) {
 614 +               if (!port->enable)
 615 +                       continue;
 616 +               res = platform_get_resource(pdev, IORESOURCE_MEM, port->id + 1);
 617 +               port->phy_base = devm_ioremap_resource(&pdev->dev, res);
 618 +               if (IS_ERR(port->phy_base)) {
 619 +                       dev_err(&pdev->dev, "Failed to get pcie phy%d range %p\n",
 620 +                               port->id, port->phy_base);
 621 +                       return PTR_ERR(port->phy_base);
 622 +               }
 623 +               port->irq = platform_get_irq(pdev, port->id);
 624 +       }
 625 +
 626 +       return clk_prepare_enable(pcie->clk);
 627 +}
 628 +
 629 +static int mtk_pcie_probe(struct platform_device *pdev)
 630 +{
 631 +       struct mtk_pcie *pcie;
 632 +       struct hw_pci hw;
 633 +       int ret;
 634 +
 635 +       pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
 636 +       if (!pcie)
 637 +               return -ENOMEM;
 638 +
 639 +       pcie->dev = &pdev->dev;
 640 +       ret = mtk_pcie_parse_dt(pcie);
 641 +       if (ret < 0)
 642 +               return ret;
 643 +
 644 +       pm_runtime_enable(&pdev->dev);
 645 +       pm_runtime_get_sync(&pdev->dev);
 646 +
 647 +       ret = mtk_pcie_get_resources(pcie);
 648 +       if (ret < 0) {
 649 +               dev_err(&pdev->dev, "failed to request resources: %d\n", ret);
 650 +               goto err_out;
 651 +       }
 652 +
 653 +       ret = mtk_pcie_preinit(pcie);
 654 +       if (ret)
 655 +               return ret;
 656 +
 657 +       memset(&hw, 0, sizeof(hw));
 658 +       hw.nr_controllers = 1;
 659 +       hw.private_data = (void **)&pcie;
 660 +       hw.setup = mtk_pcie_setup;
 661 +       hw.map_irq = mtk_pcie_map_irq;
 662 +       hw.scan = mtk_pcie_scan_bus;
 663 +
 664 +       pci_common_init_dev(pcie->dev, &hw);
 665 +       platform_set_drvdata(pdev, pcie);
 666 +
 667 +       return 0;
 668 +
 669 +err_out:
 670 +       clk_disable_unprepare(pcie->clk);
 671 +       pm_runtime_put_sync(&pdev->dev);
 672 +       pm_runtime_disable(&pdev->dev);
 673 +
 674 +       return ret;
 675 +}
 676 +
 677 +static const struct of_device_id mtk_pcie_ids[] = {
 678 +       { .compatible = "mediatek,mt2701-pcie" },
 679 +       { .compatible = "mediatek,mt7623-pcie" },
 680 +       {},
 681 +};
 682 +MODULE_DEVICE_TABLE(of, mtk_pcie_ids);
 683 +
 684 +static struct platform_driver mtk_pcie_driver = {
 685 +       .probe = mtk_pcie_probe,
 686 +       .driver = {
 687 +               .name = "mediatek-pcie",
 688 +               .owner = THIS_MODULE,
 689 +               .of_match_table = of_match_ptr(mtk_pcie_ids),
 690 +       },
 691 +};
 692 +
 693 +static int __init mtk_pcie_init(void)
 694 +{
 695 +       return platform_driver_register(&mtk_pcie_driver);
 696 +}
 697 +
 698 +module_init(mtk_pcie_init);