target/linux/mediatek/patches-4.9/0071-pwm-add-pwm-mediatek.patch

   1 From 6f5941c93bdf7649f392f1263b9068d360ceab4d Mon Sep 17 00:00:00 2001
   2 From: John Crispin <john@phrozen.org>
   3 Date: Fri, 6 May 2016 02:55:48 +0200
   4 Subject: [PATCH 071/102] pwm: add pwm-mediatek
   5
   6 Signed-off-by: John Crispin <john@phrozen.org>
   7 ---
   8  arch/arm/boot/dts/mt7623-evb.dts |   17 +++
   9  arch/arm/boot/dts/mt7623.dtsi    |   22 ++++
  10  drivers/pwm/Kconfig              |    9 ++
  11  drivers/pwm/Makefile             |    1 +
  12  drivers/pwm/pwm-mediatek.c       |  230 ++++++++++++++++++++++++++++++++++++++
  13  5 files changed, 279 insertions(+)
  14  create mode 100644 drivers/pwm/pwm-mediatek.c
  15
  16 --- a/drivers/pwm/Kconfig
  17 +++ b/drivers/pwm/Kconfig
  18 @@ -282,6 +282,15 @@ config PWM_MTK_DISP
  19           To compile this driver as a module, choose M here: the module
  20           will be called pwm-mtk-disp.
  21
  22 +config PWM_MEDIATEK
  23 +       tristate "MediaTek PWM support"
  24 +       depends on ARCH_MEDIATEK || COMPILE_TEST
  25 +       help
  26 +         Generic PWM framework driver for Mediatek ARM SoC.
  27 +
  28 +         To compile this driver as a module, choose M here: the module
  29 +         will be called pwm-mxs.
  30 +
  31  config PWM_MXS
  32         tristate "Freescale MXS PWM support"
  33         depends on ARCH_MXS && OF
  34 --- a/drivers/pwm/Makefile
  35 +++ b/drivers/pwm/Makefile
  36 @@ -25,6 +25,7 @@ obj-$(CONFIG_PWM_LPSS)                += pwm-lpss.o
  37  obj-$(CONFIG_PWM_LPSS_PCI)     += pwm-lpss-pci.o
  38  obj-$(CONFIG_PWM_LPSS_PLATFORM)        += pwm-lpss-platform.o
  39  obj-$(CONFIG_PWM_MESON)                += pwm-meson.o
  40 +obj-$(CONFIG_PWM_MEDIATEK)     += pwm-mediatek.o
  41  obj-$(CONFIG_PWM_MTK_DISP)     += pwm-mtk-disp.o
  42  obj-$(CONFIG_PWM_MXS)          += pwm-mxs.o
  43  obj-$(CONFIG_PWM_OMAP_DMTIMER) += pwm-omap-dmtimer.o
  44 --- /dev/null
  45 +++ b/drivers/pwm/pwm-mediatek.c
  46 @@ -0,0 +1,230 @@
  47 +/*
  48 + * Mediatek Pulse Width Modulator driver
  49 + *
  50 + * Copyright (C) 2015 John Crispin <blogic@openwrt.org>
  51 + *
  52 + * This file is licensed under the terms of the GNU General Public
  53 + * License version 2. This program is licensed "as is" without any
  54 + * warranty of any kind, whether express or implied.
  55 + */
  56 +
  57 +#include <linux/err.h>
  58 +#include <linux/io.h>
  59 +#include <linux/ioport.h>
  60 +#include <linux/kernel.h>
  61 +#include <linux/module.h>
  62 +#include <linux/clk.h>
  63 +#include <linux/of.h>
  64 +#include <linux/platform_device.h>
  65 +#include <linux/pwm.h>
  66 +#include <linux/slab.h>
  67 +#include <linux/types.h>
  68 +
  69 +#define NUM_PWM                5
  70 +
  71 +/* PWM registers and bits definitions */
  72 +#define PWMCON                 0x00
  73 +#define PWMHDUR                        0x04
  74 +#define PWMLDUR                        0x08
  75 +#define PWMGDUR                        0x0c
  76 +#define PWMWAVENUM             0x28
  77 +#define PWMDWIDTH              0x2c
  78 +#define PWMTHRES               0x30
  79 +
  80 +/**
  81 + * struct mtk_pwm_chip - struct representing pwm chip
  82 + *
  83 + * @mmio_base: base address of pwm chip
  84 + * @chip: linux pwm chip representation
  85 + */
  86 +struct mtk_pwm_chip {
  87 +       void __iomem *mmio_base;
  88 +       struct pwm_chip chip;
  89 +       struct clk *clk_top;
  90 +       struct clk *clk_main;
  91 +       struct clk *clk_pwm[NUM_PWM];
  92 +};
  93 +
  94 +static inline struct mtk_pwm_chip *to_mtk_pwm_chip(struct pwm_chip *chip)
  95 +{
  96 +       return container_of(chip, struct mtk_pwm_chip, chip);
  97 +}
  98 +
  99 +static inline u32 mtk_pwm_readl(struct mtk_pwm_chip *chip, unsigned int num,
 100 +                                 unsigned long offset)
 101 +{
 102 +       return ioread32(chip->mmio_base + 0x10 + (num * 0x40) + offset);
 103 +}
 104 +
 105 +static inline void mtk_pwm_writel(struct mtk_pwm_chip *chip,
 106 +                                   unsigned int num, unsigned long offset,
 107 +                                   unsigned long val)
 108 +{
 109 +       iowrite32(val, chip->mmio_base + 0x10 + (num * 0x40) + offset);
 110 +}
 111 +
 112 +static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 113 +                           int duty_ns, int period_ns)
 114 +{
 115 +       struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
 116 +       u32 resolution = 100 / 4;
 117 +       u32 clkdiv = 0;
 118 +
 119 +       resolution = 1000000000 / (clk_get_rate(pc->clk_pwm[pwm->hwpwm]));
 120 +
 121 +       while (period_ns / resolution  > 8191) {
 122 +               clkdiv++;
 123 +               resolution *= 2;
 124 +       }
 125 +
 126 +       if (clkdiv > 7)
 127 +               return -1;
 128 +
 129 +       mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | BIT(3) | clkdiv);
 130 +       mtk_pwm_writel(pc, pwm->hwpwm, PWMDWIDTH, period_ns / resolution);
 131 +       mtk_pwm_writel(pc, pwm->hwpwm, PWMTHRES, duty_ns / resolution);
 132 +       return 0;
 133 +}
 134 +
 135 +static int mtk_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 136 +{
 137 +       struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
 138 +       u32 val;
 139 +       int ret;
 140 +
 141 +       ret = clk_prepare(pc->clk_pwm[pwm->hwpwm]);
 142 +       if (ret < 0)
 143 +               return ret;
 144 +
 145 +       val = ioread32(pc->mmio_base);
 146 +       val |= BIT(pwm->hwpwm);
 147 +       iowrite32(val, pc->mmio_base);
 148 +
 149 +       return 0;
 150 +}
 151 +
 152 +static void mtk_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 153 +{
 154 +       struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
 155 +       u32 val;
 156 +
 157 +       val = ioread32(pc->mmio_base);
 158 +       val &= ~BIT(pwm->hwpwm);
 159 +       iowrite32(val, pc->mmio_base);
 160 +        clk_unprepare(pc->clk_pwm[pwm->hwpwm]);
 161 +}
 162 +
 163 +static const struct pwm_ops mtk_pwm_ops = {
 164 +       .config = mtk_pwm_config,
 165 +       .enable = mtk_pwm_enable,
 166 +       .disable = mtk_pwm_disable,
 167 +       .owner = THIS_MODULE,
 168 +};
 169 +
 170 +static int mtk_pwm_probe(struct platform_device *pdev)
 171 +{
 172 +       struct mtk_pwm_chip *pc;
 173 +       struct resource *r;
 174 +       int ret;
 175 +
 176 +       pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
 177 +       if (!pc)
 178 +               return -ENOMEM;
 179 +
 180 +       r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 181 +       pc->mmio_base = devm_ioremap_resource(&pdev->dev, r);
 182 +       if (IS_ERR(pc->mmio_base))
 183 +               return PTR_ERR(pc->mmio_base);
 184 +
 185 +       pc->clk_main = devm_clk_get(&pdev->dev, "main");
 186 +        if (IS_ERR(pc->clk_main))
 187 +               return PTR_ERR(pc->clk_main);
 188 +
 189 +       pc->clk_top = devm_clk_get(&pdev->dev, "top");
 190 +        if (IS_ERR(pc->clk_top))
 191 +               return PTR_ERR(pc->clk_top);
 192 +
 193 +       pc->clk_pwm[0] = devm_clk_get(&pdev->dev, "pwm1");
 194 +        if (IS_ERR(pc->clk_pwm[0]))
 195 +               return PTR_ERR(pc->clk_pwm[0]);
 196 +
 197 +       pc->clk_pwm[1] = devm_clk_get(&pdev->dev, "pwm2");
 198 +        if (IS_ERR(pc->clk_pwm[1]))
 199 +               return PTR_ERR(pc->clk_pwm[1]);
 200 +
 201 +       pc->clk_pwm[2] = devm_clk_get(&pdev->dev, "pwm3");
 202 +        if (IS_ERR(pc->clk_pwm[2]))
 203 +               return PTR_ERR(pc->clk_pwm[2]);
 204 +
 205 +       pc->clk_pwm[3] = devm_clk_get(&pdev->dev, "pwm4");
 206 +        if (IS_ERR(pc->clk_pwm[3]))
 207 +               return PTR_ERR(pc->clk_pwm[3]);
 208 +
 209 +       pc->clk_pwm[4] = devm_clk_get(&pdev->dev, "pwm5");
 210 +        if (IS_ERR(pc->clk_pwm[4]))
 211 +               return PTR_ERR(pc->clk_pwm[4]);
 212 +
 213 +       ret = clk_prepare(pc->clk_top);
 214 +        if (ret < 0)
 215 +               return ret;
 216 +
 217 +       ret = clk_prepare(pc->clk_main);
 218 +       if (ret < 0)
 219 +               goto disable_clk_top;
 220 +
 221 +       platform_set_drvdata(pdev, pc);
 222 +
 223 +       pc->chip.dev = &pdev->dev;
 224 +       pc->chip.ops = &mtk_pwm_ops;
 225 +       pc->chip.base = -1;
 226 +       pc->chip.npwm = NUM_PWM;
 227 +
 228 +       ret = pwmchip_add(&pc->chip);
 229 +       if (ret < 0) {
 230 +               dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
 231 +               goto disable_clk_main;
 232 +       }
 233 +
 234 +       return 0;
 235 +
 236 +disable_clk_main:
 237 +       clk_unprepare(pc->clk_main);
 238 +disable_clk_top:
 239 +       clk_unprepare(pc->clk_top);
 240 +
 241 +       return ret;
 242 +}
 243 +
 244 +static int mtk_pwm_remove(struct platform_device *pdev)
 245 +{
 246 +       struct mtk_pwm_chip *pc = platform_get_drvdata(pdev);
 247 +       int i;
 248 +
 249 +       for (i = 0; i < NUM_PWM; i++)
 250 +               pwm_disable(&pc->chip.pwms[i]);
 251 +
 252 +       return pwmchip_remove(&pc->chip);
 253 +}
 254 +
 255 +static const struct of_device_id mtk_pwm_of_match[] = {
 256 +       { .compatible = "mediatek,mt7623-pwm" },
 257 +       { }
 258 +};
 259 +
 260 +MODULE_DEVICE_TABLE(of, mtk_pwm_of_match);
 261 +
 262 +static struct platform_driver mtk_pwm_driver = {
 263 +       .driver = {
 264 +               .name = "mtk-pwm",
 265 +               .owner = THIS_MODULE,
 266 +               .of_match_table = mtk_pwm_of_match,
 267 +       },
 268 +       .probe = mtk_pwm_probe,
 269 +       .remove = mtk_pwm_remove,
 270 +};
 271 +
 272 +module_platform_driver(mtk_pwm_driver);
 273 +
 274 +MODULE_LICENSE("GPL");
 275 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
 276 +MODULE_ALIAS("platform:mtk-pwm");