target/linux/mediatek/patches-4.9/0071-pwm-add-pwm-mediatek.patch

   1 From 6f5941c93bdf7649f392f1263b9068d360ceab4d Mon Sep 17 00:00:00 2001
   2 From: John Crispin <john@phrozen.org>
   3 Date: Fri, 6 May 2016 02:55:48 +0200
   4 Subject: [PATCH 071/102] pwm: add pwm-mediatek
   5
   6 Signed-off-by: John Crispin <john@phrozen.org>
   7 ---
   8  arch/arm/boot/dts/mt7623-evb.dts |   17 +++
   9  arch/arm/boot/dts/mt7623.dtsi    |   22 ++++
  10  drivers/pwm/Kconfig              |    9 ++
  11  drivers/pwm/Makefile             |    1 +
  12  drivers/pwm/pwm-mediatek.c       |  230 ++++++++++++++++++++++++++++++++++++++
  13  5 files changed, 279 insertions(+)
  14  create mode 100644 drivers/pwm/pwm-mediatek.c
  15
  16 --- a/arch/arm/boot/dts/mt7623-evb.dts
  17 +++ b/arch/arm/boot/dts/mt7623-evb.dts
  18 @@ -26,8 +26,25 @@
  19         memory {
  20                 reg = <0 0x80000000 0 0x40000000>;
  21         };
  22 +/*
  23 +       pwm_pins: pwm {
  24 +               pins_pwm1 {
  25 +                       pinmux = <MT7623_PIN_204_PWM1_FUNC_PWM1>;
  26 +               };
  27 +
  28 +               pins_pwm2 {
  29 +                       pinmux = <MT7623_PIN_205_PWM2_FUNC_PWM2>;
  30 +               };
  31 +       };*/
  32 +
  33  };
  34
  35  &uart2 {
  36         status = "okay";
  37  };
  38 +
  39 +/*&pwm {
  40 +       pinctrl-names = "default";
  41 +       pinctrl-0 = <&pwm_pins>;
  42 +       status = "okay";
  43 +};*/
  44 --- a/drivers/pwm/Kconfig
  45 +++ b/drivers/pwm/Kconfig
  46 @@ -282,6 +282,15 @@
  47           To compile this driver as a module, choose M here: the module
  48           will be called pwm-mtk-disp.
  49
  50 +config PWM_MEDIATEK
  51 +       tristate "MediaTek PWM support"
  52 +       depends on ARCH_MEDIATEK || COMPILE_TEST
  53 +       help
  54 +         Generic PWM framework driver for Mediatek ARM SoC.
  55 +
  56 +         To compile this driver as a module, choose M here: the module
  57 +         will be called pwm-mxs.
  58 +
  59  config PWM_MXS
  60         tristate "Freescale MXS PWM support"
  61         depends on ARCH_MXS && OF
  62 --- a/drivers/pwm/Makefile
  63 +++ b/drivers/pwm/Makefile
  64 @@ -25,6 +25,7 @@
  65  obj-$(CONFIG_PWM_LPSS_PCI)     += pwm-lpss-pci.o
  66  obj-$(CONFIG_PWM_LPSS_PLATFORM)        += pwm-lpss-platform.o
  67  obj-$(CONFIG_PWM_MESON)                += pwm-meson.o
  68 +obj-$(CONFIG_PWM_MEDIATEK)     += pwm-mediatek.o
  69  obj-$(CONFIG_PWM_MTK_DISP)     += pwm-mtk-disp.o
  70  obj-$(CONFIG_PWM_MXS)          += pwm-mxs.o
  71  obj-$(CONFIG_PWM_OMAP_DMTIMER) += pwm-omap-dmtimer.o
  72 --- /dev/null
  73 +++ b/drivers/pwm/pwm-mediatek.c
  74 @@ -0,0 +1,230 @@
  75 +/*
  76 + * Mediatek Pulse Width Modulator driver
  77 + *
  78 + * Copyright (C) 2015 John Crispin <blogic@openwrt.org>
  79 + *
  80 + * This file is licensed under the terms of the GNU General Public
  81 + * License version 2. This program is licensed "as is" without any
  82 + * warranty of any kind, whether express or implied.
  83 + */
  84 +
  85 +#include <linux/err.h>
  86 +#include <linux/io.h>
  87 +#include <linux/ioport.h>
  88 +#include <linux/kernel.h>
  89 +#include <linux/module.h>
  90 +#include <linux/clk.h>
  91 +#include <linux/of.h>
  92 +#include <linux/platform_device.h>
  93 +#include <linux/pwm.h>
  94 +#include <linux/slab.h>
  95 +#include <linux/types.h>
  96 +
  97 +#define NUM_PWM                5
  98 +
  99 +/* PWM registers and bits definitions */
 100 +#define PWMCON                 0x00
 101 +#define PWMHDUR                        0x04
 102 +#define PWMLDUR                        0x08
 103 +#define PWMGDUR                        0x0c
 104 +#define PWMWAVENUM             0x28
 105 +#define PWMDWIDTH              0x2c
 106 +#define PWMTHRES               0x30
 107 +
 108 +/**
 109 + * struct mtk_pwm_chip - struct representing pwm chip
 110 + *
 111 + * @mmio_base: base address of pwm chip
 112 + * @chip: linux pwm chip representation
 113 + */
 114 +struct mtk_pwm_chip {
 115 +       void __iomem *mmio_base;
 116 +       struct pwm_chip chip;
 117 +       struct clk *clk_top;
 118 +       struct clk *clk_main;
 119 +       struct clk *clk_pwm[NUM_PWM];
 120 +};
 121 +
 122 +static inline struct mtk_pwm_chip *to_mtk_pwm_chip(struct pwm_chip *chip)
 123 +{
 124 +       return container_of(chip, struct mtk_pwm_chip, chip);
 125 +}
 126 +
 127 +static inline u32 mtk_pwm_readl(struct mtk_pwm_chip *chip, unsigned int num,
 128 +                                 unsigned long offset)
 129 +{
 130 +       return ioread32(chip->mmio_base + 0x10 + (num * 0x40) + offset);
 131 +}
 132 +
 133 +static inline void mtk_pwm_writel(struct mtk_pwm_chip *chip,
 134 +                                   unsigned int num, unsigned long offset,
 135 +                                   unsigned long val)
 136 +{
 137 +       iowrite32(val, chip->mmio_base + 0x10 + (num * 0x40) + offset);
 138 +}
 139 +
 140 +static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 141 +                           int duty_ns, int period_ns)
 142 +{
 143 +       struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
 144 +       u32 resolution = 100 / 4;
 145 +       u32 clkdiv = 0;
 146 +
 147 +       resolution = 1000000000 / (clk_get_rate(pc->clk_pwm[pwm->hwpwm]));
 148 +
 149 +       while (period_ns / resolution  > 8191) {
 150 +               clkdiv++;
 151 +               resolution *= 2;
 152 +       }
 153 +
 154 +       if (clkdiv > 7)
 155 +               return -1;
 156 +
 157 +       mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | BIT(3) | clkdiv);
 158 +       mtk_pwm_writel(pc, pwm->hwpwm, PWMDWIDTH, period_ns / resolution);
 159 +       mtk_pwm_writel(pc, pwm->hwpwm, PWMTHRES, duty_ns / resolution);
 160 +       return 0;
 161 +}
 162 +
 163 +static int mtk_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 164 +{
 165 +       struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
 166 +       u32 val;
 167 +       int ret;
 168 +
 169 +       ret = clk_prepare(pc->clk_pwm[pwm->hwpwm]);
 170 +       if (ret < 0)
 171 +               return ret;
 172 +
 173 +       val = ioread32(pc->mmio_base);
 174 +       val |= BIT(pwm->hwpwm);
 175 +       iowrite32(val, pc->mmio_base);
 176 +
 177 +       return 0;
 178 +}
 179 +
 180 +static void mtk_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 181 +{
 182 +       struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
 183 +       u32 val;
 184 +
 185 +       val = ioread32(pc->mmio_base);
 186 +       val &= ~BIT(pwm->hwpwm);
 187 +       iowrite32(val, pc->mmio_base);
 188 +        clk_unprepare(pc->clk_pwm[pwm->hwpwm]);
 189 +}
 190 +
 191 +static const struct pwm_ops mtk_pwm_ops = {
 192 +       .config = mtk_pwm_config,
 193 +       .enable = mtk_pwm_enable,
 194 +       .disable = mtk_pwm_disable,
 195 +       .owner = THIS_MODULE,
 196 +};
 197 +
 198 +static int mtk_pwm_probe(struct platform_device *pdev)
 199 +{
 200 +       struct mtk_pwm_chip *pc;
 201 +       struct resource *r;
 202 +       int ret;
 203 +
 204 +       pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
 205 +       if (!pc)
 206 +               return -ENOMEM;
 207 +
 208 +       r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 209 +       pc->mmio_base = devm_ioremap_resource(&pdev->dev, r);
 210 +       if (IS_ERR(pc->mmio_base))
 211 +               return PTR_ERR(pc->mmio_base);
 212 +
 213 +       pc->clk_main = devm_clk_get(&pdev->dev, "main");
 214 +        if (IS_ERR(pc->clk_main))
 215 +               return PTR_ERR(pc->clk_main);
 216 +
 217 +       pc->clk_top = devm_clk_get(&pdev->dev, "top");
 218 +        if (IS_ERR(pc->clk_top))
 219 +               return PTR_ERR(pc->clk_top);
 220 +
 221 +       pc->clk_pwm[0] = devm_clk_get(&pdev->dev, "pwm1");
 222 +        if (IS_ERR(pc->clk_pwm[0]))
 223 +               return PTR_ERR(pc->clk_pwm[0]);
 224 +
 225 +       pc->clk_pwm[1] = devm_clk_get(&pdev->dev, "pwm2");
 226 +        if (IS_ERR(pc->clk_pwm[1]))
 227 +               return PTR_ERR(pc->clk_pwm[1]);
 228 +
 229 +       pc->clk_pwm[2] = devm_clk_get(&pdev->dev, "pwm3");
 230 +        if (IS_ERR(pc->clk_pwm[2]))
 231 +               return PTR_ERR(pc->clk_pwm[2]);
 232 +
 233 +       pc->clk_pwm[3] = devm_clk_get(&pdev->dev, "pwm4");
 234 +        if (IS_ERR(pc->clk_pwm[3]))
 235 +               return PTR_ERR(pc->clk_pwm[3]);
 236 +
 237 +       pc->clk_pwm[4] = devm_clk_get(&pdev->dev, "pwm5");
 238 +        if (IS_ERR(pc->clk_pwm[4]))
 239 +               return PTR_ERR(pc->clk_pwm[4]);
 240 +
 241 +       ret = clk_prepare(pc->clk_top);
 242 +        if (ret < 0)
 243 +               return ret;
 244 +
 245 +       ret = clk_prepare(pc->clk_main);
 246 +       if (ret < 0)
 247 +               goto disable_clk_top;
 248 +
 249 +       platform_set_drvdata(pdev, pc);
 250 +
 251 +       pc->chip.dev = &pdev->dev;
 252 +       pc->chip.ops = &mtk_pwm_ops;
 253 +       pc->chip.base = -1;
 254 +       pc->chip.npwm = NUM_PWM;
 255 +
 256 +       ret = pwmchip_add(&pc->chip);
 257 +       if (ret < 0) {
 258 +               dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
 259 +               goto disable_clk_main;
 260 +       }
 261 +
 262 +       return 0;
 263 +
 264 +disable_clk_main:
 265 +       clk_unprepare(pc->clk_main);
 266 +disable_clk_top:
 267 +       clk_unprepare(pc->clk_top);
 268 +
 269 +       return ret;
 270 +}
 271 +
 272 +static int mtk_pwm_remove(struct platform_device *pdev)
 273 +{
 274 +       struct mtk_pwm_chip *pc = platform_get_drvdata(pdev);
 275 +       int i;
 276 +
 277 +       for (i = 0; i < NUM_PWM; i++)
 278 +               pwm_disable(&pc->chip.pwms[i]);
 279 +
 280 +       return pwmchip_remove(&pc->chip);
 281 +}
 282 +
 283 +static const struct of_device_id mtk_pwm_of_match[] = {
 284 +       { .compatible = "mediatek,mt7623-pwm" },
 285 +       { }
 286 +};
 287 +
 288 +MODULE_DEVICE_TABLE(of, mtk_pwm_of_match);
 289 +
 290 +static struct platform_driver mtk_pwm_driver = {
 291 +       .driver = {
 292 +               .name = "mtk-pwm",
 293 +               .owner = THIS_MODULE,
 294 +               .of_match_table = mtk_pwm_of_match,
 295 +       },
 296 +       .probe = mtk_pwm_probe,
 297 +       .remove = mtk_pwm_remove,
 298 +};
 299 +
 300 +module_platform_driver(mtk_pwm_driver);
 301 +
 302 +MODULE_LICENSE("GPL");
 303 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
 304 +MODULE_ALIAS("platform:mtk-pwm");