mediatek: various fixes for v4.9
[openwrt/openwrt.git] / target / linux / mediatek / patches-4.9 / 0071-pwm-add-pwm-mediatek.patch
1 From 6f5941c93bdf7649f392f1263b9068d360ceab4d Mon Sep 17 00:00:00 2001
2 From: John Crispin <john@phrozen.org>
3 Date: Fri, 6 May 2016 02:55:48 +0200
4 Subject: [PATCH 071/102] pwm: add pwm-mediatek
5
6 Signed-off-by: John Crispin <john@phrozen.org>
7 ---
8 arch/arm/boot/dts/mt7623-evb.dts | 17 +++
9 arch/arm/boot/dts/mt7623.dtsi | 22 ++++
10 drivers/pwm/Kconfig | 9 ++
11 drivers/pwm/Makefile | 1 +
12 drivers/pwm/pwm-mediatek.c | 230 ++++++++++++++++++++++++++++++++++++++
13 5 files changed, 279 insertions(+)
14 create mode 100644 drivers/pwm/pwm-mediatek.c
15
16 Index: linux-4.9.17/drivers/pwm/Kconfig
17 ===================================================================
18 --- linux-4.9.17.orig/drivers/pwm/Kconfig
19 +++ linux-4.9.17/drivers/pwm/Kconfig
20 @@ -282,6 +282,15 @@ config PWM_MTK_DISP
21 To compile this driver as a module, choose M here: the module
22 will be called pwm-mtk-disp.
23
24 +config PWM_MEDIATEK
25 + tristate "MediaTek PWM support"
26 + depends on ARCH_MEDIATEK || COMPILE_TEST
27 + help
28 + Generic PWM framework driver for Mediatek ARM SoC.
29 +
30 + To compile this driver as a module, choose M here: the module
31 + will be called pwm-mxs.
32 +
33 config PWM_MXS
34 tristate "Freescale MXS PWM support"
35 depends on ARCH_MXS && OF
36 Index: linux-4.9.17/drivers/pwm/Makefile
37 ===================================================================
38 --- linux-4.9.17.orig/drivers/pwm/Makefile
39 +++ linux-4.9.17/drivers/pwm/Makefile
40 @@ -25,6 +25,7 @@ obj-$(CONFIG_PWM_LPSS) += pwm-lpss.o
41 obj-$(CONFIG_PWM_LPSS_PCI) += pwm-lpss-pci.o
42 obj-$(CONFIG_PWM_LPSS_PLATFORM) += pwm-lpss-platform.o
43 obj-$(CONFIG_PWM_MESON) += pwm-meson.o
44 +obj-$(CONFIG_PWM_MEDIATEK) += pwm-mediatek.o
45 obj-$(CONFIG_PWM_MTK_DISP) += pwm-mtk-disp.o
46 obj-$(CONFIG_PWM_MXS) += pwm-mxs.o
47 obj-$(CONFIG_PWM_OMAP_DMTIMER) += pwm-omap-dmtimer.o
48 Index: linux-4.9.17/drivers/pwm/pwm-mediatek.c
49 ===================================================================
50 --- /dev/null
51 +++ linux-4.9.17/drivers/pwm/pwm-mediatek.c
52 @@ -0,0 +1,230 @@
53 +/*
54 + * Mediatek Pulse Width Modulator driver
55 + *
56 + * Copyright (C) 2015 John Crispin <blogic@openwrt.org>
57 + *
58 + * This file is licensed under the terms of the GNU General Public
59 + * License version 2. This program is licensed "as is" without any
60 + * warranty of any kind, whether express or implied.
61 + */
62 +
63 +#include <linux/err.h>
64 +#include <linux/io.h>
65 +#include <linux/ioport.h>
66 +#include <linux/kernel.h>
67 +#include <linux/module.h>
68 +#include <linux/clk.h>
69 +#include <linux/of.h>
70 +#include <linux/platform_device.h>
71 +#include <linux/pwm.h>
72 +#include <linux/slab.h>
73 +#include <linux/types.h>
74 +
75 +#define NUM_PWM 5
76 +
77 +/* PWM registers and bits definitions */
78 +#define PWMCON 0x00
79 +#define PWMHDUR 0x04
80 +#define PWMLDUR 0x08
81 +#define PWMGDUR 0x0c
82 +#define PWMWAVENUM 0x28
83 +#define PWMDWIDTH 0x2c
84 +#define PWMTHRES 0x30
85 +
86 +/**
87 + * struct mtk_pwm_chip - struct representing pwm chip
88 + *
89 + * @mmio_base: base address of pwm chip
90 + * @chip: linux pwm chip representation
91 + */
92 +struct mtk_pwm_chip {
93 + void __iomem *mmio_base;
94 + struct pwm_chip chip;
95 + struct clk *clk_top;
96 + struct clk *clk_main;
97 + struct clk *clk_pwm[NUM_PWM];
98 +};
99 +
100 +static inline struct mtk_pwm_chip *to_mtk_pwm_chip(struct pwm_chip *chip)
101 +{
102 + return container_of(chip, struct mtk_pwm_chip, chip);
103 +}
104 +
105 +static inline u32 mtk_pwm_readl(struct mtk_pwm_chip *chip, unsigned int num,
106 + unsigned long offset)
107 +{
108 + return ioread32(chip->mmio_base + 0x10 + (num * 0x40) + offset);
109 +}
110 +
111 +static inline void mtk_pwm_writel(struct mtk_pwm_chip *chip,
112 + unsigned int num, unsigned long offset,
113 + unsigned long val)
114 +{
115 + iowrite32(val, chip->mmio_base + 0x10 + (num * 0x40) + offset);
116 +}
117 +
118 +static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
119 + int duty_ns, int period_ns)
120 +{
121 + struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
122 + u32 resolution = 100 / 4;
123 + u32 clkdiv = 0;
124 +
125 + resolution = 1000000000 / (clk_get_rate(pc->clk_pwm[pwm->hwpwm]));
126 +
127 + while (period_ns / resolution > 8191) {
128 + clkdiv++;
129 + resolution *= 2;
130 + }
131 +
132 + if (clkdiv > 7)
133 + return -1;
134 +
135 + mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | BIT(3) | clkdiv);
136 + mtk_pwm_writel(pc, pwm->hwpwm, PWMDWIDTH, period_ns / resolution);
137 + mtk_pwm_writel(pc, pwm->hwpwm, PWMTHRES, duty_ns / resolution);
138 + return 0;
139 +}
140 +
141 +static int mtk_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
142 +{
143 + struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
144 + u32 val;
145 + int ret;
146 +
147 + ret = clk_prepare(pc->clk_pwm[pwm->hwpwm]);
148 + if (ret < 0)
149 + return ret;
150 +
151 + val = ioread32(pc->mmio_base);
152 + val |= BIT(pwm->hwpwm);
153 + iowrite32(val, pc->mmio_base);
154 +
155 + return 0;
156 +}
157 +
158 +static void mtk_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
159 +{
160 + struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
161 + u32 val;
162 +
163 + val = ioread32(pc->mmio_base);
164 + val &= ~BIT(pwm->hwpwm);
165 + iowrite32(val, pc->mmio_base);
166 + clk_unprepare(pc->clk_pwm[pwm->hwpwm]);
167 +}
168 +
169 +static const struct pwm_ops mtk_pwm_ops = {
170 + .config = mtk_pwm_config,
171 + .enable = mtk_pwm_enable,
172 + .disable = mtk_pwm_disable,
173 + .owner = THIS_MODULE,
174 +};
175 +
176 +static int mtk_pwm_probe(struct platform_device *pdev)
177 +{
178 + struct mtk_pwm_chip *pc;
179 + struct resource *r;
180 + int ret;
181 +
182 + pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
183 + if (!pc)
184 + return -ENOMEM;
185 +
186 + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
187 + pc->mmio_base = devm_ioremap_resource(&pdev->dev, r);
188 + if (IS_ERR(pc->mmio_base))
189 + return PTR_ERR(pc->mmio_base);
190 +
191 + pc->clk_main = devm_clk_get(&pdev->dev, "main");
192 + if (IS_ERR(pc->clk_main))
193 + return PTR_ERR(pc->clk_main);
194 +
195 + pc->clk_top = devm_clk_get(&pdev->dev, "top");
196 + if (IS_ERR(pc->clk_top))
197 + return PTR_ERR(pc->clk_top);
198 +
199 + pc->clk_pwm[0] = devm_clk_get(&pdev->dev, "pwm1");
200 + if (IS_ERR(pc->clk_pwm[0]))
201 + return PTR_ERR(pc->clk_pwm[0]);
202 +
203 + pc->clk_pwm[1] = devm_clk_get(&pdev->dev, "pwm2");
204 + if (IS_ERR(pc->clk_pwm[1]))
205 + return PTR_ERR(pc->clk_pwm[1]);
206 +
207 + pc->clk_pwm[2] = devm_clk_get(&pdev->dev, "pwm3");
208 + if (IS_ERR(pc->clk_pwm[2]))
209 + return PTR_ERR(pc->clk_pwm[2]);
210 +
211 + pc->clk_pwm[3] = devm_clk_get(&pdev->dev, "pwm4");
212 + if (IS_ERR(pc->clk_pwm[3]))
213 + return PTR_ERR(pc->clk_pwm[3]);
214 +
215 + pc->clk_pwm[4] = devm_clk_get(&pdev->dev, "pwm5");
216 + if (IS_ERR(pc->clk_pwm[4]))
217 + return PTR_ERR(pc->clk_pwm[4]);
218 +
219 + ret = clk_prepare(pc->clk_top);
220 + if (ret < 0)
221 + return ret;
222 +
223 + ret = clk_prepare(pc->clk_main);
224 + if (ret < 0)
225 + goto disable_clk_top;
226 +
227 + platform_set_drvdata(pdev, pc);
228 +
229 + pc->chip.dev = &pdev->dev;
230 + pc->chip.ops = &mtk_pwm_ops;
231 + pc->chip.base = -1;
232 + pc->chip.npwm = NUM_PWM;
233 +
234 + ret = pwmchip_add(&pc->chip);
235 + if (ret < 0) {
236 + dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
237 + goto disable_clk_main;
238 + }
239 +
240 + return 0;
241 +
242 +disable_clk_main:
243 + clk_unprepare(pc->clk_main);
244 +disable_clk_top:
245 + clk_unprepare(pc->clk_top);
246 +
247 + return ret;
248 +}
249 +
250 +static int mtk_pwm_remove(struct platform_device *pdev)
251 +{
252 + struct mtk_pwm_chip *pc = platform_get_drvdata(pdev);
253 + int i;
254 +
255 + for (i = 0; i < NUM_PWM; i++)
256 + pwm_disable(&pc->chip.pwms[i]);
257 +
258 + return pwmchip_remove(&pc->chip);
259 +}
260 +
261 +static const struct of_device_id mtk_pwm_of_match[] = {
262 + { .compatible = "mediatek,mt7623-pwm" },
263 + { }
264 +};
265 +
266 +MODULE_DEVICE_TABLE(of, mtk_pwm_of_match);
267 +
268 +static struct platform_driver mtk_pwm_driver = {
269 + .driver = {
270 + .name = "mtk-pwm",
271 + .owner = THIS_MODULE,
272 + .of_match_table = mtk_pwm_of_match,
273 + },
274 + .probe = mtk_pwm_probe,
275 + .remove = mtk_pwm_remove,
276 +};
277 +
278 +module_platform_driver(mtk_pwm_driver);
279 +
280 +MODULE_LICENSE("GPL");
281 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
282 +MODULE_ALIAS("platform:mtk-pwm");