target/linux/mediatek/patches-5.4/0226-phy-phy-mtk-tphy-Add-hifsys-support.patch

   1 From 28f9a5e2a3f5441ab5594669ed82da11e32277a9 Mon Sep 17 00:00:00 2001
   2 From: Kristian Evensen <kristian.evensen@gmail.com>
   3 Date: Mon, 30 Apr 2018 14:38:01 +0200
   4 Subject: [PATCH] phy: phy-mtk-tphy: Add hifsys-support
   5
   6 ---
   7  drivers/phy/mediatek/phy-mtk-tphy.c | 20 ++++++++++++++++++++
   8  1 file changed, 20 insertions(+)
   9
  10 --- a/drivers/phy/mediatek/phy-mtk-tphy.c
  11 +++ b/drivers/phy/mediatek/phy-mtk-tphy.c
  12 @@ -15,6 +15,8 @@
  13  #include <linux/of_device.h>
  14  #include <linux/phy/phy.h>
  15  #include <linux/platform_device.h>
  16 +#include <linux/mfd/syscon.h>
  17 +#include <linux/regmap.h>
  18
  19  /* version V1 sub-banks offset base address */
  20  /* banks shared by multiple phys */
  21 @@ -263,6 +265,9 @@
  22  #define RG_CDR_BIRLTD0_GEN3_MSK                GENMASK(4, 0)
  23  #define RG_CDR_BIRLTD0_GEN3_VAL(x)     (0x1f & (x))
  24
  25 +#define HIF_SYSCFG1                    0x14
  26 +#define HIF_SYSCFG1_PHY2_MASK          (0x3 << 20)
  27 +
  28  enum mtk_phy_version {
  29         MTK_PHY_V1 = 1,
  30         MTK_PHY_V2,
  31 @@ -310,6 +315,7 @@ struct mtk_tphy {
  32         struct clk *u3phya_ref; /* reference clock of usb3 anolog phy */
  33         const struct mtk_phy_pdata *pdata;
  34         struct mtk_phy_instance **phys;
  35 +       struct regmap *hif;
  36         int nphys;
  37         int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */
  38         int src_coef; /* coefficient for slew rate calibrate */
  39 @@ -629,6 +635,10 @@ static void pcie_phy_instance_init(struc
  40         if (tphy->pdata->version != MTK_PHY_V1)
  41                 return;
  42
  43 +       if (tphy->hif)
  44 +               regmap_update_bits(tphy->hif, HIF_SYSCFG1,
  45 +                                  HIF_SYSCFG1_PHY2_MASK, 0);
  46 +
  47         tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0);
  48         tmp &= ~(P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H);
  49         tmp |= P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | P3A_RG_XTAL_EXT_PE2H_VAL(0x2);
  50 @@ -1114,6 +1124,16 @@ static int mtk_tphy_probe(struct platfor
  51                 &tphy->src_ref_clk);
  52         device_property_read_u32(dev, "mediatek,src-coef", &tphy->src_coef);
  53
  54 +       if (of_find_property(np, "mediatek,phy-switch", NULL)) {
  55 +               tphy->hif = syscon_regmap_lookup_by_phandle(np,
  56 +                                                           "mediatek,phy-switch");
  57 +               if (IS_ERR(tphy->hif)) {
  58 +                       dev_err(&pdev->dev,
  59 +                               "missing \"mediatek,phy-switch\" phandle\n");
  60 +                       return PTR_ERR(tphy->hif);
  61 +               }
  62 +       }
  63 +
  64         port = 0;
  65         for_each_child_of_node(np, child_np) {
  66                 struct mtk_phy_instance *instance;