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[openwrt/openwrt.git] / target / linux / mediatek / patches-5.4 / 0604-net-dsa-mt7530-Add-the-support-of-MT7531-switch.patch
1 From: Landen Chao <landen.chao@mediatek.com>
2 Date: Fri, 4 Sep 2020 22:21:59 +0800
3 Subject: [PATCH] net: dsa: mt7530: Add the support of MT7531 switch
4
5 Add new support for MT7531:
6
7 MT7531 is the next generation of MT7530. It is also a 7-ports switch with
8 5 giga embedded phys, 2 cpu ports, and the same MAC logic of MT7530. Cpu
9 port 6 only supports SGMII interface. Cpu port 5 supports either RGMII
10 or SGMII in different HW sku, but cannot be muxed to PHY of port 0/4 like
11 mt7530. Due to SGMII interface support, pll, and pad setting are different
12 from MT7530. This patch adds different initial setting, and SGMII phylink
13 handlers of MT7531.
14
15 MT7531 SGMII interface can be configured in following mode:
16 - 'SGMII AN mode' with in-band negotiation capability
17 which is compatible with PHY_INTERFACE_MODE_SGMII.
18 - 'SGMII force mode' without in-band negotiation
19 which is compatible with 10B/8B encoding of
20 PHY_INTERFACE_MODE_1000BASEX with fixed full-duplex and fixed pause.
21 - 2.5 times faster clocked 'SGMII force mode' without in-band negotiation
22 which is compatible with 10B/8B encoding of
23 PHY_INTERFACE_MODE_2500BASEX with fixed full-duplex and fixed pause.
24
25 Signed-off-by: Landen Chao <landen.chao@mediatek.com>
26 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
27 ---
28
29 --- a/drivers/net/dsa/mt7530.c
30 +++ b/drivers/net/dsa/mt7530.c
31 @@ -234,6 +234,12 @@ mt7530_write(struct mt7530_priv *priv, u
32 }
33
34 static u32
35 +_mt7530_unlocked_read(struct mt7530_dummy_poll *p)
36 +{
37 + return mt7530_mii_read(p->priv, p->reg);
38 +}
39 +
40 +static u32
41 _mt7530_read(struct mt7530_dummy_poll *p)
42 {
43 struct mii_bus *bus = p->priv->bus;
44 @@ -481,6 +487,108 @@ mt7530_pad_clk_setup(struct dsa_switch *
45 return 0;
46 }
47
48 +static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv)
49 +{
50 + u32 val;
51 +
52 + val = mt7530_read(priv, MT7531_TOP_SIG_SR);
53 +
54 + return (val & PAD_DUAL_SGMII_EN) != 0;
55 +}
56 +
57 +static int
58 +mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface)
59 +{
60 + struct mt7530_priv *priv = ds->priv;
61 + u32 val;
62 + u32 top_sig;
63 + u32 hwstrap;
64 + u32 xtal;
65 +
66 + if (mt7531_dual_sgmii_supported(priv))
67 + return 0;
68 +
69 + val = mt7530_read(priv, MT7531_CREV);
70 + top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR);
71 + hwstrap = mt7530_read(priv, MT7531_HWTRAP);
72 + if ((val & CHIP_REV_M) > 0)
73 + xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ :
74 + HWTRAP_XTAL_FSEL_25MHZ;
75 + else
76 + xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK;
77 +
78 + /* Step 1 : Disable MT7531 COREPLL */
79 + val = mt7530_read(priv, MT7531_PLLGP_EN);
80 + val &= ~EN_COREPLL;
81 + mt7530_write(priv, MT7531_PLLGP_EN, val);
82 +
83 + /* Step 2: switch to XTAL output */
84 + val = mt7530_read(priv, MT7531_PLLGP_EN);
85 + val |= SW_CLKSW;
86 + mt7530_write(priv, MT7531_PLLGP_EN, val);
87 +
88 + val = mt7530_read(priv, MT7531_PLLGP_CR0);
89 + val &= ~RG_COREPLL_EN;
90 + mt7530_write(priv, MT7531_PLLGP_CR0, val);
91 +
92 + /* Step 3: disable PLLGP and enable program PLLGP */
93 + val = mt7530_read(priv, MT7531_PLLGP_EN);
94 + val |= SW_PLLGP;
95 + mt7530_write(priv, MT7531_PLLGP_EN, val);
96 +
97 + /* Step 4: program COREPLL output frequency to 500MHz */
98 + val = mt7530_read(priv, MT7531_PLLGP_CR0);
99 + val &= ~RG_COREPLL_POSDIV_M;
100 + val |= 2 << RG_COREPLL_POSDIV_S;
101 + mt7530_write(priv, MT7531_PLLGP_CR0, val);
102 + usleep_range(25, 35);
103 +
104 + switch (xtal) {
105 + case HWTRAP_XTAL_FSEL_25MHZ:
106 + val = mt7530_read(priv, MT7531_PLLGP_CR0);
107 + val &= ~RG_COREPLL_SDM_PCW_M;
108 + val |= 0x140000 << RG_COREPLL_SDM_PCW_S;
109 + mt7530_write(priv, MT7531_PLLGP_CR0, val);
110 + break;
111 + case HWTRAP_XTAL_FSEL_40MHZ:
112 + val = mt7530_read(priv, MT7531_PLLGP_CR0);
113 + val &= ~RG_COREPLL_SDM_PCW_M;
114 + val |= 0x190000 << RG_COREPLL_SDM_PCW_S;
115 + mt7530_write(priv, MT7531_PLLGP_CR0, val);
116 + break;
117 + };
118 +
119 + /* Set feedback divide ratio update signal to high */
120 + val = mt7530_read(priv, MT7531_PLLGP_CR0);
121 + val |= RG_COREPLL_SDM_PCW_CHG;
122 + mt7530_write(priv, MT7531_PLLGP_CR0, val);
123 + /* Wait for at least 16 XTAL clocks */
124 + usleep_range(10, 20);
125 +
126 + /* Step 5: set feedback divide ratio update signal to low */
127 + val = mt7530_read(priv, MT7531_PLLGP_CR0);
128 + val &= ~RG_COREPLL_SDM_PCW_CHG;
129 + mt7530_write(priv, MT7531_PLLGP_CR0, val);
130 +
131 + /* Enable 325M clock for SGMII */
132 + mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000);
133 +
134 + /* Enable 250SSC clock for RGMII */
135 + mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000);
136 +
137 + /* Step 6: Enable MT7531 PLL */
138 + val = mt7530_read(priv, MT7531_PLLGP_CR0);
139 + val |= RG_COREPLL_EN;
140 + mt7530_write(priv, MT7531_PLLGP_CR0, val);
141 +
142 + val = mt7530_read(priv, MT7531_PLLGP_EN);
143 + val |= EN_COREPLL;
144 + mt7530_write(priv, MT7531_PLLGP_EN, val);
145 + usleep_range(25, 35);
146 +
147 + return 0;
148 +}
149 +
150 static void
151 mt7530_mib_reset(struct dsa_switch *ds)
152 {
153 @@ -505,6 +613,217 @@ static int mt7530_phy_write(struct dsa_s
154 return mdiobus_write_nested(priv->bus, port, regnum, val);
155 }
156
157 +static int
158 +mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad,
159 + int regnum)
160 +{
161 + struct mii_bus *bus = priv->bus;
162 + struct mt7530_dummy_poll p;
163 + u32 reg, val;
164 + int ret;
165 +
166 + INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
167 +
168 + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
169 +
170 + ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
171 + !(val & MT7531_PHY_ACS_ST), 20, 100000);
172 + if (ret < 0) {
173 + dev_err(priv->dev, "poll timeout\n");
174 + goto out;
175 + }
176 +
177 + reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) |
178 + MT7531_MDIO_DEV_ADDR(devad) | regnum;
179 + mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
180 +
181 + ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
182 + !(val & MT7531_PHY_ACS_ST), 20, 100000);
183 + if (ret < 0) {
184 + dev_err(priv->dev, "poll timeout\n");
185 + goto out;
186 + }
187 +
188 + reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) |
189 + MT7531_MDIO_DEV_ADDR(devad);
190 + mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
191 +
192 + ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
193 + !(val & MT7531_PHY_ACS_ST), 20, 100000);
194 + if (ret < 0) {
195 + dev_err(priv->dev, "poll timeout\n");
196 + goto out;
197 + }
198 +
199 + ret = val & MT7531_MDIO_RW_DATA_MASK;
200 +out:
201 + mutex_unlock(&bus->mdio_lock);
202 +
203 + return ret;
204 +}
205 +
206 +static int
207 +mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad,
208 + int regnum, u32 data)
209 +{
210 + struct mii_bus *bus = priv->bus;
211 + struct mt7530_dummy_poll p;
212 + u32 val, reg;
213 + int ret;
214 +
215 + INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
216 +
217 + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
218 +
219 + ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
220 + !(val & MT7531_PHY_ACS_ST), 20, 100000);
221 + if (ret < 0) {
222 + dev_err(priv->dev, "poll timeout\n");
223 + goto out;
224 + }
225 +
226 + reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) |
227 + MT7531_MDIO_DEV_ADDR(devad) | regnum;
228 + mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
229 +
230 + ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
231 + !(val & MT7531_PHY_ACS_ST), 20, 100000);
232 + if (ret < 0) {
233 + dev_err(priv->dev, "poll timeout\n");
234 + goto out;
235 + }
236 +
237 + reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) |
238 + MT7531_MDIO_DEV_ADDR(devad) | data;
239 + mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
240 +
241 + ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
242 + !(val & MT7531_PHY_ACS_ST), 20, 100000);
243 + if (ret < 0) {
244 + dev_err(priv->dev, "poll timeout\n");
245 + goto out;
246 + }
247 +
248 +out:
249 + mutex_unlock(&bus->mdio_lock);
250 +
251 + return ret;
252 +}
253 +
254 +static int
255 +mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum)
256 +{
257 + struct mii_bus *bus = priv->bus;
258 + struct mt7530_dummy_poll p;
259 + int ret;
260 + u32 val;
261 +
262 + INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
263 +
264 + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
265 +
266 + ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
267 + !(val & MT7531_PHY_ACS_ST), 20, 100000);
268 + if (ret < 0) {
269 + dev_err(priv->dev, "poll timeout\n");
270 + goto out;
271 + }
272 +
273 + val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) |
274 + MT7531_MDIO_REG_ADDR(regnum);
275 +
276 + mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST);
277 +
278 + ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
279 + !(val & MT7531_PHY_ACS_ST), 20, 100000);
280 + if (ret < 0) {
281 + dev_err(priv->dev, "poll timeout\n");
282 + goto out;
283 + }
284 +
285 + ret = val & MT7531_MDIO_RW_DATA_MASK;
286 +out:
287 + mutex_unlock(&bus->mdio_lock);
288 +
289 + return ret;
290 +}
291 +
292 +static int
293 +mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum,
294 + u16 data)
295 +{
296 + struct mii_bus *bus = priv->bus;
297 + struct mt7530_dummy_poll p;
298 + int ret;
299 + u32 reg;
300 +
301 + INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
302 +
303 + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
304 +
305 + ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
306 + !(reg & MT7531_PHY_ACS_ST), 20, 100000);
307 + if (ret < 0) {
308 + dev_err(priv->dev, "poll timeout\n");
309 + goto out;
310 + }
311 +
312 + reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) |
313 + MT7531_MDIO_REG_ADDR(regnum) | data;
314 +
315 + mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
316 +
317 + ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
318 + !(reg & MT7531_PHY_ACS_ST), 20, 100000);
319 + if (ret < 0) {
320 + dev_err(priv->dev, "poll timeout\n");
321 + goto out;
322 + }
323 +
324 +out:
325 + mutex_unlock(&bus->mdio_lock);
326 +
327 + return ret;
328 +}
329 +
330 +static int
331 +mt7531_ind_phy_read(struct dsa_switch *ds, int port, int regnum)
332 +{
333 + struct mt7530_priv *priv = ds->priv;
334 + int devad;
335 + int ret;
336 +
337 + if (regnum & MII_ADDR_C45) {
338 + devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f;
339 + ret = mt7531_ind_c45_phy_read(priv, port, devad,
340 + regnum & MII_REGADDR_C45_MASK);
341 + } else {
342 + ret = mt7531_ind_c22_phy_read(priv, port, regnum);
343 + }
344 +
345 + return ret;
346 +}
347 +
348 +static int
349 +mt7531_ind_phy_write(struct dsa_switch *ds, int port, int regnum,
350 + u16 data)
351 +{
352 + struct mt7530_priv *priv = ds->priv;
353 + int devad;
354 + int ret;
355 +
356 + if (regnum & MII_ADDR_C45) {
357 + devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f;
358 + ret = mt7531_ind_c45_phy_write(priv, port, devad,
359 + regnum & MII_REGADDR_C45_MASK,
360 + data);
361 + } else {
362 + ret = mt7531_ind_c22_phy_write(priv, port, regnum, data);
363 + }
364 +
365 + return ret;
366 +}
367 +
368 static void
369 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset,
370 uint8_t *data)
371 @@ -621,9 +940,14 @@ unlock_exit:
372 }
373
374 static int
375 -mt7530_cpu_port_enable(struct mt7530_priv *priv,
376 - int port)
377 +mt753x_cpu_port_enable(struct dsa_switch *ds, int port)
378 {
379 + struct mt7530_priv *priv = ds->priv;
380 +
381 + /* Setup max capability of CPU port at first */
382 + if (priv->info->cpu_port_config)
383 + priv->info->cpu_port_config(ds, port);
384 +
385 /* Enable Mediatek header mode on the cpu port */
386 mt7530_write(priv, MT7530_PVC_P(port),
387 PORT_SPEC_TAG);
388 @@ -636,7 +960,7 @@ mt7530_cpu_port_enable(struct mt7530_pri
389 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port));
390
391 /* CPU port gets connected to all user ports of
392 - * the switch
393 + * the switch.
394 */
395 mt7530_write(priv, MT7530_PCR_P(port),
396 PCR_MATRIX(dsa_user_ports(priv->ds)));
397 @@ -1130,27 +1454,42 @@ mt7530_port_vlan_del(struct dsa_switch *
398 return 0;
399 }
400
401 -static int mt7530_port_mirror_add(struct dsa_switch *ds, int port,
402 +static int mt753x_mirror_port_get(unsigned int id, u32 val)
403 +{
404 + return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) :
405 + MIRROR_PORT(val);
406 +}
407 +
408 +static int mt753x_mirror_port_set(unsigned int id, u32 val)
409 +{
410 + return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) :
411 + MIRROR_PORT(val);
412 +}
413 +
414 +static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,
415 struct dsa_mall_mirror_tc_entry *mirror,
416 bool ingress)
417 {
418 struct mt7530_priv *priv = ds->priv;
419 + int monitor_port;
420 u32 val;
421
422 /* Check for existent entry */
423 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port))
424 return -EEXIST;
425
426 - val = mt7530_read(priv, MT7530_MFC);
427 + val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
428
429 /* MT7530 only supports one monitor port */
430 - if (val & MIRROR_EN && MIRROR_PORT(val) != mirror->to_local_port)
431 + monitor_port = mt753x_mirror_port_get(priv->id, val);
432 + if (val & MT753X_MIRROR_EN(priv->id) &&
433 + monitor_port != mirror->to_local_port)
434 return -EEXIST;
435
436 - val |= MIRROR_EN;
437 - val &= ~MIRROR_MASK;
438 - val |= mirror->to_local_port;
439 - mt7530_write(priv, MT7530_MFC, val);
440 + val |= MT753X_MIRROR_EN(priv->id);
441 + val &= ~MT753X_MIRROR_MASK(priv->id);
442 + val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port);
443 + mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
444
445 val = mt7530_read(priv, MT7530_PCR_P(port));
446 if (ingress) {
447 @@ -1165,7 +1504,7 @@ static int mt7530_port_mirror_add(struct
448 return 0;
449 }
450
451 -static void mt7530_port_mirror_del(struct dsa_switch *ds, int port,
452 +static void mt753x_port_mirror_del(struct dsa_switch *ds, int port,
453 struct dsa_mall_mirror_tc_entry *mirror)
454 {
455 struct mt7530_priv *priv = ds->priv;
456 @@ -1182,9 +1521,9 @@ static void mt7530_port_mirror_del(struc
457 mt7530_write(priv, MT7530_PCR_P(port), val);
458
459 if (!priv->mirror_rx && !priv->mirror_tx) {
460 - val = mt7530_read(priv, MT7530_MFC);
461 - val &= ~MIRROR_EN;
462 - mt7530_write(priv, MT7530_MFC, val);
463 + val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
464 + val &= ~MT753X_MIRROR_EN(priv->id);
465 + mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
466 }
467 }
468
469 @@ -1290,7 +1629,7 @@ mt7530_setup(struct dsa_switch *ds)
470 PCR_MATRIX_CLR);
471
472 if (dsa_is_cpu_port(ds, i))
473 - mt7530_cpu_port_enable(priv, i);
474 + mt753x_cpu_port_enable(ds, i);
475 else
476 mt7530_port_disable(ds, i);
477
478 @@ -1344,6 +1683,118 @@ mt7530_setup(struct dsa_switch *ds)
479 return 0;
480 }
481
482 +static int
483 +mt7531_setup(struct dsa_switch *ds)
484 +{
485 + struct mt7530_priv *priv = ds->priv;
486 + struct mt7530_dummy_poll p;
487 + u32 val, id;
488 + int ret, i;
489 +
490 + /* Reset whole chip through gpio pin or memory-mapped registers for
491 + * different type of hardware
492 + */
493 + if (priv->mcm) {
494 + reset_control_assert(priv->rstc);
495 + usleep_range(1000, 1100);
496 + reset_control_deassert(priv->rstc);
497 + } else {
498 + gpiod_set_value_cansleep(priv->reset, 0);
499 + usleep_range(1000, 1100);
500 + gpiod_set_value_cansleep(priv->reset, 1);
501 + }
502 +
503 + /* Waiting for MT7530 got to stable */
504 + INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
505 + ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
506 + 20, 1000000);
507 + if (ret < 0) {
508 + dev_err(priv->dev, "reset timeout\n");
509 + return ret;
510 + }
511 +
512 + id = mt7530_read(priv, MT7531_CREV);
513 + id >>= CHIP_NAME_SHIFT;
514 +
515 + if (id != MT7531_ID) {
516 + dev_err(priv->dev, "chip %x can't be supported\n", id);
517 + return -ENODEV;
518 + }
519 +
520 + /* Reset the switch through internal reset */
521 + mt7530_write(priv, MT7530_SYS_CTRL,
522 + SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
523 + SYS_CTRL_REG_RST);
524 +
525 + if (mt7531_dual_sgmii_supported(priv)) {
526 + priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII;
527 +
528 + /* Let ds->slave_mii_bus be able to access external phy. */
529 + mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK,
530 + MT7531_EXT_P_MDC_11);
531 + mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK,
532 + MT7531_EXT_P_MDIO_12);
533 + } else {
534 + priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
535 + }
536 + dev_dbg(ds->dev, "P5 support %s interface\n",
537 + p5_intf_modes(priv->p5_intf_sel));
538 +
539 + mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
540 + MT7531_GPIO0_INTERRUPT);
541 +
542 + /* Let phylink decide the interface later. */
543 + priv->p5_interface = PHY_INTERFACE_MODE_NA;
544 + priv->p6_interface = PHY_INTERFACE_MODE_NA;
545 +
546 + /* Enable PHY core PLL, since phy_device has not yet been created
547 + * provided for phy_[read,write]_mmd_indirect is called, we provide
548 + * our own mt7531_ind_mmd_phy_[read,write] to complete this
549 + * function.
550 + */
551 + val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR,
552 + MDIO_MMD_VEND2, CORE_PLL_GROUP4);
553 + val |= MT7531_PHY_PLL_BYPASS_MODE;
554 + val &= ~MT7531_PHY_PLL_OFF;
555 + mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2,
556 + CORE_PLL_GROUP4, val);
557 +
558 + /* BPDU to CPU port */
559 + mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK,
560 + BIT(MT7530_CPU_PORT));
561 + mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK,
562 + MT753X_BPDU_CPU_ONLY);
563 +
564 + /* Enable and reset MIB counters */
565 + mt7530_mib_reset(ds);
566 +
567 + for (i = 0; i < MT7530_NUM_PORTS; i++) {
568 + /* Disable forwarding by default on all ports */
569 + mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
570 + PCR_MATRIX_CLR);
571 +
572 + mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR);
573 +
574 + if (dsa_is_cpu_port(ds, i))
575 + mt753x_cpu_port_enable(ds, i);
576 + else
577 + mt7530_port_disable(ds, i);
578 +
579 + /* Enable consistent egress tag */
580 + mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
581 + PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
582 + }
583 +
584 + ds->configure_vlan_while_not_filtering = true;
585 +
586 + /* Flush the FDB table */
587 + ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
588 + if (ret < 0)
589 + return ret;
590 +
591 + return 0;
592 +}
593 +
594 static bool
595 mt7530_phy_mode_supported(struct dsa_switch *ds, int port,
596 const struct phylink_link_state *state)
597 @@ -1382,6 +1833,47 @@ unsupported:
598 return false;
599 }
600
601 +static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port)
602 +{
603 + return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII);
604 +}
605 +
606 +static bool
607 +mt7531_phy_supported(struct dsa_switch *ds, int port,
608 + const struct phylink_link_state *state)
609 +{
610 + struct mt7530_priv *priv = ds->priv;
611 +
612 + switch (port) {
613 + case 0: /* Internal phy */
614 + case 1:
615 + case 2:
616 + case 3:
617 + case 4:
618 + if (state->interface != PHY_INTERFACE_MODE_GMII)
619 + goto unsupported;
620 + break;
621 + case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */
622 + if (mt7531_is_rgmii_port(priv, port))
623 + return phy_interface_mode_is_rgmii(state->interface);
624 + fallthrough;
625 + case 6: /* 1st cpu port supports sgmii/8023z only */
626 + if (state->interface != PHY_INTERFACE_MODE_SGMII &&
627 + !phy_interface_mode_is_8023z(state->interface))
628 + goto unsupported;
629 + break;
630 + default:
631 + dev_err(priv->dev, "%s: unsupported port: %i\n", __func__,
632 + port);
633 + goto unsupported;
634 + }
635 +
636 + return true;
637 +
638 +unsupported:
639 + return false;
640 +}
641 +
642 static bool
643 mt753x_phy_mode_supported(struct dsa_switch *ds, int port,
644 const struct phylink_link_state *state)
645 @@ -1414,6 +1906,227 @@ mt7530_mac_config(struct dsa_switch *ds,
646 return 0;
647 }
648
649 +static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port,
650 + phy_interface_t interface,
651 + struct phy_device *phydev)
652 +{
653 + u32 val;
654 +
655 + if (!mt7531_is_rgmii_port(priv, port)) {
656 + dev_err(priv->dev, "RGMII mode is not available for port %d\n",
657 + port);
658 + return -EINVAL;
659 + }
660 +
661 + val = mt7530_read(priv, MT7531_CLKGEN_CTRL);
662 + val |= GP_CLK_EN;
663 + val &= ~GP_MODE_MASK;
664 + val |= GP_MODE(MT7531_GP_MODE_RGMII);
665 + val &= ~CLK_SKEW_IN_MASK;
666 + val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG);
667 + val &= ~CLK_SKEW_OUT_MASK;
668 + val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG);
669 + val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY;
670 +
671 + /* Do not adjust rgmii delay when vendor phy driver presents. */
672 + if (!phydev || phy_driver_is_genphy(phydev)) {
673 + val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY);
674 + switch (interface) {
675 + case PHY_INTERFACE_MODE_RGMII:
676 + val |= TXCLK_NO_REVERSE;
677 + val |= RXCLK_NO_DELAY;
678 + break;
679 + case PHY_INTERFACE_MODE_RGMII_RXID:
680 + val |= TXCLK_NO_REVERSE;
681 + break;
682 + case PHY_INTERFACE_MODE_RGMII_TXID:
683 + val |= RXCLK_NO_DELAY;
684 + break;
685 + case PHY_INTERFACE_MODE_RGMII_ID:
686 + break;
687 + default:
688 + return -EINVAL;
689 + }
690 + }
691 + mt7530_write(priv, MT7531_CLKGEN_CTRL, val);
692 +
693 + return 0;
694 +}
695 +
696 +static void mt7531_sgmii_validate(struct mt7530_priv *priv, int port,
697 + unsigned long *supported)
698 +{
699 + /* Port5 supports ethier RGMII or SGMII.
700 + * Port6 supports SGMII only.
701 + */
702 + switch (port) {
703 + case 5:
704 + if (mt7531_is_rgmii_port(priv, port))
705 + break;
706 + fallthrough;
707 + case 6:
708 + phylink_set(supported, 1000baseX_Full);
709 + phylink_set(supported, 2500baseX_Full);
710 + phylink_set(supported, 2500baseT_Full);
711 + }
712 +}
713 +
714 +static void
715 +mt7531_sgmii_link_up_force(struct dsa_switch *ds, int port,
716 + unsigned int mode, phy_interface_t interface,
717 + int speed, int duplex)
718 +{
719 + struct mt7530_priv *priv = ds->priv;
720 + unsigned int val;
721 +
722 + /* For adjusting speed and duplex of SGMII force mode. */
723 + if (interface != PHY_INTERFACE_MODE_SGMII ||
724 + phylink_autoneg_inband(mode))
725 + return;
726 +
727 + /* SGMII force mode setting */
728 + val = mt7530_read(priv, MT7531_SGMII_MODE(port));
729 + val &= ~MT7531_SGMII_IF_MODE_MASK;
730 +
731 + switch (speed) {
732 + case SPEED_10:
733 + val |= MT7531_SGMII_FORCE_SPEED_10;
734 + break;
735 + case SPEED_100:
736 + val |= MT7531_SGMII_FORCE_SPEED_100;
737 + break;
738 + case SPEED_1000:
739 + val |= MT7531_SGMII_FORCE_SPEED_1000;
740 + break;
741 + }
742 +
743 + /* MT7531 SGMII 1G force mode can only work in full duplex mode,
744 + * no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not.
745 + */
746 + if ((speed == SPEED_10 || speed == SPEED_100) &&
747 + duplex != DUPLEX_FULL)
748 + val |= MT7531_SGMII_FORCE_HALF_DUPLEX;
749 +
750 + mt7530_write(priv, MT7531_SGMII_MODE(port), val);
751 +}
752 +
753 +static bool mt753x_is_mac_port(u32 port)
754 +{
755 + return (port == 5 || port == 6);
756 +}
757 +
758 +static int mt7531_sgmii_setup_mode_force(struct mt7530_priv *priv, u32 port,
759 + phy_interface_t interface)
760 +{
761 + u32 val;
762 +
763 + if (!mt753x_is_mac_port(port))
764 + return -EINVAL;
765 +
766 + mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port),
767 + MT7531_SGMII_PHYA_PWD);
768 +
769 + val = mt7530_read(priv, MT7531_PHYA_CTRL_SIGNAL3(port));
770 + val &= ~MT7531_RG_TPHY_SPEED_MASK;
771 + /* Setup 2.5 times faster clock for 2.5Gbps data speeds with 10B/8B
772 + * encoding.
773 + */
774 + val |= (interface == PHY_INTERFACE_MODE_2500BASEX) ?
775 + MT7531_RG_TPHY_SPEED_3_125G : MT7531_RG_TPHY_SPEED_1_25G;
776 + mt7530_write(priv, MT7531_PHYA_CTRL_SIGNAL3(port), val);
777 +
778 + mt7530_clear(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE);
779 +
780 + /* MT7531 SGMII 1G and 2.5G force mode can only work in full duplex
781 + * mode, no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not.
782 + */
783 + mt7530_rmw(priv, MT7531_SGMII_MODE(port),
784 + MT7531_SGMII_IF_MODE_MASK | MT7531_SGMII_REMOTE_FAULT_DIS,
785 + MT7531_SGMII_FORCE_SPEED_1000);
786 +
787 + mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0);
788 +
789 + return 0;
790 +}
791 +
792 +static int mt7531_sgmii_setup_mode_an(struct mt7530_priv *priv, int port,
793 + phy_interface_t interface)
794 +{
795 + if (!mt753x_is_mac_port(port))
796 + return -EINVAL;
797 +
798 + mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port),
799 + MT7531_SGMII_PHYA_PWD);
800 +
801 + mt7530_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port),
802 + MT7531_RG_TPHY_SPEED_MASK, MT7531_RG_TPHY_SPEED_1_25G);
803 +
804 + mt7530_set(priv, MT7531_SGMII_MODE(port),
805 + MT7531_SGMII_REMOTE_FAULT_DIS |
806 + MT7531_SGMII_SPEED_DUPLEX_AN);
807 +
808 + mt7530_rmw(priv, MT7531_PCS_SPEED_ABILITY(port),
809 + MT7531_SGMII_TX_CONFIG_MASK, 1);
810 +
811 + mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE);
812 +
813 + mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_RESTART);
814 +
815 + mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0);
816 +
817 + return 0;
818 +}
819 +
820 +static void mt7531_sgmii_restart_an(struct dsa_switch *ds, int port)
821 +{
822 + struct mt7530_priv *priv = ds->priv;
823 + u32 val;
824 +
825 + /* Only restart AN when AN is enabled */
826 + val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
827 + if (val & MT7531_SGMII_AN_ENABLE) {
828 + val |= MT7531_SGMII_AN_RESTART;
829 + mt7530_write(priv, MT7531_PCS_CONTROL_1(port), val);
830 + }
831 +}
832 +
833 +static int
834 +mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
835 + phy_interface_t interface)
836 +{
837 + struct mt7530_priv *priv = ds->priv;
838 + struct phy_device *phydev;
839 + const struct dsa_port *dp;
840 +
841 + if (!mt753x_is_mac_port(port)) {
842 + dev_err(priv->dev, "port %d is not a MAC port\n", port);
843 + return -EINVAL;
844 + }
845 +
846 + switch (interface) {
847 + case PHY_INTERFACE_MODE_RGMII:
848 + case PHY_INTERFACE_MODE_RGMII_ID:
849 + case PHY_INTERFACE_MODE_RGMII_RXID:
850 + case PHY_INTERFACE_MODE_RGMII_TXID:
851 + dp = dsa_to_port(ds, port);
852 + phydev = dp->slave->phydev;
853 + return mt7531_rgmii_setup(priv, port, interface, phydev);
854 + case PHY_INTERFACE_MODE_SGMII:
855 + return mt7531_sgmii_setup_mode_an(priv, port, interface);
856 + case PHY_INTERFACE_MODE_NA:
857 + case PHY_INTERFACE_MODE_1000BASEX:
858 + case PHY_INTERFACE_MODE_2500BASEX:
859 + if (phylink_autoneg_inband(mode))
860 + return -EINVAL;
861 +
862 + return mt7531_sgmii_setup_mode_force(priv, port, interface);
863 + default:
864 + return -EINVAL;
865 + }
866 +
867 + return -EINVAL;
868 +}
869 +
870 static int
871 mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
872 const struct phylink_link_state *state)
873 @@ -1449,6 +2162,8 @@ mt753x_phylink_mac_config(struct dsa_swi
874 if (mt753x_mac_config(ds, port, mode, state) < 0)
875 goto unsupported;
876
877 + if (priv->p5_intf_sel != P5_DISABLED)
878 + priv->p5_interface = state->interface;
879 break;
880 case 6: /* 1st cpu port */
881 if (priv->p6_interface == state->interface)
882 @@ -1468,7 +2183,8 @@ unsupported:
883 return;
884 }
885
886 - if (phylink_autoneg_inband(mode)) {
887 + if (phylink_autoneg_inband(mode) &&
888 + state->interface != PHY_INTERFACE_MODE_SGMII) {
889 dev_err(ds->dev, "%s: in-band negotiation unsupported\n",
890 __func__);
891 return;
892 @@ -1478,7 +2194,7 @@ unsupported:
893 mcr_new = mcr_cur;
894 mcr_new &= ~PMCR_LINK_SETTINGS_MASK;
895 mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN |
896 - PMCR_BACKPR_EN | PMCR_FORCE_MODE;
897 + PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id);
898
899 /* Are we connected to external phy */
900 if (port == 5 && dsa_is_user_port(ds, 5))
901 @@ -1488,7 +2204,18 @@ unsupported:
902 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new);
903 }
904
905 -static void mt7530_phylink_mac_link_down(struct dsa_switch *ds, int port,
906 +static void
907 +mt753x_phylink_mac_an_restart(struct dsa_switch *ds, int port)
908 +{
909 + struct mt7530_priv *priv = ds->priv;
910 +
911 + if (!priv->info->mac_pcs_an_restart)
912 + return;
913 +
914 + priv->info->mac_pcs_an_restart(ds, port);
915 +}
916 +
917 +static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port,
918 unsigned int mode,
919 phy_interface_t interface)
920 {
921 @@ -1497,7 +2224,19 @@ static void mt7530_phylink_mac_link_down
922 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
923 }
924
925 -static void mt7530_phylink_mac_link_up(struct dsa_switch *ds, int port,
926 +static void mt753x_mac_pcs_link_up(struct dsa_switch *ds, int port,
927 + unsigned int mode, phy_interface_t interface,
928 + int speed, int duplex)
929 +{
930 + struct mt7530_priv *priv = ds->priv;
931 +
932 + if (!priv->info->mac_pcs_link_up)
933 + return;
934 +
935 + priv->info->mac_pcs_link_up(ds, port, mode, interface, speed, duplex);
936 +}
937 +
938 +static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port,
939 unsigned int mode,
940 phy_interface_t interface,
941 struct phy_device *phydev,
942 @@ -1507,18 +2246,29 @@ static void mt7530_phylink_mac_link_up(s
943 struct mt7530_priv *priv = ds->priv;
944 u32 mcr;
945
946 + mt753x_mac_pcs_link_up(ds, port, mode, interface, speed, duplex);
947 +
948 mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
949
950 + /* MT753x MAC works in 1G full duplex mode for all up-clocked
951 + * variants.
952 + */
953 + if (interface == PHY_INTERFACE_MODE_TRGMII ||
954 + (phy_interface_mode_is_8023z(interface))) {
955 + speed = SPEED_1000;
956 + duplex = DUPLEX_FULL;
957 + }
958 +
959 switch (speed) {
960 case SPEED_1000:
961 mcr |= PMCR_FORCE_SPEED_1000;
962 if (priv->eee_enable & BIT(port))
963 - mcr_new |= PMCR_FORCE_EEE1G;
964 + mcr |= PMCR_FORCE_EEE1G;
965 break;
966 case SPEED_100:
967 mcr |= PMCR_FORCE_SPEED_100;
968 if (priv->eee_enable & BIT(port))
969 - mcr_new |= PMCR_FORCE_EEE100;
970 + mcr |= PMCR_FORCE_EEE100;
971 break;
972 }
973 if (duplex == DUPLEX_FULL) {
974 @@ -1532,6 +2282,45 @@ static void mt7530_phylink_mac_link_up(s
975 mt7530_set(priv, MT7530_PMCR_P(port), mcr);
976 }
977
978 +static int
979 +mt7531_cpu_port_config(struct dsa_switch *ds, int port)
980 +{
981 + struct mt7530_priv *priv = ds->priv;
982 + phy_interface_t interface;
983 + int speed;
984 +
985 + switch (port) {
986 + case 5:
987 + if (mt7531_is_rgmii_port(priv, port))
988 + interface = PHY_INTERFACE_MODE_RGMII;
989 + else
990 + interface = PHY_INTERFACE_MODE_2500BASEX;
991 +
992 + priv->p5_interface = interface;
993 + break;
994 + case 6:
995 + interface = PHY_INTERFACE_MODE_2500BASEX;
996 +
997 + mt7531_pad_setup(ds, interface);
998 +
999 + priv->p6_interface = interface;
1000 + break;
1001 + };
1002 +
1003 + if (interface == PHY_INTERFACE_MODE_2500BASEX)
1004 + speed = SPEED_2500;
1005 + else
1006 + speed = SPEED_1000;
1007 +
1008 + mt7531_mac_config(ds, port, MLO_AN_FIXED, interface);
1009 + mt7530_write(priv, MT7530_PMCR_P(port),
1010 + PMCR_CPU_PORT_SETTING(priv->id));
1011 + mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL,
1012 + speed, DUPLEX_FULL, true, true);
1013 +
1014 + return 0;
1015 +}
1016 +
1017 static void
1018 mt7530_mac_port_validate(struct dsa_switch *ds, int port,
1019 unsigned long *supported)
1020 @@ -1540,6 +2329,14 @@ mt7530_mac_port_validate(struct dsa_swit
1021 phylink_set(supported, 1000baseX_Full);
1022 }
1023
1024 +static void mt7531_mac_port_validate(struct dsa_switch *ds, int port,
1025 + unsigned long *supported)
1026 +{
1027 + struct mt7530_priv *priv = ds->priv;
1028 +
1029 + mt7531_sgmii_validate(priv, port, supported);
1030 +}
1031 +
1032 static void
1033 mt753x_phylink_validate(struct dsa_switch *ds, int port,
1034 unsigned long *supported,
1035 @@ -1556,7 +2353,8 @@ mt753x_phylink_validate(struct dsa_switc
1036
1037 phylink_set_port_modes(mask);
1038
1039 - if (state->interface != PHY_INTERFACE_MODE_TRGMII) {
1040 + if (state->interface != PHY_INTERFACE_MODE_TRGMII ||
1041 + !phy_interface_mode_is_8023z(state->interface)) {
1042 phylink_set(mask, 10baseT_Half);
1043 phylink_set(mask, 10baseT_Full);
1044 phylink_set(mask, 100baseT_Half);
1045 @@ -1575,6 +2373,11 @@ mt753x_phylink_validate(struct dsa_switc
1046
1047 linkmode_and(supported, supported, mask);
1048 linkmode_and(state->advertising, state->advertising, mask);
1049 +
1050 + /* We can only operate at 2500BaseX or 1000BaseX. If requested
1051 + * to advertise both, only report advertising at 2500BaseX.
1052 + */
1053 + phylink_helper_basex_speed(state);
1054 }
1055
1056 static int
1057 @@ -1665,6 +2468,63 @@ static int mt7530_set_mac_eee(struct dsa
1058 return 0;
1059 }
1060
1061 +#ifdef notyet
1062 +static int
1063 +mt7531_sgmii_pcs_get_state_an(struct mt7530_priv *priv, int port,
1064 + struct phylink_link_state *state)
1065 +{
1066 + u32 status, val;
1067 + u16 config_reg;
1068 +
1069 + status = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
1070 + state->link = !!(status & MT7531_SGMII_LINK_STATUS);
1071 + if (state->interface == PHY_INTERFACE_MODE_SGMII &&
1072 + (status & MT7531_SGMII_AN_ENABLE)) {
1073 + val = mt7530_read(priv, MT7531_PCS_SPEED_ABILITY(port));
1074 + config_reg = val >> 16;
1075 +
1076 + switch (config_reg & LPA_SGMII_SPD_MASK) {
1077 + case LPA_SGMII_1000:
1078 + state->speed = SPEED_1000;
1079 + break;
1080 + case LPA_SGMII_100:
1081 + state->speed = SPEED_100;
1082 + break;
1083 + case LPA_SGMII_10:
1084 + state->speed = SPEED_10;
1085 + break;
1086 + default:
1087 + dev_err(priv->dev, "invalid sgmii PHY speed\n");
1088 + state->link = false;
1089 + return -EINVAL;
1090 + }
1091 +
1092 + if (config_reg & LPA_SGMII_FULL_DUPLEX)
1093 + state->duplex = DUPLEX_FULL;
1094 + else
1095 + state->duplex = DUPLEX_HALF;
1096 + }
1097 +
1098 + return 0;
1099 +}
1100 +#endif
1101 +
1102 +static int
1103 +mt7531_phylink_mac_link_state(struct dsa_switch *ds, int port,
1104 + struct phylink_link_state *state)
1105 +{
1106 +#ifdef notyet
1107 + struct mt7530_priv *priv = ds->priv;
1108 +
1109 + if (state->interface == PHY_INTERFACE_MODE_SGMII)
1110 + return mt7531_sgmii_pcs_get_state_an(priv, port, state);
1111 +#else
1112 + return mt7530_phylink_mac_link_state(ds, port, state);
1113 +#endif
1114 +
1115 + return -EOPNOTSUPP;
1116 +}
1117 +
1118 static int
1119 mt753x_phylink_mac_link_state(struct dsa_switch *ds, int port,
1120 struct phylink_link_state *state)
1121 @@ -1718,13 +2578,14 @@ static const struct dsa_switch_ops mt753
1122 .port_vlan_prepare = mt7530_port_vlan_prepare,
1123 .port_vlan_add = mt7530_port_vlan_add,
1124 .port_vlan_del = mt7530_port_vlan_del,
1125 - .port_mirror_add = mt7530_port_mirror_add,
1126 - .port_mirror_del = mt7530_port_mirror_del,
1127 + .port_mirror_add = mt753x_port_mirror_add,
1128 + .port_mirror_del = mt753x_port_mirror_del,
1129 .phylink_validate = mt753x_phylink_validate,
1130 .phylink_mac_link_state = mt753x_phylink_mac_link_state,
1131 .phylink_mac_config = mt753x_phylink_mac_config,
1132 - .phylink_mac_link_down = mt7530_phylink_mac_link_down,
1133 - .phylink_mac_link_up = mt7530_phylink_mac_link_up,
1134 + .phylink_mac_an_restart = mt753x_phylink_mac_an_restart,
1135 + .phylink_mac_link_down = mt753x_phylink_mac_link_down,
1136 + .phylink_mac_link_up = mt753x_phylink_mac_link_up,
1137 .get_mac_eee = mt7530_get_mac_eee,
1138 .set_mac_eee = mt7530_set_mac_eee,
1139 };
1140 @@ -1752,11 +2613,26 @@ static const struct mt753x_info mt753x_t
1141 .mac_port_get_state = mt7530_phylink_mac_link_state,
1142 .mac_port_config = mt7530_mac_config,
1143 },
1144 + [ID_MT7531] = {
1145 + .id = ID_MT7531,
1146 + .sw_setup = mt7531_setup,
1147 + .phy_read = mt7531_ind_phy_read,
1148 + .phy_write = mt7531_ind_phy_write,
1149 + .pad_setup = mt7531_pad_setup,
1150 + .cpu_port_config = mt7531_cpu_port_config,
1151 + .phy_mode_supported = mt7531_phy_supported,
1152 + .mac_port_validate = mt7531_mac_port_validate,
1153 + .mac_port_get_state = mt7531_phylink_mac_link_state,
1154 + .mac_port_config = mt7531_mac_config,
1155 + .mac_pcs_an_restart = mt7531_sgmii_restart_an,
1156 + .mac_pcs_link_up = mt7531_sgmii_link_up_force,
1157 + },
1158 };
1159
1160 static const struct of_device_id mt7530_of_match[] = {
1161 { .compatible = "mediatek,mt7621", .data = &mt753x_table[ID_MT7621], },
1162 { .compatible = "mediatek,mt7530", .data = &mt753x_table[ID_MT7530], },
1163 + { .compatible = "mediatek,mt7531", .data = &mt753x_table[ID_MT7531], },
1164 { /* sentinel */ },
1165 };
1166 MODULE_DEVICE_TABLE(of, mt7530_of_match);
1167 --- a/drivers/net/dsa/mt7530.h
1168 +++ b/drivers/net/dsa/mt7530.h
1169 @@ -14,6 +14,7 @@
1170 enum mt753x_id {
1171 ID_MT7530 = 0,
1172 ID_MT7621 = 1,
1173 + ID_MT7531 = 2,
1174 };
1175
1176 #define NUM_TRGMII_CTRL 5
1177 @@ -41,6 +42,33 @@ enum mt753x_id {
1178 #define MIRROR_PORT(x) ((x) & 0x7)
1179 #define MIRROR_MASK 0x7
1180
1181 +/* Registers for CPU forward control */
1182 +#define MT7531_CFC 0x4
1183 +#define MT7531_MIRROR_EN BIT(19)
1184 +#define MT7531_MIRROR_MASK (MIRROR_MASK << 16)
1185 +#define MT7531_MIRROR_PORT_GET(x) (((x) >> 16) & MIRROR_MASK)
1186 +#define MT7531_MIRROR_PORT_SET(x) (((x) & MIRROR_MASK) << 16)
1187 +#define MT7531_CPU_PMAP_MASK GENMASK(7, 0)
1188 +
1189 +#define MT753X_MIRROR_REG(id) (((id) == ID_MT7531) ? \
1190 + MT7531_CFC : MT7530_MFC)
1191 +#define MT753X_MIRROR_EN(id) (((id) == ID_MT7531) ? \
1192 + MT7531_MIRROR_EN : MIRROR_EN)
1193 +#define MT753X_MIRROR_MASK(id) (((id) == ID_MT7531) ? \
1194 + MT7531_MIRROR_MASK : MIRROR_MASK)
1195 +
1196 +/* Registers for BPDU and PAE frame control*/
1197 +#define MT753X_BPC 0x24
1198 +#define MT753X_BPDU_PORT_FW_MASK GENMASK(2, 0)
1199 +
1200 +enum mt753x_bpdu_port_fw {
1201 + MT753X_BPDU_FOLLOW_MFC,
1202 + MT753X_BPDU_CPU_EXCLUDE = 4,
1203 + MT753X_BPDU_CPU_INCLUDE = 5,
1204 + MT753X_BPDU_CPU_ONLY = 6,
1205 + MT753X_BPDU_DROP = 7,
1206 +};
1207 +
1208 /* Registers for address table access */
1209 #define MT7530_ATA1 0x74
1210 #define STATIC_EMP 0
1211 @@ -222,10 +250,30 @@ enum mt7530_vlan_port_attr {
1212 #define PMCR_FORCE_LNK BIT(0)
1213 #define PMCR_SPEED_MASK (PMCR_FORCE_SPEED_100 | \
1214 PMCR_FORCE_SPEED_1000)
1215 +#define MT7531_FORCE_LNK BIT(31)
1216 +#define MT7531_FORCE_SPD BIT(30)
1217 +#define MT7531_FORCE_DPX BIT(29)
1218 +#define MT7531_FORCE_RX_FC BIT(28)
1219 +#define MT7531_FORCE_TX_FC BIT(27)
1220 +#define MT7531_FORCE_MODE (MT7531_FORCE_LNK | \
1221 + MT7531_FORCE_SPD | \
1222 + MT7531_FORCE_DPX | \
1223 + MT7531_FORCE_RX_FC | \
1224 + MT7531_FORCE_TX_FC)
1225 +#define PMCR_FORCE_MODE_ID(id) (((id) == ID_MT7531) ? \
1226 + MT7531_FORCE_MODE : \
1227 + PMCR_FORCE_MODE)
1228 #define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \
1229 PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \
1230 PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
1231 PMCR_FORCE_FDX | PMCR_FORCE_LNK)
1232 +#define PMCR_CPU_PORT_SETTING(id) (PMCR_FORCE_MODE_ID((id)) | \
1233 + PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | \
1234 + PMCR_BACKOFF_EN | PMCR_BACKPR_EN | \
1235 + PMCR_TX_EN | PMCR_RX_EN | \
1236 + PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
1237 + PMCR_FORCE_SPEED_1000 | \
1238 + PMCR_FORCE_FDX | PMCR_FORCE_LNK)
1239
1240 #define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100)
1241 #define PMSR_EEE1G BIT(7)
1242 @@ -245,6 +293,10 @@ enum mt7530_vlan_port_attr {
1243 #define LPI_THRESH(x) ((x & 0xFFF) << 4)
1244 #define LPI_MODE_EN BIT(0)
1245
1246 +/* Register for port debug count */
1247 +#define MT7531_DBG_CNT(x) (0x3018 + (x) * 0x100)
1248 +#define MT7531_DIS_CLR BIT(31)
1249 +
1250 /* Register for MIB */
1251 #define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100)
1252 #define MT7530_MIB_CCR 0x4fe0
1253 @@ -262,12 +314,118 @@ enum mt7530_vlan_port_attr {
1254 CCR_RX_OCT_CNT_BAD | \
1255 CCR_TX_OCT_CNT_GOOD | \
1256 CCR_TX_OCT_CNT_BAD)
1257 +
1258 +/* MT7531 SGMII register group */
1259 +#define MT7531_SGMII_REG_BASE 0x5000
1260 +#define MT7531_SGMII_REG(p, r) (MT7531_SGMII_REG_BASE + \
1261 + ((p) - 5) * 0x1000 + (r))
1262 +
1263 +/* Register forSGMII PCS_CONTROL_1 */
1264 +#define MT7531_PCS_CONTROL_1(p) MT7531_SGMII_REG(p, 0x00)
1265 +#define MT7531_SGMII_LINK_STATUS BIT(18)
1266 +#define MT7531_SGMII_AN_ENABLE BIT(12)
1267 +#define MT7531_SGMII_AN_RESTART BIT(9)
1268 +
1269 +/* Register for SGMII PCS_SPPED_ABILITY */
1270 +#define MT7531_PCS_SPEED_ABILITY(p) MT7531_SGMII_REG(p, 0x08)
1271 +#define MT7531_SGMII_TX_CONFIG_MASK GENMASK(15, 0)
1272 +#define MT7531_SGMII_TX_CONFIG BIT(0)
1273 +
1274 +/* Register for SGMII_MODE */
1275 +#define MT7531_SGMII_MODE(p) MT7531_SGMII_REG(p, 0x20)
1276 +#define MT7531_SGMII_REMOTE_FAULT_DIS BIT(8)
1277 +#define MT7531_SGMII_IF_MODE_MASK GENMASK(5, 1)
1278 +#define MT7531_SGMII_FORCE_DUPLEX BIT(4)
1279 +#define MT7531_SGMII_FORCE_SPEED_MASK GENMASK(3, 2)
1280 +#define MT7531_SGMII_FORCE_SPEED_1000 BIT(3)
1281 +#define MT7531_SGMII_FORCE_SPEED_100 BIT(2)
1282 +#define MT7531_SGMII_FORCE_SPEED_10 0
1283 +#define MT7531_SGMII_SPEED_DUPLEX_AN BIT(1)
1284 +
1285 +enum mt7531_sgmii_force_duplex {
1286 + MT7531_SGMII_FORCE_FULL_DUPLEX = 0,
1287 + MT7531_SGMII_FORCE_HALF_DUPLEX = 0x10,
1288 +};
1289 +
1290 +/* Fields of QPHY_PWR_STATE_CTRL */
1291 +#define MT7531_QPHY_PWR_STATE_CTRL(p) MT7531_SGMII_REG(p, 0xe8)
1292 +#define MT7531_SGMII_PHYA_PWD BIT(4)
1293 +
1294 +/* Values of SGMII SPEED */
1295 +#define MT7531_PHYA_CTRL_SIGNAL3(p) MT7531_SGMII_REG(p, 0x128)
1296 +#define MT7531_RG_TPHY_SPEED_MASK (BIT(2) | BIT(3))
1297 +#define MT7531_RG_TPHY_SPEED_1_25G 0x0
1298 +#define MT7531_RG_TPHY_SPEED_3_125G BIT(2)
1299 +
1300 /* Register for system reset */
1301 #define MT7530_SYS_CTRL 0x7000
1302 #define SYS_CTRL_PHY_RST BIT(2)
1303 #define SYS_CTRL_SW_RST BIT(1)
1304 #define SYS_CTRL_REG_RST BIT(0)
1305
1306 +/* Register for PHY Indirect Access Control */
1307 +#define MT7531_PHY_IAC 0x701C
1308 +#define MT7531_PHY_ACS_ST BIT(31)
1309 +#define MT7531_MDIO_REG_ADDR_MASK (0x1f << 25)
1310 +#define MT7531_MDIO_PHY_ADDR_MASK (0x1f << 20)
1311 +#define MT7531_MDIO_CMD_MASK (0x3 << 18)
1312 +#define MT7531_MDIO_ST_MASK (0x3 << 16)
1313 +#define MT7531_MDIO_RW_DATA_MASK (0xffff)
1314 +#define MT7531_MDIO_REG_ADDR(x) (((x) & 0x1f) << 25)
1315 +#define MT7531_MDIO_DEV_ADDR(x) (((x) & 0x1f) << 25)
1316 +#define MT7531_MDIO_PHY_ADDR(x) (((x) & 0x1f) << 20)
1317 +#define MT7531_MDIO_CMD(x) (((x) & 0x3) << 18)
1318 +#define MT7531_MDIO_ST(x) (((x) & 0x3) << 16)
1319 +
1320 +enum mt7531_phy_iac_cmd {
1321 + MT7531_MDIO_ADDR = 0,
1322 + MT7531_MDIO_WRITE = 1,
1323 + MT7531_MDIO_READ = 2,
1324 + MT7531_MDIO_READ_CL45 = 3,
1325 +};
1326 +
1327 +/* MDIO_ST: MDIO start field */
1328 +enum mt7531_mdio_st {
1329 + MT7531_MDIO_ST_CL45 = 0,
1330 + MT7531_MDIO_ST_CL22 = 1,
1331 +};
1332 +
1333 +#define MT7531_MDIO_CL22_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \
1334 + MT7531_MDIO_CMD(MT7531_MDIO_READ))
1335 +#define MT7531_MDIO_CL22_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \
1336 + MT7531_MDIO_CMD(MT7531_MDIO_WRITE))
1337 +#define MT7531_MDIO_CL45_ADDR (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \
1338 + MT7531_MDIO_CMD(MT7531_MDIO_ADDR))
1339 +#define MT7531_MDIO_CL45_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \
1340 + MT7531_MDIO_CMD(MT7531_MDIO_READ))
1341 +#define MT7531_MDIO_CL45_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \
1342 + MT7531_MDIO_CMD(MT7531_MDIO_WRITE))
1343 +
1344 +/* Register for RGMII clock phase */
1345 +#define MT7531_CLKGEN_CTRL 0x7500
1346 +#define CLK_SKEW_OUT(x) (((x) & 0x3) << 8)
1347 +#define CLK_SKEW_OUT_MASK GENMASK(9, 8)
1348 +#define CLK_SKEW_IN(x) (((x) & 0x3) << 6)
1349 +#define CLK_SKEW_IN_MASK GENMASK(7, 6)
1350 +#define RXCLK_NO_DELAY BIT(5)
1351 +#define TXCLK_NO_REVERSE BIT(4)
1352 +#define GP_MODE(x) (((x) & 0x3) << 1)
1353 +#define GP_MODE_MASK GENMASK(2, 1)
1354 +#define GP_CLK_EN BIT(0)
1355 +
1356 +enum mt7531_gp_mode {
1357 + MT7531_GP_MODE_RGMII = 0,
1358 + MT7531_GP_MODE_MII = 1,
1359 + MT7531_GP_MODE_REV_MII = 2
1360 +};
1361 +
1362 +enum mt7531_clk_skew {
1363 + MT7531_CLK_SKEW_NO_CHG = 0,
1364 + MT7531_CLK_SKEW_DLY_100PPS = 1,
1365 + MT7531_CLK_SKEW_DLY_200PPS = 2,
1366 + MT7531_CLK_SKEW_REVERSE = 3,
1367 +};
1368 +
1369 /* Register for hw trap status */
1370 #define MT7530_HWTRAP 0x7800
1371 #define HWTRAP_XTAL_MASK (BIT(10) | BIT(9))
1372 @@ -275,6 +433,16 @@ enum mt7530_vlan_port_attr {
1373 #define HWTRAP_XTAL_40MHZ (BIT(10))
1374 #define HWTRAP_XTAL_20MHZ (BIT(9))
1375
1376 +#define MT7531_HWTRAP 0x7800
1377 +#define HWTRAP_XTAL_FSEL_MASK BIT(7)
1378 +#define HWTRAP_XTAL_FSEL_25MHZ BIT(7)
1379 +#define HWTRAP_XTAL_FSEL_40MHZ 0
1380 +/* Unique fields of (M)HWSTRAP for MT7531 */
1381 +#define XTAL_FSEL_S 7
1382 +#define XTAL_FSEL_M BIT(7)
1383 +#define PHY_EN BIT(6)
1384 +#define CHG_STRAP BIT(8)
1385 +
1386 /* Register for hw trap modification */
1387 #define MT7530_MHWTRAP 0x7804
1388 #define MHWTRAP_PHY0_SEL BIT(20)
1389 @@ -289,14 +457,37 @@ enum mt7530_vlan_port_attr {
1390 #define MT7530_TOP_SIG_CTRL 0x7808
1391 #define TOP_SIG_CTRL_NORMAL (BIT(17) | BIT(16))
1392
1393 +#define MT7531_TOP_SIG_SR 0x780c
1394 +#define PAD_DUAL_SGMII_EN BIT(1)
1395 +#define PAD_MCM_SMI_EN BIT(0)
1396 +
1397 #define MT7530_IO_DRV_CR 0x7810
1398 #define P5_IO_CLK_DRV(x) ((x) & 0x3)
1399 #define P5_IO_DATA_DRV(x) (((x) & 0x3) << 4)
1400
1401 +#define MT7531_CHIP_REV 0x781C
1402 +
1403 +#define MT7531_PLLGP_EN 0x7820
1404 +#define EN_COREPLL BIT(2)
1405 +#define SW_CLKSW BIT(1)
1406 +#define SW_PLLGP BIT(0)
1407 +
1408 #define MT7530_P6ECR 0x7830
1409 #define P6_INTF_MODE_MASK 0x3
1410 #define P6_INTF_MODE(x) ((x) & 0x3)
1411
1412 +#define MT7531_PLLGP_CR0 0x78a8
1413 +#define RG_COREPLL_EN BIT(22)
1414 +#define RG_COREPLL_POSDIV_S 23
1415 +#define RG_COREPLL_POSDIV_M 0x3800000
1416 +#define RG_COREPLL_SDM_PCW_S 1
1417 +#define RG_COREPLL_SDM_PCW_M 0x3ffffe
1418 +#define RG_COREPLL_SDM_PCW_CHG BIT(0)
1419 +
1420 +/* Registers for RGMII and SGMII PLL clock */
1421 +#define MT7531_ANA_PLLGP_CR2 0x78b0
1422 +#define MT7531_ANA_PLLGP_CR5 0x78bc
1423 +
1424 /* Registers for TRGMII on the both side */
1425 #define MT7530_TRGMII_RCK_CTRL 0x7a00
1426 #define RX_RST BIT(31)
1427 @@ -335,10 +526,25 @@ enum mt7530_vlan_port_attr {
1428 #define MT7530_P5RGMIITXCR 0x7b04
1429 #define CSR_RGMII_TXC_CFG(x) ((x) & 0x1f)
1430
1431 +/* Registers for GPIO mode */
1432 +#define MT7531_GPIO_MODE0 0x7c0c
1433 +#define MT7531_GPIO0_MASK GENMASK(3, 0)
1434 +#define MT7531_GPIO0_INTERRUPT 1
1435 +
1436 +#define MT7531_GPIO_MODE1 0x7c10
1437 +#define MT7531_GPIO11_RG_RXD2_MASK GENMASK(15, 12)
1438 +#define MT7531_EXT_P_MDC_11 (2 << 12)
1439 +#define MT7531_GPIO12_RG_RXD3_MASK GENMASK(19, 16)
1440 +#define MT7531_EXT_P_MDIO_12 (2 << 16)
1441 +
1442 #define MT7530_CREV 0x7ffc
1443 #define CHIP_NAME_SHIFT 16
1444 #define MT7530_ID 0x7530
1445
1446 +#define MT7531_CREV 0x781C
1447 +#define CHIP_REV_M 0x0f
1448 +#define MT7531_ID 0x7531
1449 +
1450 /* Registers for core PLL access through mmd indirect */
1451 #define CORE_PLL_GROUP2 0x401
1452 #define RG_SYSPLL_EN_NORMAL BIT(15)
1453 @@ -355,6 +561,10 @@ enum mt7530_vlan_port_attr {
1454 #define RG_SYSPLL_DDSFBK_EN BIT(12)
1455 #define RG_SYSPLL_BIAS_EN BIT(11)
1456 #define RG_SYSPLL_BIAS_LPF_EN BIT(10)
1457 +#define MT7531_PHY_PLL_OFF BIT(5)
1458 +#define MT7531_PHY_PLL_BYPASS_MODE BIT(4)
1459 +
1460 +#define MT753X_CTRL_PHY_ADDR 0
1461
1462 #define CORE_PLL_GROUP5 0x404
1463 #define RG_LCDDS_PCW_NCPO1(x) ((x) & 0xffff)
1464 @@ -433,6 +643,7 @@ enum p5_interface_select {
1465 P5_INTF_SEL_PHY_P0,
1466 P5_INTF_SEL_PHY_P4,
1467 P5_INTF_SEL_GMAC5,
1468 + P5_INTF_SEL_GMAC5_SGMII,
1469 };
1470
1471 static const char *p5_intf_modes(unsigned int p5_interface)
1472 @@ -446,6 +657,8 @@ static const char *p5_intf_modes(unsigne
1473 return "PHY P4";
1474 case P5_INTF_SEL_GMAC5:
1475 return "GMAC5";
1476 + case P5_INTF_SEL_GMAC5_SGMII:
1477 + return "GMAC5_SGMII";
1478 default:
1479 return "unknown";
1480 }
1481 @@ -466,6 +679,10 @@ static const char *p5_intf_modes(unsigne
1482 * MAC port
1483 * @mac_port_config: Holding the way setting up the PHY attribute to a
1484 * certain MAC port
1485 + * @mac_pcs_an_restart Holding the way restarting PCS autonegotiation for a
1486 + * certain MAC port
1487 + * @mac_pcs_link_up: Holding the way setting up the PHY attribute to the pcs
1488 + * of the certain MAC port
1489 */
1490 struct mt753x_info {
1491 enum mt753x_id id;
1492 @@ -474,6 +691,7 @@ struct mt753x_info {
1493 int (*phy_read)(struct dsa_switch *ds, int port, int regnum);
1494 int (*phy_write)(struct dsa_switch *ds, int port, int regnum, u16 val);
1495 int (*pad_setup)(struct dsa_switch *ds, phy_interface_t interface);
1496 + int (*cpu_port_config)(struct dsa_switch *ds, int port);
1497 bool (*phy_mode_supported)(struct dsa_switch *ds, int port,
1498 const struct phylink_link_state *state);
1499 void (*mac_port_validate)(struct dsa_switch *ds, int port,
1500 @@ -483,6 +701,10 @@ struct mt753x_info {
1501 int (*mac_port_config)(struct dsa_switch *ds, int port,
1502 unsigned int mode,
1503 phy_interface_t interface);
1504 + void (*mac_pcs_an_restart)(struct dsa_switch *ds, int port);
1505 + void (*mac_pcs_link_up)(struct dsa_switch *ds, int port,
1506 + unsigned int mode, phy_interface_t interface,
1507 + int speed, int duplex);
1508 };
1509
1510 /* struct mt7530_priv - This is the main data structure for holding the state
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