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mediatek/ramips: remove an ethernet optimization patch that was reported to cause...
[openwrt/openwrt.git] / target / linux / mediatek / patches-5.4 / 0999-hnat.patch
1 --- a/drivers/net/ethernet/mediatek/Kconfig
2 +++ b/drivers/net/ethernet/mediatek/Kconfig
3 @@ -15,4 +15,8 @@ config NET_MEDIATEK_SOC
4 This driver supports the gigabit ethernet MACs in the
5 MediaTek SoC family.
6
7 +config NET_MEDIATEK_OFFLOAD
8 + def_bool NET_MEDIATEK_SOC
9 + depends on NET_MEDIATEK_SOC
10 +
11 endif #NET_VENDOR_MEDIATEK
12 --- a/drivers/net/ethernet/mediatek/Makefile
13 +++ b/drivers/net/ethernet/mediatek/Makefile
14 @@ -5,3 +5,4 @@
15
16 obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o
17 mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_eth_path.o
18 +mtk_eth-$(CONFIG_NET_MEDIATEK_OFFLOAD) += mtk_offload.o mtk_debugfs.o
19 --- /dev/null
20 +++ b/drivers/net/ethernet/mediatek/mtk_debugfs.c
21 @@ -0,0 +1,117 @@
22 +/* This program is free software; you can redistribute it and/or modify
23 + * it under the terms of the GNU General Public License as published by
24 + * the Free Software Foundation; version 2 of the License
25 + *
26 + * This program is distributed in the hope that it will be useful,
27 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
28 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29 + * GNU General Public License for more details.
30 + *
31 + * Copyright (C) 2014-2016 Sean Wang <sean.wang@mediatek.com>
32 + * Copyright (C) 2016-2017 John Crispin <blogic@openwrt.org>
33 + */
34 +
35 +#include "mtk_offload.h"
36 +
37 +static const char *mtk_foe_entry_state_str[] = {
38 + "INVALID",
39 + "UNBIND",
40 + "BIND",
41 + "FIN"
42 +};
43 +
44 +static const char *mtk_foe_packet_type_str[] = {
45 + "IPV4_HNAPT",
46 + "IPV4_HNAT",
47 + "IPV6_1T_ROUTE",
48 + "IPV4_DSLITE",
49 + "IPV6_3T_ROUTE",
50 + "IPV6_5T_ROUTE",
51 + "IPV6_6RD",
52 +};
53 +
54 +#define IPV4_HNAPT 0
55 +#define IPV4_HNAT 1
56 +#define IS_IPV4_HNAPT(x) (((x)->bfib1.pkt_type == IPV4_HNAPT) ? 1: 0)
57 +struct mtk_eth *_eth;
58 +#define es(entry) (mtk_foe_entry_state_str[entry->bfib1.state])
59 +//#define ei(entry, end) (MTK_PPE_TBL_SZ - (int)(end - entry))
60 +#define ei(entry, end) (MTK_PPE_ENTRY_CNT - (int)(end - entry))
61 +#define pt(entry) (mtk_foe_packet_type_str[entry->ipv4_hnapt.bfib1.pkt_type])
62 +
63 +static int mtk_ppe_debugfs_foe_show(struct seq_file *m, void *private)
64 +{
65 + struct mtk_eth *eth = _eth;
66 + struct mtk_foe_entry *entry, *end;
67 + int i = 0;
68 +
69 + entry = eth->foe_table;
70 + end = eth->foe_table + MTK_PPE_ENTRY_CNT;
71 +
72 + while (entry < end) {
73 + if (!entry->bfib1.state) {
74 +
75 + } else if (IS_IPV4_HNAPT(entry)) {
76 + __be32 saddr = htonl(entry->ipv4_hnapt.sip);
77 + __be32 daddr = htonl(entry->ipv4_hnapt.dip);
78 + __be32 nsaddr = htonl(entry->ipv4_hnapt.new_sip);
79 + __be32 ndaddr = htonl(entry->ipv4_hnapt.new_dip);
80 + unsigned char h_dest[ETH_ALEN];
81 + unsigned char h_source[ETH_ALEN];
82 +
83 + *((u32*) h_source) = swab32(entry->ipv4_hnapt.smac_hi);
84 + *((u16*) &h_source[4]) = swab16(entry->ipv4_hnapt.smac_lo);
85 + *((u32*) h_dest) = swab32(entry->ipv4_hnapt.dmac_hi);
86 + *((u16*) &h_dest[4]) = swab16(entry->ipv4_hnapt.dmac_lo);
87 + seq_printf(m,
88 + "(%x)0x%05x|state=%s|type=%s|"
89 + "%pI4:%d->%pI4:%d=>%pI4:%d->%pI4:%d|%pM=>%pM|"
90 + "etype=0x%04x|info1=0x%x|info2=0x%x|"
91 + "vlan1=%d|vlan2=%d\n",
92 + i,
93 + ei(entry, end), es(entry), pt(entry),
94 + &saddr, entry->ipv4_hnapt.sport,
95 + &daddr, entry->ipv4_hnapt.dport,
96 + &nsaddr, entry->ipv4_hnapt.new_sport,
97 + &ndaddr, entry->ipv4_hnapt.new_dport, h_source,
98 + h_dest, ntohs(entry->ipv4_hnapt.etype),
99 + entry->ipv4_hnapt.info_blk1,
100 + entry->ipv4_hnapt.info_blk2,
101 + entry->ipv4_hnapt.vlan1,
102 + entry->ipv4_hnapt.vlan2);
103 + } else
104 + seq_printf(m, "0x%05x state=%s\n",
105 + ei(entry, end), es(entry));
106 + entry++;
107 + i++;
108 + }
109 +
110 + return 0;
111 +}
112 +
113 +static int mtk_ppe_debugfs_foe_open(struct inode *inode, struct file *file)
114 +{
115 + return single_open(file, mtk_ppe_debugfs_foe_show, file->private_data);
116 +}
117 +
118 +static const struct file_operations mtk_ppe_debugfs_foe_fops = {
119 + .open = mtk_ppe_debugfs_foe_open,
120 + .read = seq_read,
121 + .llseek = seq_lseek,
122 + .release = single_release,
123 +};
124 +
125 +int mtk_ppe_debugfs_init(struct mtk_eth *eth)
126 +{
127 + struct dentry *root;
128 +
129 + _eth = eth;
130 +
131 + root = debugfs_create_dir("mtk_ppe", NULL);
132 + if (!root)
133 + return -ENOMEM;
134 +
135 + debugfs_create_file("all_entry", S_IRUGO, root, eth, &mtk_ppe_debugfs_foe_fops);
136 +
137 + return 0;
138 +}
139 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
140 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
141 @@ -19,6 +19,8 @@
142 #include <linux/interrupt.h>
143 #include <linux/pinctrl/devinfo.h>
144 #include <linux/phylink.h>
145 +#include <linux/netfilter.h>
146 +#include <net/netfilter/nf_flow_table.h>
147
148 #include "mtk_eth_soc.h"
149
150 @@ -1320,8 +1322,16 @@ static int mtk_poll_rx(struct napi_struc
151 (trxd.rxd2 & RX_DMA_VTAG))
152 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
153 RX_DMA_VID(trxd.rxd3));
154 - skb_record_rx_queue(skb, 0);
155 - napi_gro_receive(napi, skb);
156 +#ifdef CONFIG_NET_MEDIATEK_OFFLOAD
157 + if (mtk_offload_check_rx(eth, skb, trxd.rxd4) == 0) {
158 +#endif
159 + skb_record_rx_queue(skb, 0);
160 + napi_gro_receive(napi, skb);
161 +#ifdef CONFIG_NET_MEDIATEK_OFFLOAD
162 + } else {
163 + dev_kfree_skb(skb);
164 + }
165 +#endif
166
167 skip_rx:
168 ring->data[idx] = new_data;
169 @@ -2255,6 +2265,9 @@ static int mtk_open(struct net_device *d
170 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
171 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
172 refcount_set(&eth->dma_refcnt, 1);
173 +#ifdef CONFIG_NET_MEDIATEK_OFFLOAD
174 + mtk_ppe_probe(eth);
175 +#endif
176 }
177 else
178 refcount_inc(&eth->dma_refcnt);
179 @@ -2316,6 +2329,9 @@ static int mtk_stop(struct net_device *d
180
181 mtk_dma_free(eth);
182
183 +#ifdef CONFIG_NET_MEDIATEK_OFFLOAD
184 + mtk_ppe_remove(eth);
185 +#endif
186 return 0;
187 }
188
189 @@ -2829,6 +2845,27 @@ static int mtk_set_rxnfc(struct net_devi
190 return ret;
191 }
192
193 +#ifdef CONFIG_NET_MEDIATEK_OFFLOAD
194 +static int
195 +mtk_flow_offload(enum flow_offload_type type, struct flow_offload *flow,
196 + struct flow_offload_hw_path *src,
197 + struct flow_offload_hw_path *dest)
198 +{
199 + struct mtk_mac *mac = netdev_priv(src->dev);
200 + struct mtk_eth *eth = mac->hw;
201 +
202 + if (!eth->soc->offload_version)
203 + return -EINVAL;
204 +
205 + if (src->dev->base_addr != dest->dev->base_addr)
206 + return -EINVAL;
207 +
208 + mac = netdev_priv(src->dev);
209 +
210 + return mtk_flow_offload_add(eth, type, flow, src, dest);
211 +}
212 +#endif
213 +
214 static const struct ethtool_ops mtk_ethtool_ops = {
215 .get_link_ksettings = mtk_get_link_ksettings,
216 .set_link_ksettings = mtk_set_link_ksettings,
217 @@ -2860,6 +2897,9 @@ static const struct net_device_ops mtk_n
218 #ifdef CONFIG_NET_POLL_CONTROLLER
219 .ndo_poll_controller = mtk_poll_controller,
220 #endif
221 +#ifdef CONFIG_NET_MEDIATEK_OFFLOAD
222 + .ndo_flow_offload = mtk_flow_offload,
223 +#endif
224 };
225
226 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
227 @@ -3202,6 +3242,7 @@ static const struct mtk_soc_data mt7622_
228 .hw_features = MTK_HW_FEATURES,
229 .required_clks = MT7622_CLKS_BITMAP,
230 .required_pctl = false,
231 + .offload_version = MTK_OFFLOAD_V2,
232 };
233
234 static const struct mtk_soc_data mt7623_data = {
235 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
236 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
237 @@ -787,6 +787,13 @@ enum mkt_eth_capabilities {
238 MTK_MUX_U3_GMAC2_TO_QPHY | \
239 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA)
240
241 +enum mtk_flow_offload_version {
242 + MTK_OFFLOAD_NONE = 0,
243 + MTK_OFFLOAD_V1,
244 + MTK_OFFLOAD_V2,
245 + MTK_OFFLOAD_V3,
246 +};
247 +
248 /* struct mtk_eth_data - This is the structure holding all differences
249 * among various plaforms
250 * @ana_rgc3: The offset for register ANA_RGC3 related to
251 @@ -804,6 +811,7 @@ struct mtk_soc_data {
252 u32 required_clks;
253 bool required_pctl;
254 netdev_features_t hw_features;
255 + enum mtk_flow_offload_version offload_version;
256 };
257
258 /* currently no SoC has more than 2 macs */
259 @@ -829,6 +837,23 @@ struct mtk_sgmii {
260 u32 ana_rgc3;
261 };
262
263 +
264 +struct mib_entry {
265 + u32 byt_cnt_l;
266 + u16 byt_cnt_h;
267 + u32 pkt_cnt_l;
268 + u8 pkt_cnt_h;
269 + u8 resv0;
270 + u32 resv1;
271 +} __packed __aligned(4);
272 +
273 +struct hnat_accounting {
274 + u64 bytes;
275 + u64 packets;
276 +};
277 +
278 +
279 +
280 /* struct mtk_eth - This is the main datasructure for holding the state
281 * of the driver
282 * @dev: The device pointer
283 @@ -914,6 +939,16 @@ struct mtk_eth {
284 u32 tx_int_status_reg;
285 u32 rx_dma_l4_valid;
286 int ip_align;
287 +
288 + struct reset_control *rst_ppe;
289 + struct mtk_foe_entry *foe_table;
290 + dma_addr_t foe_table_phys;
291 + struct flow_offload __rcu **foe_flow_table;
292 +
293 + struct mib_entry *foe_mib_cpu;
294 + dma_addr_t foe_mib_dev;
295 + struct hnat_accounting *acct;
296 + bool per_flow_accounting;
297 };
298
299 /* struct mtk_mac - the structure that holds the info about the MACs of the
300 @@ -946,6 +981,7 @@ void mtk_stats_update_mac(struct mtk_mac
301
302 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);
303 u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
304 +u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg);
305
306 int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np,
307 u32 ana_rgc3);
308 @@ -958,4 +994,13 @@ int mtk_gmac_sgmii_path_setup(struct mtk
309 int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);
310 int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id);
311
312 +int mtk_ppe_probe(struct mtk_eth *eth);
313 +void mtk_ppe_remove(struct mtk_eth *eth);
314 +int mtk_flow_offload_add(struct mtk_eth *eth,
315 + enum flow_offload_type type,
316 + struct flow_offload *flow,
317 + struct flow_offload_hw_path *src,
318 + struct flow_offload_hw_path *dest);
319 +int mtk_offload_check_rx(struct mtk_eth *eth, struct sk_buff *skb, u32 rxd4);
320 +
321 #endif /* MTK_ETH_H */
322 --- /dev/null
323 +++ b/drivers/net/ethernet/mediatek/mtk_offload.c
324 @@ -0,0 +1,593 @@
325 +/* This program is free software; you can redistribute it and/or modify
326 + * it under the terms of the GNU General Public License as published by
327 + * the Free Software Foundation; version 2 of the License
328 + *
329 + * This program is distributed in the hope that it will be useful,
330 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
331 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
332 + * GNU General Public License for more details.
333 + *
334 + * Copyright (C) 2018 John Crispin <john@phrozen.org>
335 + */
336 +
337 +#include "mtk_offload.h"
338 +
339 +#define INVALID 0
340 +#define UNBIND 1
341 +#define BIND 2
342 +#define FIN 3
343 +
344 +#define IPV4_HNAPT 0
345 +#define IPV4_HNAT 1
346 +
347 +static u32
348 +mtk_flow_hash_v4(struct flow_offload_tuple *tuple)
349 +{
350 + u32 ports = ntohs(tuple->src_port) << 16 | ntohs(tuple->dst_port);
351 + u32 src = ntohl(tuple->dst_v4.s_addr);
352 + u32 dst = ntohl(tuple->src_v4.s_addr);
353 + u32 hash = (ports & src) | ((~ports) & dst);
354 + u32 hash_23_0 = hash & 0xffffff;
355 + u32 hash_31_24 = hash & 0xff000000;
356 +
357 + hash = ports ^ src ^ dst ^ ((hash_23_0 << 8) | (hash_31_24 >> 24));
358 + hash = ((hash & 0xffff0000) >> 16 ) ^ (hash & 0xfffff);
359 + hash &= 0x7ff;
360 + hash *= 2;;
361 +
362 + return hash;
363 +}
364 +
365 +static int
366 +mtk_foe_prepare_v4(struct mtk_foe_entry *entry,
367 + struct flow_offload_tuple *tuple,
368 + struct flow_offload_tuple *dest_tuple,
369 + struct flow_offload_hw_path *src,
370 + struct flow_offload_hw_path *dest)
371 +{
372 + int is_mcast = !!is_multicast_ether_addr(dest->eth_dest);
373 +
374 + if (tuple->l4proto == IPPROTO_UDP)
375 + entry->ipv4_hnapt.bfib1.udp = 1;
376 +
377 + entry->ipv4_hnapt.etype = htons(ETH_P_IP);
378 + entry->ipv4_hnapt.bfib1.pkt_type = IPV4_HNAPT;
379 + entry->ipv4_hnapt.iblk2.fqos = 0;
380 + entry->ipv4_hnapt.bfib1.ttl = 1;
381 + entry->ipv4_hnapt.bfib1.cah = 1;
382 + entry->ipv4_hnapt.bfib1.ka = 1;
383 + entry->ipv4_hnapt.iblk2.mcast = is_mcast;
384 + entry->ipv4_hnapt.iblk2.dscp = 0;
385 + entry->ipv4_hnapt.iblk2.port_mg = 0x3f;
386 + entry->ipv4_hnapt.iblk2.port_ag = 0x1f;
387 +#ifdef CONFIG_NET_MEDIATEK_HW_QOS
388 + entry->ipv4_hnapt.iblk2.qid = 1;
389 + entry->ipv4_hnapt.iblk2.fqos = 1;
390 +#endif
391 +#ifdef CONFIG_RALINK
392 + entry->ipv4_hnapt.iblk2.dp = 1;
393 + if ((dest->flags & FLOW_OFFLOAD_PATH_VLAN) && (dest->vlan_id > 1))
394 + entry->ipv4_hnapt.iblk2.qid += 8;
395 +#else
396 + entry->ipv4_hnapt.iblk2.dp = (dest->dev->name[3] - '0') + 1;
397 +#endif
398 +
399 + entry->ipv4_hnapt.sip = ntohl(tuple->src_v4.s_addr);
400 + entry->ipv4_hnapt.dip = ntohl(tuple->dst_v4.s_addr);
401 + entry->ipv4_hnapt.sport = ntohs(tuple->src_port);
402 + entry->ipv4_hnapt.dport = ntohs(tuple->dst_port);
403 +
404 + entry->ipv4_hnapt.new_sip = ntohl(dest_tuple->dst_v4.s_addr);
405 + entry->ipv4_hnapt.new_dip = ntohl(dest_tuple->src_v4.s_addr);
406 + entry->ipv4_hnapt.new_sport = ntohs(dest_tuple->dst_port);
407 + entry->ipv4_hnapt.new_dport = ntohs(dest_tuple->src_port);
408 +
409 + entry->bfib1.state = BIND;
410 +
411 + if (dest->flags & FLOW_OFFLOAD_PATH_PPPOE) {
412 + entry->bfib1.psn = 1;
413 + entry->ipv4_hnapt.etype = htons(ETH_P_PPP_SES);
414 + entry->ipv4_hnapt.pppoe_id = dest->pppoe_sid;
415 + }
416 +
417 + if (dest->flags & FLOW_OFFLOAD_PATH_VLAN) {
418 + entry->ipv4_hnapt.vlan1 = dest->vlan_id;
419 + entry->bfib1.vlan_layer = 1;
420 +
421 + switch (dest->vlan_proto) {
422 + case htons(ETH_P_8021Q):
423 + entry->ipv4_hnapt.bfib1.vpm = 1;
424 + break;
425 + case htons(ETH_P_8021AD):
426 + entry->ipv4_hnapt.bfib1.vpm = 2;
427 + break;
428 + default:
429 + return -EINVAL;
430 + }
431 + }
432 +
433 + return 0;
434 +}
435 +
436 +static void
437 +mtk_foe_set_mac(struct mtk_foe_entry *entry, u8 *smac, u8 *dmac)
438 +{
439 + entry->ipv4_hnapt.dmac_hi = swab32(*((u32*) dmac));
440 + entry->ipv4_hnapt.dmac_lo = swab16(*((u16*) &dmac[4]));
441 + entry->ipv4_hnapt.smac_hi = swab32(*((u32*) smac));
442 + entry->ipv4_hnapt.smac_lo = swab16(*((u16*) &smac[4]));
443 +}
444 +
445 +static int
446 +mtk_check_entry_available(struct mtk_eth *eth, u32 hash)
447 +{
448 + struct mtk_foe_entry entry = ((struct mtk_foe_entry *)eth->foe_table)[hash];
449 +
450 + return (entry.bfib1.state == BIND)? 0:1;
451 +}
452 +
453 +static void
454 +mtk_foe_write(struct mtk_eth *eth, u32 hash,
455 + struct mtk_foe_entry *entry)
456 +{
457 + struct mtk_foe_entry *table = (struct mtk_foe_entry *)eth->foe_table;
458 +
459 + memcpy(&table[hash], entry, sizeof(*entry));
460 +}
461 +
462 +int mtk_flow_offload_add(struct mtk_eth *eth,
463 + enum flow_offload_type type,
464 + struct flow_offload *flow,
465 + struct flow_offload_hw_path *src,
466 + struct flow_offload_hw_path *dest)
467 +{
468 + struct flow_offload_tuple *otuple = &flow->tuplehash[FLOW_OFFLOAD_DIR_ORIGINAL].tuple;
469 + struct flow_offload_tuple *rtuple = &flow->tuplehash[FLOW_OFFLOAD_DIR_REPLY].tuple;
470 + u32 time_stamp = mtk_r32(eth, 0x0010) & (0x7fff);
471 + u32 ohash, rhash;
472 + struct mtk_foe_entry orig = {
473 + .bfib1.time_stamp = time_stamp,
474 + .bfib1.psn = 0,
475 + };
476 + struct mtk_foe_entry reply = {
477 + .bfib1.time_stamp = time_stamp,
478 + .bfib1.psn = 0,
479 + };
480 +
481 + if (otuple->l4proto != IPPROTO_TCP && otuple->l4proto != IPPROTO_UDP)
482 + return -EINVAL;
483 +
484 + if (type == FLOW_OFFLOAD_DEL) {
485 + flow = NULL;
486 + synchronize_rcu();
487 + return 0;
488 + }
489 +
490 + switch (otuple->l3proto) {
491 + case AF_INET:
492 + if (mtk_foe_prepare_v4(&orig, otuple, rtuple, src, dest) ||
493 + mtk_foe_prepare_v4(&reply, rtuple, otuple, dest, src))
494 + return -EINVAL;
495 +
496 + ohash = mtk_flow_hash_v4(otuple);
497 + rhash = mtk_flow_hash_v4(rtuple);
498 + break;
499 +
500 + case AF_INET6:
501 + return -EINVAL;
502 +
503 + default:
504 + return -EINVAL;
505 + }
506 +
507 + /* Two-way hash: when hash collision occurs, the hash value will be shifted to the next position. */
508 + if (!mtk_check_entry_available(eth, ohash)){
509 + if (!mtk_check_entry_available(eth, ohash + 1))
510 + return -EINVAL;
511 + ohash += 1;
512 + }
513 + if (!mtk_check_entry_available(eth, rhash)){
514 + if (!mtk_check_entry_available(eth, rhash + 1))
515 + return -EINVAL;
516 + rhash += 1;
517 + }
518 +
519 + mtk_foe_set_mac(&orig, dest->eth_src, dest->eth_dest);
520 + mtk_foe_set_mac(&reply, src->eth_src, src->eth_dest);
521 + mtk_foe_write(eth, ohash, &orig);
522 + mtk_foe_write(eth, rhash, &reply);
523 + rcu_assign_pointer(eth->foe_flow_table[ohash], flow);
524 + rcu_assign_pointer(eth->foe_flow_table[rhash], flow);
525 +
526 + return 0;
527 +}
528 +
529 +#ifdef CONFIG_NET_MEDIATEK_HW_QOS
530 +
531 +#define QDMA_TX_SCH_TX 0x1a14
532 +
533 +static void mtk_ppe_scheduler(struct mtk_eth *eth, int id, u32 rate)
534 +{
535 + int exp = 0, shift = 0;
536 + u32 reg = mtk_r32(eth, QDMA_TX_SCH_TX);
537 + u32 val = 0;
538 +
539 + if (rate)
540 + val = BIT(11);
541 +
542 + while (rate > 127) {
543 + rate /= 10;
544 + exp++;
545 + }
546 +
547 + val |= (rate & 0x7f) << 4;
548 + val |= exp & 0xf;
549 + if (id)
550 + shift = 16;
551 + reg &= ~(0xffff << shift);
552 + reg |= val << shift;
553 + mtk_w32(eth, val, QDMA_TX_SCH_TX);
554 +}
555 +
556 +#define QTX_CFG(x) (0x1800 + (x * 0x10))
557 +#define QTX_SCH(x) (0x1804 + (x * 0x10))
558 +
559 +static void mtk_ppe_queue(struct mtk_eth *eth, int id, int sched, int weight, int resv, u32 min_rate, u32 max_rate)
560 +{
561 + int max_exp = 0, min_exp = 0;
562 + u32 reg;
563 +
564 + if (id >= 16)
565 + return;
566 +
567 + reg = mtk_r32(eth, QTX_SCH(id));
568 + reg &= 0x70000000;
569 +
570 + if (sched)
571 + reg |= BIT(31);
572 +
573 + if (min_rate)
574 + reg |= BIT(27);
575 +
576 + if (max_rate)
577 + reg |= BIT(11);
578 +
579 + while (max_rate > 127) {
580 + max_rate /= 10;
581 + max_exp++;
582 + }
583 +
584 + while (min_rate > 127) {
585 + min_rate /= 10;
586 + min_exp++;
587 + }
588 +
589 + reg |= (min_rate & 0x7f) << 20;
590 + reg |= (min_exp & 0xf) << 16;
591 + reg |= (weight & 0xf) << 12;
592 + reg |= (max_rate & 0x7f) << 4;
593 + reg |= max_exp & 0xf;
594 + mtk_w32(eth, reg, QTX_SCH(id));
595 +
596 + resv &= 0xff;
597 + reg = mtk_r32(eth, QTX_CFG(id));
598 + reg &= 0xffff0000;
599 + reg |= (resv << 8) | resv;
600 + mtk_w32(eth, reg, QTX_CFG(id));
601 +}
602 +#endif
603 +
604 +static int mtk_init_foe_table(struct mtk_eth *eth)
605 +{
606 + if (eth->foe_table)
607 + return 0;
608 +
609 + eth->foe_flow_table = devm_kcalloc(eth->dev, MTK_PPE_ENTRY_CNT,
610 + sizeof(*eth->foe_flow_table),
611 + GFP_KERNEL);
612 + if (!eth->foe_flow_table)
613 + return -EINVAL;
614 +
615 + /* map the FOE table */
616 + eth->foe_table = dmam_alloc_coherent(eth->dev, MTK_PPE_TBL_SZ,
617 + &eth->foe_table_phys, GFP_KERNEL);
618 + if (!eth->foe_table) {
619 + dev_err(eth->dev, "failed to allocate foe table\n");
620 + kfree(eth->foe_flow_table);
621 + return -ENOMEM;
622 + }
623 +
624 +
625 + return 0;
626 +}
627 +
628 +static int mtk_ppe_start(struct mtk_eth *eth)
629 +{
630 + u32 foe_mib_tb_sz;
631 + u32 foe_etry_num = MTK_PPE_ENTRY_CNT;
632 +
633 + int ret;
634 +
635 + ret = mtk_init_foe_table(eth);
636 + if (ret)
637 + return ret;
638 +
639 + /* tell the PPE about the tables base address */
640 + mtk_w32(eth, eth->foe_table_phys, MTK_REG_PPE_TB_BASE);
641 +
642 + /* flush the table */
643 + memset(eth->foe_table, 0, MTK_PPE_TBL_SZ);
644 +
645 + eth->per_flow_accounting = false; //true;
646 +
647 + if (eth->per_flow_accounting) {
648 + foe_mib_tb_sz = foe_etry_num * sizeof(struct mib_entry);
649 + eth->foe_mib_cpu = dma_alloc_coherent(eth->dev, foe_mib_tb_sz,
650 + &eth->foe_mib_dev, GFP_KERNEL);
651 + if (!eth->foe_mib_cpu)
652 + return -1;
653 + mtk_w32(eth, eth->foe_mib_dev, MTK_REG_PPE_MIB_TB_BASE);
654 + memset(eth->foe_mib_cpu, 0, foe_mib_tb_sz);
655 +
656 + eth->acct =
657 + kzalloc(foe_etry_num * sizeof(struct hnat_accounting),
658 + GFP_KERNEL);
659 + if (!eth->acct)
660 + return -1;
661 + }
662 +
663 + /* setup hashing */
664 + mtk_m32(eth,
665 + MTK_PPE_TB_CFG_HASH_MODE_MASK | MTK_PPE_TB_CFG_TBL_SZ_MASK,
666 + MTK_PPE_TB_CFG_HASH_MODE1 | MTK_PPE_TB_CFG_TBL_SZ_4K,
667 + MTK_REG_PPE_TB_CFG);
668 +
669 + /* set the default hashing seed */
670 + mtk_w32(eth, MTK_PPE_HASH_SEED, MTK_REG_PPE_HASH_SEED);
671 +
672 + /* each foe entry is 80bytes and is setup by cpu forwarding*/
673 + mtk_m32(eth, MTK_PPE_CAH_CTRL_X_MODE | MTK_PPE_TB_CFG_ENTRY_SZ_MASK |
674 + MTK_PPE_TB_CFG_SMA_MASK,
675 + MTK_PPE_TB_CFG_ENTRY_SZ_64B | MTK_PPE_TB_CFG_SMA_FWD_CPU,
676 + MTK_REG_PPE_TB_CFG);
677 +
678 + /* set ip proto */
679 + //writel(0xFFFFFFFF, host->ppe_base + PPE_IP_PROT_CHK);
680 + mtk_w32(eth, 0xFFFFFFFF, MTK_REG_PPE_IP_PROT_CHK);
681 +
682 + /* setup caching */
683 + // cr_set_field(host->ppe_base + PPE_CAH_CTRL, CAH_X_MODE, 1);
684 + mtk_m32(eth, 1, MTK_PPE_CAH_CTRL_X_MODE, MTK_REG_PPE_CAH_CTRL);
685 + // cr_set_field(host->ppe_base + PPE_CAH_CTRL, CAH_X_MODE, 0);
686 + mtk_m32(eth, 0, MTK_PPE_CAH_CTRL_X_MODE, MTK_REG_PPE_CAH_CTRL);
687 + // cr_set_field(host->ppe_base + PPE_CAH_CTRL, CAH_EN, 1);
688 + mtk_m32(eth, MTK_PPE_CAH_CTRL_X_MODE, MTK_PPE_CAH_CTRL_EN,
689 + MTK_REG_PPE_CAH_CTRL);
690 +
691 + /* enable FOE */
692 + /* cr_set_bits(host->ppe_base + PPE_FLOW_CFG,
693 + BIT_UDP_IP4F_NAT_EN | BIT_IPV4_NAT_EN | BIT_IPV4_NAPT_EN |
694 + BIT_IPV4_NAT_FRAG_EN | BIT_IPV4_HASH_GREK |
695 + BIT_IPV4_DSL_EN | BIT_IPV6_6RD_EN |
696 + BIT_IPV6_3T_ROUTE_EN | BIT_IPV6_5T_ROUTE_EN); */
697 + mtk_m32(eth, 0, MTK_PPE_FLOW_CFG_IPV4_NAT_FRAG_EN |
698 + MTK_PPE_FLOW_CFG_IPV4_NAPT_EN | MTK_PPE_FLOW_CFG_IPV4_NAT_EN |
699 + MTK_PPE_FLOW_CFG_IPV4_GREK_EN,
700 + MTK_REG_PPE_FLOW_CFG);
701 +
702 + mtk_w32(eth, 0x000a7780, MTK_REG_PPE_FLOW_CFG);
703 +
704 + /* setup flow entry un/bind aging */
705 + // cr_set_field(host->ppe_base + PPE_TB_CFG, NTU_AGE, 1);
706 + // cr_set_field(host->ppe_base + PPE_TB_CFG, UNBD_AGE, 1);
707 + // cr_set_field(host->ppe_base + PPE_TB_CFG, TCP_AGE, 1);
708 + // cr_set_field(host->ppe_base + PPE_TB_CFG, UDP_AGE, 1);
709 + // cr_set_field(host->ppe_base + PPE_TB_CFG, FIN_AGE, 1);
710 + mtk_m32(eth, 0,
711 + MTK_PPE_TB_CFG_UNBD_AGE | MTK_PPE_TB_CFG_NTU_AGE |
712 + MTK_PPE_TB_CFG_FIN_AGE | MTK_PPE_TB_CFG_UDP_AGE |
713 + MTK_PPE_TB_CFG_TCP_AGE,
714 + MTK_REG_PPE_TB_CFG);
715 +
716 + // cr_set_field(host->ppe_base + PPE_UNB_AGE, UNB_MNP, 1000);
717 + // cr_set_field(host->ppe_base + PPE_UNB_AGE, UNB_DLTA, 3);
718 + mtk_m32(eth, MTK_PPE_UNB_AGE_MNP_MASK | MTK_PPE_UNB_AGE_DLTA_MASK,
719 + MTK_PPE_UNB_AGE_MNP | MTK_PPE_UNB_AGE_DLTA,
720 + MTK_REG_PPE_UNB_AGE);
721 +
722 + // cr_set_field(host->ppe_base + PPE_BND_AGE_0, UDP_DLTA, 12);
723 + // cr_set_field(host->ppe_base + PPE_BND_AGE_0, NTU_DLTA, 1);
724 + mtk_m32(eth, MTK_PPE_BND_AGE0_NTU_DLTA_MASK |
725 + MTK_PPE_BND_AGE0_UDP_DLTA_MASK,
726 + MTK_PPE_BND_AGE0_NTU_DLTA | MTK_PPE_BND_AGE0_UDP_DLTA,
727 + MTK_REG_PPE_BND_AGE0);
728 + mtk_w32(eth, 0x0001000c, MTK_REG_PPE_BND_AGE0);
729 +
730 + // cr_set_field(host->ppe_base + PPE_BND_AGE_1, FIN_DLTA, 1);
731 + // cr_set_field(host->ppe_base + PPE_BND_AGE_1, TCP_DLTA, 7);
732 + mtk_m32(eth, MTK_PPE_BND_AGE1_FIN_DLTA_MASK |
733 + MTK_PPE_BND_AGE1_TCP_DLTA_MASK,
734 + MTK_PPE_BND_AGE1_FIN_DLTA | MTK_PPE_BND_AGE1_TCP_DLTA,
735 + MTK_REG_PPE_BND_AGE1);
736 + mtk_w32(eth, 0x00010007, MTK_REG_PPE_BND_AGE1);
737 +
738 + /* setup flow entry keep alive */
739 + // cr_set_field(host->ppe_base + PPE_TB_CFG, SCAN_MODE, 2);
740 + // cr_set_field(host->ppe_base + PPE_TB_CFG, KA_CFG, 3);
741 + mtk_m32(eth, MTK_PPE_TB_CFG_KA_MASK | MTK_PPE_TB_CFG_SCAN_MODE_MASK,
742 + MTK_PPE_TB_CFG_KA | MTK_PPE_TB_CFG_SCAN_MODE,
743 + MTK_REG_PPE_TB_CFG);
744 + // cr_set_field(host->ppe_base + PPE_KA, KA_T, 1);
745 + // cr_set_field(host->ppe_base + PPE_KA, TCP_KA, 1);
746 + // cr_set_field(host->ppe_base + PPE_KA, UDP_KA, 1);
747 + mtk_w32(eth, MTK_PPE_KA_UDP | MTK_PPE_KA_TCP | MTK_PPE_KA_T, MTK_REG_PPE_KA);
748 +
749 + /* setup flow entry rate limit */
750 + mtk_w32(eth, (0x3fff << 16) | 0x3fff, MTK_REG_PPE_BIND_LMT_0);
751 + mtk_w32(eth, 0x2000000 | MTK_PPE_NTU_KA | 0x3fff, MTK_REG_PPE_BIND_LMT_1);
752 + /* 30 packets per second */
753 + mtk_m32(eth, MTK_PPE_BNDR_RATE_MASK, 0x1e, MTK_REG_PPE_BNDR);
754 +
755 + /* enable the PPE */
756 + mtk_m32(eth, 0, MTK_PPE_GLO_CFG_EN, MTK_REG_PPE_GLO_CFG);
757 +
758 + /* set the default forwarding port to PDMA */
759 + mtk_w32(eth, 0x0, MTK_REG_PPE_DFT_CPORT);
760 +
761 + /* disallow packets with TTL=0 */
762 + mtk_m32(eth, 0, MTK_PPE_GLO_CFG_TTL0_DROP, MTK_REG_PPE_GLO_CFG);
763 +
764 + /*enable ppe mib counter*/
765 + if (eth->per_flow_accounting) {
766 + mtk_w32(eth, 0x3, MTK_REG_PPE_MIB_CFG);
767 + mtk_w32(eth, 0x3, MTK_REG_PPE_MIB_CAH_CTRL);
768 + }
769 +
770 + /* send all traffic from gmac to the ppe */
771 + mtk_m32(eth, 0xffff, 0x4444, MTK_GDMA_FWD_CFG(0));
772 + mtk_m32(eth, 0xffff, 0x4444, MTK_GDMA_FWD_CFG(1));
773 +
774 + mtk_w32(eth, 0x00027fb4, MTK_REG_PPE_TB_CFG);
775 +
776 + dev_info(eth->dev, "PPE started\n");
777 +
778 +#ifdef CONFIG_NET_MEDIATEK_HW_QOS
779 + mtk_ppe_scheduler(eth, 0, 500000);
780 + mtk_ppe_scheduler(eth, 1, 500000);
781 + mtk_ppe_queue(eth, 0, 0, 7, 32, 250000, 0);
782 + mtk_ppe_queue(eth, 1, 0, 7, 32, 250000, 0);
783 + mtk_ppe_queue(eth, 8, 1, 7, 32, 250000, 0);
784 + mtk_ppe_queue(eth, 9, 1, 7, 32, 250000, 0);
785 +#endif
786 +
787 + return 0;
788 +}
789 +
790 +static int mtk_ppe_busy_wait(struct mtk_eth *eth)
791 +{
792 + unsigned long t_start = jiffies;
793 + u32 r = 0;
794 +
795 + while (1) {
796 + r = mtk_r32(eth, MTK_REG_PPE_GLO_CFG);
797 + if (!(r & MTK_PPE_GLO_CFG_BUSY))
798 + return 0;
799 + if (time_after(jiffies, t_start + HZ))
800 + break;
801 + usleep_range(10, 20);
802 + }
803 +
804 + dev_err(eth->dev, "ppe: table busy timeout - resetting\n");
805 + reset_control_reset(eth->rst_ppe);
806 +
807 + return -ETIMEDOUT;
808 +}
809 +
810 +static int mtk_ppe_stop(struct mtk_eth *eth)
811 +{
812 + u32 r1 = 0, r2 = 0;
813 + int i;
814 +
815 + /* discard all traffic while we disable the PPE */
816 + mtk_m32(eth, 0xffff, 0x7777, MTK_GDMA_FWD_CFG(0));
817 + mtk_m32(eth, 0xffff, 0x7777, MTK_GDMA_FWD_CFG(1));
818 +
819 + if (mtk_ppe_busy_wait(eth))
820 + return -ETIMEDOUT;
821 +
822 + /* invalidate all flow table entries */
823 + for (i = 0; i < MTK_PPE_ENTRY_CNT; i++)
824 + eth->foe_table[i].bfib1.state = FOE_STATE_INVALID;
825 +
826 + /* disable caching */
827 + mtk_m32(eth, 0, MTK_PPE_CAH_CTRL_X_MODE, MTK_REG_PPE_CAH_CTRL);
828 + mtk_m32(eth, MTK_PPE_CAH_CTRL_X_MODE | MTK_PPE_CAH_CTRL_EN, 0,
829 + MTK_REG_PPE_CAH_CTRL);
830 +
831 + /* flush cache has to be ahead of hnat diable --*/
832 + mtk_m32(eth, MTK_PPE_GLO_CFG_EN, 0, MTK_REG_PPE_GLO_CFG);
833 +
834 + /* disable FOE */
835 + mtk_m32(eth,
836 + MTK_PPE_FLOW_CFG_IPV4_NAT_FRAG_EN |
837 + MTK_PPE_FLOW_CFG_IPV4_NAPT_EN | MTK_PPE_FLOW_CFG_IPV4_NAT_EN |
838 + MTK_PPE_FLOW_CFG_FUC_FOE | MTK_PPE_FLOW_CFG_FMC_FOE,
839 + 0, MTK_REG_PPE_FLOW_CFG);
840 +
841 + /* disable FOE aging */
842 + mtk_m32(eth, 0,
843 + MTK_PPE_TB_CFG_FIN_AGE | MTK_PPE_TB_CFG_UDP_AGE |
844 + MTK_PPE_TB_CFG_TCP_AGE | MTK_PPE_TB_CFG_UNBD_AGE |
845 + MTK_PPE_TB_CFG_NTU_AGE, MTK_REG_PPE_TB_CFG);
846 +
847 + r1 = mtk_r32(eth, 0x100);
848 + r2 = mtk_r32(eth, 0x10c);
849 +
850 + dev_info(eth->dev, "0x100 = 0x%x, 0x10c = 0x%x\n", r1, r2);
851 +
852 + if (((r1 & 0xff00) >> 0x8) >= (r1 & 0xff) ||
853 + ((r1 & 0xff00) >> 0x8) >= (r2 & 0xff)) {
854 + dev_info(eth->dev, "reset pse\n");
855 + mtk_w32(eth, 0x1, 0x4);
856 + }
857 +
858 + /* set the foe entry base address to 0 */
859 + mtk_w32(eth, 0, MTK_REG_PPE_TB_BASE);
860 +
861 + if (mtk_ppe_busy_wait(eth))
862 + return -ETIMEDOUT;
863 +
864 + /* send all traffic back to the DMA engine */
865 + mtk_m32(eth, 0xffff, 0x0, MTK_GDMA_FWD_CFG(0));
866 + mtk_m32(eth, 0xffff, 0x0, MTK_GDMA_FWD_CFG(1));
867 + return 0;
868 +}
869 +
870 +static void mtk_offload_keepalive(struct mtk_eth *eth, unsigned int hash)
871 +{
872 + struct flow_offload *flow;
873 +
874 + rcu_read_lock();
875 + flow = rcu_dereference(eth->foe_flow_table[hash]);
876 + if (flow)
877 + flow->timeout = jiffies + 30 * HZ;
878 + rcu_read_unlock();
879 +}
880 +
881 +int mtk_offload_check_rx(struct mtk_eth *eth, struct sk_buff *skb, u32 rxd4)
882 +{
883 + unsigned int hash;
884 +
885 + switch (FIELD_GET(MTK_RXD4_CPU_REASON, rxd4)) {
886 + case MTK_CPU_REASON_KEEPALIVE_UC_OLD_HDR:
887 + case MTK_CPU_REASON_KEEPALIVE_MC_NEW_HDR:
888 + case MTK_CPU_REASON_KEEPALIVE_DUP_OLD_HDR:
889 + hash = FIELD_GET(MTK_RXD4_FOE_ENTRY, rxd4);
890 + mtk_offload_keepalive(eth, hash);
891 + return -1;
892 + case MTK_CPU_REASON_PACKET_SAMPLING:
893 + return -1;
894 + default:
895 + return 0;
896 + }
897 +}
898 +
899 +int mtk_ppe_probe(struct mtk_eth *eth)
900 +{
901 + int err;
902 +
903 + err = mtk_ppe_start(eth);
904 + if (err)
905 + return err;
906 +
907 + err = mtk_ppe_debugfs_init(eth);
908 + if (err)
909 + return err;
910 +
911 + return 0;
912 +}
913 +
914 +void mtk_ppe_remove(struct mtk_eth *eth)
915 +{
916 + mtk_ppe_stop(eth);
917 +}
918 --- /dev/null
919 +++ b/drivers/net/ethernet/mediatek/mtk_offload.h
920 @@ -0,0 +1,298 @@
921 +/* This program is free software; you can redistribute it and/or modify
922 + * it under the terms of the GNU General Public License as published by
923 + * the Free Software Foundation; version 2 of the License
924 + *
925 + * This program is distributed in the hope that it will be useful,
926 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
927 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
928 + * GNU General Public License for more details.
929 + *
930 + * Copyright (C) 2014-2016 Sean Wang <sean.wang@mediatek.com>
931 + * Copyright (C) 2016-2017 John Crispin <blogic@openwrt.org>
932 + */
933 +
934 +#include <linux/dma-mapping.h>
935 +#include <linux/delay.h>
936 +#include <linux/if.h>
937 +#include <linux/io.h>
938 +#include <linux/module.h>
939 +#include <linux/of_device.h>
940 +#include <linux/platform_device.h>
941 +#include <linux/reset.h>
942 +#include <linux/netfilter.h>
943 +#include <linux/netdevice.h>
944 +#include <net/netfilter/nf_flow_table.h>
945 +#include <linux/debugfs.h>
946 +#include <linux/etherdevice.h>
947 +#include <linux/bitfield.h>
948 +
949 +#include "mtk_eth_soc.h"
950 +
951 +#ifdef CONFIG_RALINK
952 +/* ramips compat */
953 +#define mtk_eth fe_priv
954 +#define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000))
955 +#define mtk_m32 fe_m32
956 +
957 +static inline u32
958 +mtk_r32(struct mtk_eth *eth, u32 reg)
959 +{
960 + return fe_r32(reg);
961 +}
962 +
963 +static inline void
964 +mtk_w32(struct mtk_eth *eth, u32 val, u32 reg)
965 +{
966 + fe_w32(val, reg);
967 +}
968 +#endif
969 +
970 +#define MTK_REG_PPE_GLO_CFG 0xe00
971 +#define MTK_PPE_GLO_CFG_BUSY BIT(31)
972 +#define MTK_PPE_GLO_CFG_TTL0_DROP BIT(4)
973 +#define MTK_PPE_GLO_CFG_EN BIT(0)
974 +
975 +#define MTK_REG_PPE_FLOW_CFG 0xe04
976 +#define MTK_PPE_FLOW_CFG_IPV4_GREK_EN BIT(19)
977 +#define MTK_PPE_FLOW_CFG_IPV4_NAT_FRAG_EN BIT(17)
978 +#define MTK_PPE_FLOW_CFG_IPV4_NAPT_EN BIT(13)
979 +#define MTK_PPE_FLOW_CFG_IPV4_NAT_EN BIT(12)
980 +#define MTK_PPE_FLOW_CFG_FUC_FOE BIT(2)
981 +#define MTK_PPE_FLOW_CFG_FMC_FOE BIT(1)
982 +
983 +#define MTK_REG_PPE_IP_PROT_CHK 0xe08
984 +
985 +#define MTK_REG_PPE_TB_BASE 0xe20
986 +
987 +#define MTK_REG_PPE_BNDR 0xe28
988 +#define MTK_PPE_BNDR_RATE_MASK 0xffff
989 +
990 +#define MTK_REG_PPE_BIND_LMT_0 0xe2C
991 +
992 +#define MTK_REG_PPE_BIND_LMT_1 0xe30
993 +#define MTK_PPE_NTU_KA BIT(16)
994 +
995 +#define MTK_REG_PPE_KA 0xe34
996 +#define MTK_PPE_KA_T BIT(0)
997 +#define MTK_PPE_KA_TCP BIT(16)
998 +#define MTK_PPE_KA_UDP BIT(24)
999 +
1000 +#define MTK_REG_PPE_UNB_AGE 0xe38
1001 +#define MTK_PPE_UNB_AGE_MNP_MASK (0xffff << 16)
1002 +#define MTK_PPE_UNB_AGE_MNP (1000 << 16)
1003 +#define MTK_PPE_UNB_AGE_DLTA_MASK 0xff
1004 +#define MTK_PPE_UNB_AGE_DLTA 3
1005 +
1006 +#define MTK_REG_PPE_BND_AGE0 0xe3c
1007 +#define MTK_PPE_BND_AGE0_NTU_DLTA_MASK (0xffff << 16)
1008 +#define MTK_PPE_BND_AGE0_NTU_DLTA (5 << 16)
1009 +#define MTK_PPE_BND_AGE0_UDP_DLTA_MASK 0xffff
1010 +#define MTK_PPE_BND_AGE0_UDP_DLTA 5
1011 +
1012 +#define MTK_REG_PPE_BND_AGE1 0xe40
1013 +#define MTK_PPE_BND_AGE1_FIN_DLTA_MASK (0xffff << 16)
1014 +#define MTK_PPE_BND_AGE1_FIN_DLTA (5 << 16)
1015 +#define MTK_PPE_BND_AGE1_TCP_DLTA_MASK 0xffff
1016 +#define MTK_PPE_BND_AGE1_TCP_DLTA 5
1017 +
1018 +#define MTK_REG_PPE_DFT_CPORT 0xe48
1019 +
1020 +#define MTK_REG_PPE_TB_CFG 0xe1c
1021 +#define MTK_PPE_TB_CFG_X_MODE_MASK (3 << 18)
1022 +#define MTK_PPE_TB_CFG_HASH_MODE1 BIT(14)
1023 +#define MTK_PPE_TB_CFG_HASH_MODE_MASK (0x3 << 14)
1024 +#define MTK_PPE_TB_CFG_KA (3 << 12)
1025 +#define MTK_PPE_TB_CFG_KA_MASK (0x3 << 12)
1026 +#define MTK_PPE_TB_CFG_SCAN_MODE (2 << 16)
1027 +#define MTK_PPE_TB_CFG_SCAN_MODE_MASK (0x3 << 16)
1028 +#define MTK_PPE_TB_CFG_FIN_AGE BIT(11)
1029 +#define MTK_PPE_TB_CFG_UDP_AGE BIT(10)
1030 +#define MTK_PPE_TB_CFG_TCP_AGE BIT(9)
1031 +#define MTK_PPE_TB_CFG_UNBD_AGE BIT(8)
1032 +#define MTK_PPE_TB_CFG_NTU_AGE BIT(7)
1033 +#define MTK_PPE_TB_CFG_SMA_FWD_CPU (0x3 << 4)
1034 +#define MTK_PPE_TB_CFG_SMA_MASK (0x3 << 4)
1035 +#define MTK_PPE_TB_CFG_ENTRY_SZ_64B 0
1036 +#define MTK_PPE_TB_CFG_ENTRY_SZ_80B 1
1037 +#define MTK_PPE_TB_CFG_ENTRY_SZ_MASK BIT(3)
1038 +#define MTK_PPE_TB_CFG_TBL_SZ_4K 4
1039 +#define MTK_PPE_TB_CFG_TBL_SZ_MASK 0x7
1040 +
1041 +#define MTK_REG_PPE_HASH_SEED 0xe44
1042 +#define MTK_PPE_HASH_SEED 0x12345678
1043 +
1044 +
1045 +#define MTK_REG_PPE_CAH_CTRL 0xf20
1046 +#define MTK_PPE_CAH_CTRL_X_MODE BIT(9)
1047 +#define MTK_PPE_CAH_CTRL_EN BIT(0)
1048 +
1049 +#define MTK_REG_PPE_MIB_CFG 0xf34
1050 +#define MTK_REG_PPE_MIB_TB_BASE 0xf38
1051 +#define MTK_REG_PPE_MIB_CAH_CTRL 0Xf50
1052 +
1053 +
1054 +struct mtk_foe_unbind_info_blk {
1055 + u32 time_stamp:8;
1056 + u32 pcnt:16; /* packet count */
1057 + u32 preb:1;
1058 + u32 pkt_type:3;
1059 + u32 state:2;
1060 + u32 udp:1;
1061 + u32 sta:1; /* static entry */
1062 +} __attribute__ ((packed));
1063 +
1064 +struct mtk_foe_bind_info_blk {
1065 + u32 time_stamp:15;
1066 + u32 ka:1; /* keep alive */
1067 + u32 vlan_layer:3;
1068 + u32 psn:1; /* egress packet has PPPoE session */
1069 +#ifdef CONFIG_RALINK
1070 + u32 vpm:2; /* 0:ethertype remark, 1:0x8100(CR default) */
1071 +#else
1072 + u32 vpm:1; /* 0:ethertype remark, 1:0x8100(CR default) */
1073 + u32 ps:1; /* packet sampling */
1074 +#endif
1075 + u32 cah:1; /* cacheable flag */
1076 + u32 rmt:1; /* remove tunnel ip header (6rd/dslite only) */
1077 + u32 ttl:1;
1078 + u32 pkt_type:3;
1079 + u32 state:2;
1080 + u32 udp:1;
1081 + u32 sta:1; /* static entry */
1082 +} __attribute__ ((packed));
1083 +
1084 +struct mtk_foe_info_blk2 {
1085 + u32 qid:4; /* QID in Qos Port */
1086 + u32 fqos:1; /* force to PSE QoS port */
1087 + u32 dp:3; /* force to PSE port x
1088 + 0:PSE,1:GSW, 2:GMAC,4:PPE,5:QDMA,7=DROP */
1089 + u32 mcast:1; /* multicast this packet to CPU */
1090 + u32 pcpl:1; /* OSBN */
1091 + u32 mlen:1; /* 0:post 1:pre packet length in meter */
1092 + u32 alen:1; /* 0:post 1:pre packet length in accounting */
1093 + u32 port_mg:6; /* port meter group */
1094 + u32 port_ag:6; /* port account group */
1095 + u32 dscp:8; /* DSCP value */
1096 +} __attribute__ ((packed));
1097 +
1098 +/* info blk2 for WHNAT */
1099 +struct hnat_info_blk2_whnat {
1100 + u32 qid : 4; /* QID[3:0] in Qos Port */
1101 + u32 fqos : 1; /* force to PSE QoS port */
1102 + u32 dp : 3; /* force to PSE port x
1103 + * 0:PSE,1:GSW, 2:GMAC,4:PPE,5:QDMA,7=DROP
1104 + */
1105 + u32 mcast : 1; /* multicast this packet to CPU */
1106 + u32 pcpl : 1; /* OSBN */
1107 + u32 mibf : 1; /* 0:off 1:on PPE MIB counter */
1108 + u32 alen : 1; /* 0:post 1:pre packet length in accounting */
1109 + u32 qid2 : 2; /* QID[5:4] in Qos Port */
1110 + u32 resv : 2;
1111 + u32 wdmaid : 1; /* 0:to pcie0 dev 1:to pcie1 dev */
1112 + u32 winfoi : 1; /* 0:off 1:on Wi-Fi hwnat support */
1113 + u32 port_ag : 6; /* port account group */
1114 + u32 dscp : 8; /* DSCP value */
1115 +} __attribute__ ((packed));
1116 +
1117 +struct hnat_winfo {
1118 + u32 bssid : 6; /* WiFi Bssidx */
1119 + u32 wcid : 8; /* WiFi wtable Idx */
1120 + u32 rxid : 2; /* WiFi Ring idx */
1121 +} __attribute__ ((packed));
1122 +
1123 +struct mtk_foe_ipv4_hnapt {
1124 + union {
1125 + struct mtk_foe_bind_info_blk bfib1;
1126 + struct mtk_foe_unbind_info_blk udib1;
1127 + u32 info_blk1;
1128 + };
1129 + u32 sip;
1130 + u32 dip;
1131 + u16 dport;
1132 + u16 sport;
1133 + union {
1134 + struct mtk_foe_info_blk2 iblk2;
1135 + struct hnat_info_blk2_whnat iblk2w;
1136 + u32 info_blk2;
1137 + };
1138 + u32 new_sip;
1139 + u32 new_dip;
1140 + u16 new_dport;
1141 + u16 new_sport;
1142 + u32 resv1;
1143 + u32 resv2;
1144 + u32 resv3:26;
1145 + u32 act_dp:6; /* UDF */
1146 + u16 vlan1;
1147 + u16 etype;
1148 + u32 dmac_hi;
1149 + union {
1150 + struct hnat_winfo winfo;
1151 + u16 vlan2;
1152 + };
1153 + u16 dmac_lo;
1154 + u32 smac_hi;
1155 + u16 pppoe_id;
1156 + u16 smac_lo;
1157 +} __attribute__ ((packed));
1158 +
1159 +struct mtk_foe_entry {
1160 + union {
1161 + struct mtk_foe_unbind_info_blk udib1;
1162 + struct mtk_foe_bind_info_blk bfib1;
1163 + struct mtk_foe_ipv4_hnapt ipv4_hnapt;
1164 + };
1165 +};
1166 +
1167 +enum mtk_foe_entry_state {
1168 + FOE_STATE_INVALID = 0,
1169 + FOE_STATE_UNBIND = 1,
1170 + FOE_STATE_BIND = 2,
1171 + FOE_STATE_FIN = 3
1172 +};
1173 +
1174 +
1175 +#define MTK_RXD4_FOE_ENTRY GENMASK(13, 0)
1176 +#define MTK_RXD4_CPU_REASON GENMASK(18, 14)
1177 +#define MTK_RXD4_SRC_PORT GENMASK(21, 19)
1178 +#define MTK_RXD4_ALG GENMASK(31, 22)
1179 +
1180 +enum mtk_foe_cpu_reason {
1181 + MTK_CPU_REASON_TTL_EXCEEDED = 0x02,
1182 + MTK_CPU_REASON_OPTION_HEADER = 0x03,
1183 + MTK_CPU_REASON_NO_FLOW = 0x07,
1184 + MTK_CPU_REASON_IPV4_FRAG = 0x08,
1185 + MTK_CPU_REASON_IPV4_DSLITE_FRAG = 0x09,
1186 + MTK_CPU_REASON_IPV4_DSLITE_NO_TCP_UDP = 0x0a,
1187 + MTK_CPU_REASON_IPV6_6RD_NO_TCP_UDP = 0x0b,
1188 + MTK_CPU_REASON_TCP_FIN_SYN_RST = 0x0c,
1189 + MTK_CPU_REASON_UN_HIT = 0x0d,
1190 + MTK_CPU_REASON_HIT_UNBIND = 0x0e,
1191 + MTK_CPU_REASON_HIT_UNBIND_RATE_REACHED = 0x0f,
1192 + MTK_CPU_REASON_HIT_BIND_TCP_FIN = 0x10,
1193 + MTK_CPU_REASON_HIT_TTL_1 = 0x11,
1194 + MTK_CPU_REASON_HIT_BIND_VLAN_VIOLATION = 0x12,
1195 + MTK_CPU_REASON_KEEPALIVE_UC_OLD_HDR = 0x13,
1196 + MTK_CPU_REASON_KEEPALIVE_MC_NEW_HDR = 0x14,
1197 + MTK_CPU_REASON_KEEPALIVE_DUP_OLD_HDR = 0x15,
1198 + MTK_CPU_REASON_HIT_BIND_FORCE_CPU = 0x16,
1199 + MTK_CPU_REASON_TUNNEL_OPTION_HEADER = 0x17,
1200 + MTK_CPU_REASON_MULTICAST_TO_CPU = 0x18,
1201 + MTK_CPU_REASON_MULTICAST_TO_GMAC1_CPU = 0x19,
1202 + MTK_CPU_REASON_HIT_PRE_BIND = 0x1a,
1203 + MTK_CPU_REASON_PACKET_SAMPLING = 0x1b,
1204 + MTK_CPU_REASON_EXCEED_MTU = 0x1c,
1205 + MTK_CPU_REASON_PPE_BYPASS = 0x1e,
1206 + MTK_CPU_REASON_INVALID = 0x1f,
1207 +};
1208 +
1209 +
1210 +/* our table size is 4K */
1211 +#define MTK_PPE_ENTRY_CNT 0x4000
1212 +#define MTK_PPE_TBL_SZ \
1213 + (MTK_PPE_ENTRY_CNT * sizeof(struct mtk_foe_entry))
1214 +
1215 +int mtk_ppe_debugfs_init(struct mtk_eth *eth);
1216 +
1217 +
1218 +
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