kernel: bump 5.4 to 5.4.39
[openwrt/openwrt.git] / target / linux / mediatek / patches-5.4 / 1000-eth-gdm-config-backport.patch
1 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
2 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
3 @@ -2201,6 +2201,31 @@ static int mtk_start_dma(struct mtk_eth
4 return 0;
5 }
6
7 +static void mtk_gdm_config(struct mtk_eth *eth, u32 config)
8 +{
9 + int i;
10 +
11 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
12 + return;
13 +
14 + for (i = 0; i < MTK_MAC_COUNT; i++) {
15 + u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
16 +
17 + /* default setup the forward port to send frame to PDMA */
18 + val &= ~0xffff;
19 +
20 + /* Enable RX checksum */
21 + val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
22 +
23 + val |= config;
24 +
25 + mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
26 + }
27 + /* Reset and enable PSE */
28 + mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
29 + mtk_w32(eth, 0, MTK_RST_GL);
30 +}
31 +
32 static int mtk_open(struct net_device *dev)
33 {
34 struct mtk_mac *mac = netdev_priv(dev);
35 @@ -2221,6 +2246,8 @@ static int mtk_open(struct net_device *d
36 if (err)
37 return err;
38
39 + mtk_gdm_config(eth, MTK_GDMA_TO_PDMA);
40 +
41 napi_enable(&eth->tx_napi);
42 napi_enable(&eth->rx_napi);
43 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
44 @@ -2276,6 +2303,8 @@ static int mtk_stop(struct net_device *d
45 if (!refcount_dec_and_test(&eth->dma_refcnt))
46 return 0;
47
48 + mtk_gdm_config(eth, MTK_GDMA_DROP_ALL);
49 +
50 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
51 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
52 napi_disable(&eth->tx_napi);
53 @@ -2402,8 +2431,6 @@ static int mtk_hw_init(struct mtk_eth *e
54 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
55 mtk_tx_irq_disable(eth, ~0);
56 mtk_rx_irq_disable(eth, ~0);
57 - mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
58 - mtk_w32(eth, 0, MTK_RST_GL);
59
60 /* FE int grouping */
61 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1);
62 @@ -2412,19 +2439,6 @@ static int mtk_hw_init(struct mtk_eth *e
63 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);
64 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
65
66 - for (i = 0; i < MTK_MAC_COUNT; i++) {
67 - u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
68 -
69 - /* setup the forward port to send frame to PDMA */
70 - val &= ~0xffff;
71 -
72 - /* Enable RX checksum */
73 - val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
74 -
75 - /* setup the mac dma */
76 - mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
77 - }
78 -
79 return 0;
80
81 err_disable_pm:
82 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
83 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
84 @@ -84,6 +84,8 @@
85 #define MTK_GDMA_ICS_EN BIT(22)
86 #define MTK_GDMA_TCS_EN BIT(21)
87 #define MTK_GDMA_UCS_EN BIT(20)
88 +#define MTK_GDMA_TO_PDMA 0x0
89 +#define MTK_GDMA_DROP_ALL 0x7777
90
91 /* Unicast Filter MAC Address Register - Low */
92 #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000))