target/linux/mediatek/patches-5.4/1012-pci-pcie-mediatek-add-support-for-coherent-DMA.patch

   1 From: Felix Fietkau <nbd@nbd.name>
   2 Date: Fri, 4 Sep 2020 18:42:42 +0200
   3 Subject: [PATCH] pci: pcie-mediatek: add support for coherent DMA
   4
   5 It improves performance by eliminating the need for a cache flush for DMA on
   6 attached devices
   7
   8 Signed-off-by: Felix Fietkau <nbd@nbd.name>
   9 ---
  10
  11 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
  12 +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
  13 @@ -803,6 +803,8 @@
  14                 reg = <0 0x1a143000 0 0x1000>;
  15                 reg-names = "port0";
  16                 mediatek,pcie-cfg = <&pciecfg>;
  17 +               mediatek,hifsys = <&hifsys>;
  18 +               mediatek,cci-control = <&cci_control2>;
  19                 #address-cells = <3>;
  20                 #size-cells = <2>;
  21                 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
  22 @@ -820,6 +822,7 @@
  23                 bus-range = <0x00 0xff>;
  24                 ranges = <0x82000000 0 0x20000000  0x0 0x20000000  0 0x8000000>;
  25                 status = "disabled";
  26 +               dma-coherent;
  27
  28                 slot0: pcie@0,0 {
  29                         reg = <0x0000 0 0 0 0>;
  30 @@ -846,6 +849,8 @@
  31                 reg = <0 0x1a145000 0 0x1000>;
  32                 reg-names = "port1";
  33                 mediatek,pcie-cfg = <&pciecfg>;
  34 +               mediatek,hifsys = <&hifsys>;
  35 +               mediatek,cci-control = <&cci_control2>;
  36                 #address-cells = <3>;
  37                 #size-cells = <2>;
  38                 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
  39 @@ -864,6 +869,7 @@
  40                 bus-range = <0x00 0xff>;
  41                 ranges = <0x82000000 0 0x28000000  0x0 0x28000000  0 0x8000000>;
  42                 status = "disabled";
  43 +               dma-coherent;
  44
  45                 slot1: pcie@1,0 {
  46                         reg = <0x0800 0 0 0 0>;
  47 @@ -923,6 +929,11 @@
  48                 };
  49         };
  50
  51 +       hifsys: syscon@1af00000 {
  52 +               compatible = "mediatek,mt7622-hifsys", "syscon";
  53 +               reg = <0 0x1af00000 0 0x70>;
  54 +       };
  55 +
  56         ethsys: syscon@1b000000 {
  57                 compatible = "mediatek,mt7622-ethsys",
  58                              "syscon";
  59 --- a/drivers/pci/controller/pcie-mediatek.c
  60 +++ b/drivers/pci/controller/pcie-mediatek.c
  61 @@ -20,6 +20,7 @@
  62  #include <linux/of_address.h>
  63  #include <linux/of_pci.h>
  64  #include <linux/of_platform.h>
  65 +#include <linux/of_address.h>
  66  #include <linux/pci.h>
  67  #include <linux/phy/phy.h>
  68  #include <linux/platform_device.h>
  69 @@ -139,6 +140,11 @@
  70  #define PCIE_LINK_STATUS_V2    0x804
  71  #define PCIE_PORT_LINKUP_V2    BIT(10)
  72
  73 +/* DMA channel mapping */
  74 +#define HIFSYS_DMA_AG_MAP      0x008
  75 +#define HIFSYS_DMA_AG_MAP_PCIE0        BIT(0)
  76 +#define HIFSYS_DMA_AG_MAP_PCIE1        BIT(1)
  77 +
  78  struct mtk_pcie_port;
  79
  80  /**
  81 @@ -1068,6 +1074,27 @@ static int mtk_pcie_setup(struct mtk_pci
  82                 }
  83         }
  84
  85 +       if (of_dma_is_coherent(node)) {
  86 +               struct regmap *con;
  87 +               u32 mask;
  88 +
  89 +               con = syscon_regmap_lookup_by_phandle(node,
  90 +                                                     "mediatek,cci-control");
  91 +               /* enable CPU/bus coherency */
  92 +               if (!IS_ERR(con))
  93 +                       regmap_write(con, 0, 3);
  94 +
  95 +               con = syscon_regmap_lookup_by_phandle(node,
  96 +                                                     "mediatek,hifsys");
  97 +               if (IS_ERR(con)) {
  98 +                       dev_err(dev, "missing hifsys node\n");
  99 +                       return PTR_ERR(con);
 100 +               }
 101 +
 102 +               mask = HIFSYS_DMA_AG_MAP_PCIE0 | HIFSYS_DMA_AG_MAP_PCIE1;
 103 +               regmap_update_bits(con, HIFSYS_DMA_AG_MAP, mask, mask);
 104 +       }
 105 +
 106         for_each_available_child_of_node(node, child) {
 107                 int slot;
 108