target/linux/mediatek/patches/0002-clk-mediatek-Add-initial-common-clock-support-for-Me.patch

   1 From f851b4ea6cae9fd5875036b6d3968375882ce56b Mon Sep 17 00:00:00 2001
   2 From: James Liao <jamesjj.liao@mediatek.com>
   3 Date: Thu, 23 Apr 2015 10:35:39 +0200
   4 Subject: [PATCH 02/76] clk: mediatek: Add initial common clock support for
   5  Mediatek SoCs.
   6
   7 This patch adds common clock support for Mediatek SoCs, including plls,
   8 muxes and clock gates.
   9
  10 Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  11 Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
  12 Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
  13 ---
  14  drivers/clk/Makefile            |    1 +
  15  drivers/clk/mediatek/Makefile   |    1 +
  16  drivers/clk/mediatek/clk-gate.c |  137 ++++++++++++++++
  17  drivers/clk/mediatek/clk-gate.h |   49 ++++++
  18  drivers/clk/mediatek/clk-mtk.c  |  220 ++++++++++++++++++++++++++
  19  drivers/clk/mediatek/clk-mtk.h  |  159 +++++++++++++++++++
  20  drivers/clk/mediatek/clk-pll.c  |  332 +++++++++++++++++++++++++++++++++++++++
  21  7 files changed, 899 insertions(+)
  22  create mode 100644 drivers/clk/mediatek/Makefile
  23  create mode 100644 drivers/clk/mediatek/clk-gate.c
  24  create mode 100644 drivers/clk/mediatek/clk-gate.h
  25  create mode 100644 drivers/clk/mediatek/clk-mtk.c
  26  create mode 100644 drivers/clk/mediatek/clk-mtk.h
  27  create mode 100644 drivers/clk/mediatek/clk-pll.c
  28
  29 --- a/drivers/clk/Makefile
  30 +++ b/drivers/clk/Makefile
  31 @@ -51,6 +51,7 @@ obj-$(CONFIG_ARCH_HI3xxx)             += hisilicon/
  32  obj-$(CONFIG_ARCH_HIP04)               += hisilicon/
  33  obj-$(CONFIG_ARCH_HIX5HD2)             += hisilicon/
  34  obj-$(CONFIG_COMMON_CLK_KEYSTONE)      += keystone/
  35 +obj-$(CONFIG_ARCH_MEDIATEK)            += mediatek/
  36  ifeq ($(CONFIG_COMMON_CLK), y)
  37  obj-$(CONFIG_ARCH_MMP)                 += mmp/
  38  endif
  39 --- /dev/null
  40 +++ b/drivers/clk/mediatek/Makefile
  41 @@ -0,0 +1 @@
  42 +obj-y += clk-mtk.o clk-pll.o clk-gate.o
  43 --- /dev/null
  44 +++ b/drivers/clk/mediatek/clk-gate.c
  45 @@ -0,0 +1,137 @@
  46 +/*
  47 + * Copyright (c) 2014 MediaTek Inc.
  48 + * Author: James Liao <jamesjj.liao@mediatek.com>
  49 + *
  50 + * This program is free software; you can redistribute it and/or modify
  51 + * it under the terms of the GNU General Public License version 2 as
  52 + * published by the Free Software Foundation.
  53 + *
  54 + * This program is distributed in the hope that it will be useful,
  55 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  56 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  57 + * GNU General Public License for more details.
  58 + */
  59 +
  60 +#include <linux/of.h>
  61 +#include <linux/of_address.h>
  62 +
  63 +#include <linux/io.h>
  64 +#include <linux/slab.h>
  65 +#include <linux/delay.h>
  66 +#include <linux/clkdev.h>
  67 +
  68 +#include "clk-mtk.h"
  69 +#include "clk-gate.h"
  70 +
  71 +static int mtk_cg_bit_is_cleared(struct clk_hw *hw)
  72 +{
  73 +       struct mtk_clk_gate *cg = to_clk_gate(hw);
  74 +       u32 val;
  75 +
  76 +       regmap_read(cg->regmap, cg->sta_ofs, &val);
  77 +
  78 +       val &= BIT(cg->bit);
  79 +
  80 +       return val == 0;
  81 +}
  82 +
  83 +static int mtk_cg_bit_is_set(struct clk_hw *hw)
  84 +{
  85 +       struct mtk_clk_gate *cg = to_clk_gate(hw);
  86 +       u32 val;
  87 +
  88 +       regmap_read(cg->regmap, cg->sta_ofs, &val);
  89 +
  90 +       val &= BIT(cg->bit);
  91 +
  92 +       return val != 0;
  93 +}
  94 +
  95 +static void mtk_cg_set_bit(struct clk_hw *hw)
  96 +{
  97 +       struct mtk_clk_gate *cg = to_clk_gate(hw);
  98 +
  99 +       regmap_write(cg->regmap, cg->set_ofs, BIT(cg->bit));
 100 +}
 101 +
 102 +static void mtk_cg_clr_bit(struct clk_hw *hw)
 103 +{
 104 +       struct mtk_clk_gate *cg = to_clk_gate(hw);
 105 +
 106 +       regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit));
 107 +}
 108 +
 109 +static int mtk_cg_enable(struct clk_hw *hw)
 110 +{
 111 +       mtk_cg_clr_bit(hw);
 112 +
 113 +       return 0;
 114 +}
 115 +
 116 +static void mtk_cg_disable(struct clk_hw *hw)
 117 +{
 118 +       mtk_cg_set_bit(hw);
 119 +}
 120 +
 121 +static int mtk_cg_enable_inv(struct clk_hw *hw)
 122 +{
 123 +       mtk_cg_set_bit(hw);
 124 +
 125 +       return 0;
 126 +}
 127 +
 128 +static void mtk_cg_disable_inv(struct clk_hw *hw)
 129 +{
 130 +       mtk_cg_clr_bit(hw);
 131 +}
 132 +
 133 +const struct clk_ops mtk_clk_gate_ops_setclr = {
 134 +       .is_enabled     = mtk_cg_bit_is_cleared,
 135 +       .enable         = mtk_cg_enable,
 136 +       .disable        = mtk_cg_disable,
 137 +};
 138 +
 139 +const struct clk_ops mtk_clk_gate_ops_setclr_inv = {
 140 +       .is_enabled     = mtk_cg_bit_is_set,
 141 +       .enable         = mtk_cg_enable_inv,
 142 +       .disable        = mtk_cg_disable_inv,
 143 +};
 144 +
 145 +struct clk *mtk_clk_register_gate(
 146 +               const char *name,
 147 +               const char *parent_name,
 148 +               struct regmap *regmap,
 149 +               int set_ofs,
 150 +               int clr_ofs,
 151 +               int sta_ofs,
 152 +               u8 bit,
 153 +               const struct clk_ops *ops)
 154 +{
 155 +       struct mtk_clk_gate *cg;
 156 +       struct clk *clk;
 157 +       struct clk_init_data init;
 158 +
 159 +       cg = kzalloc(sizeof(*cg), GFP_KERNEL);
 160 +       if (!cg)
 161 +               return ERR_PTR(-ENOMEM);
 162 +
 163 +       init.name = name;
 164 +       init.flags = CLK_SET_RATE_PARENT;
 165 +       init.parent_names = parent_name ? &parent_name : NULL;
 166 +       init.num_parents = parent_name ? 1 : 0;
 167 +       init.ops = ops;
 168 +
 169 +       cg->regmap = regmap;
 170 +       cg->set_ofs = set_ofs;
 171 +       cg->clr_ofs = clr_ofs;
 172 +       cg->sta_ofs = sta_ofs;
 173 +       cg->bit = bit;
 174 +
 175 +       cg->hw.init = &init;
 176 +
 177 +       clk = clk_register(NULL, &cg->hw);
 178 +       if (IS_ERR(clk))
 179 +               kfree(cg);
 180 +
 181 +       return clk;
 182 +}
 183 --- /dev/null
 184 +++ b/drivers/clk/mediatek/clk-gate.h
 185 @@ -0,0 +1,49 @@
 186 +/*
 187 + * Copyright (c) 2014 MediaTek Inc.
 188 + * Author: James Liao <jamesjj.liao@mediatek.com>
 189 + *
 190 + * This program is free software; you can redistribute it and/or modify
 191 + * it under the terms of the GNU General Public License version 2 as
 192 + * published by the Free Software Foundation.
 193 + *
 194 + * This program is distributed in the hope that it will be useful,
 195 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 196 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 197 + * GNU General Public License for more details.
 198 + */
 199 +
 200 +#ifndef __DRV_CLK_GATE_H
 201 +#define __DRV_CLK_GATE_H
 202 +
 203 +#include <linux/regmap.h>
 204 +#include <linux/clk.h>
 205 +#include <linux/clk-provider.h>
 206 +
 207 +struct mtk_clk_gate {
 208 +       struct clk_hw   hw;
 209 +       struct regmap   *regmap;
 210 +       int             set_ofs;
 211 +       int             clr_ofs;
 212 +       int             sta_ofs;
 213 +       u8              bit;
 214 +};
 215 +
 216 +static inline struct mtk_clk_gate *to_clk_gate(struct clk_hw *hw)
 217 +{
 218 +       return container_of(hw, struct mtk_clk_gate, hw);
 219 +}
 220 +
 221 +extern const struct clk_ops mtk_clk_gate_ops_setclr;
 222 +extern const struct clk_ops mtk_clk_gate_ops_setclr_inv;
 223 +
 224 +struct clk *mtk_clk_register_gate(
 225 +               const char *name,
 226 +               const char *parent_name,
 227 +               struct regmap *regmap,
 228 +               int set_ofs,
 229 +               int clr_ofs,
 230 +               int sta_ofs,
 231 +               u8 bit,
 232 +               const struct clk_ops *ops);
 233 +
 234 +#endif /* __DRV_CLK_GATE_H */
 235 --- /dev/null
 236 +++ b/drivers/clk/mediatek/clk-mtk.c
 237 @@ -0,0 +1,220 @@
 238 +/*
 239 + * Copyright (c) 2014 MediaTek Inc.
 240 + * Author: James Liao <jamesjj.liao@mediatek.com>
 241 + *
 242 + * This program is free software; you can redistribute it and/or modify
 243 + * it under the terms of the GNU General Public License version 2 as
 244 + * published by the Free Software Foundation.
 245 + *
 246 + * This program is distributed in the hope that it will be useful,
 247 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 248 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 249 + * GNU General Public License for more details.
 250 + */
 251 +
 252 +#include <linux/of.h>
 253 +#include <linux/of_address.h>
 254 +#include <linux/err.h>
 255 +#include <linux/io.h>
 256 +#include <linux/slab.h>
 257 +#include <linux/delay.h>
 258 +#include <linux/clkdev.h>
 259 +#include <linux/mfd/syscon.h>
 260 +
 261 +#include "clk-mtk.h"
 262 +#include "clk-gate.h"
 263 +
 264 +struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num)
 265 +{
 266 +       int i;
 267 +       struct clk_onecell_data *clk_data;
 268 +
 269 +       clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
 270 +       if (!clk_data)
 271 +               return NULL;
 272 +
 273 +       clk_data->clks = kcalloc(clk_num, sizeof(*clk_data->clks), GFP_KERNEL);
 274 +       if (!clk_data->clks)
 275 +               goto err_out;
 276 +
 277 +       clk_data->clk_num = clk_num;
 278 +
 279 +       for (i = 0; i < clk_num; i++)
 280 +               clk_data->clks[i] = ERR_PTR(-ENOENT);
 281 +
 282 +       return clk_data;
 283 +err_out:
 284 +       kfree(clk_data);
 285 +
 286 +       return NULL;
 287 +}
 288 +
 289 +void mtk_clk_register_factors(const struct mtk_fixed_factor *clks, int num,
 290 +               struct clk_onecell_data *clk_data)
 291 +{
 292 +       int i;
 293 +       struct clk *clk;
 294 +
 295 +       for (i = 0; i < num; i++) {
 296 +               const struct mtk_fixed_factor *ff = &clks[i];
 297 +
 298 +               clk = clk_register_fixed_factor(NULL, ff->name, ff->parent_name,
 299 +                               CLK_SET_RATE_PARENT, ff->mult, ff->div);
 300 +
 301 +               if (IS_ERR(clk)) {
 302 +                       pr_err("Failed to register clk %s: %ld\n",
 303 +                                       ff->name, PTR_ERR(clk));
 304 +                       continue;
 305 +               }
 306 +
 307 +               if (clk_data)
 308 +                       clk_data->clks[ff->id] = clk;
 309 +       }
 310 +}
 311 +
 312 +int mtk_clk_register_gates(struct device_node *node, const struct mtk_gate *clks,
 313 +               int num, struct clk_onecell_data *clk_data)
 314 +{
 315 +       int i;
 316 +       struct clk *clk;
 317 +       struct regmap *regmap;
 318 +
 319 +       if (!clk_data)
 320 +               return -ENOMEM;
 321 +
 322 +       regmap = syscon_node_to_regmap(node);
 323 +       if (IS_ERR(regmap)) {
 324 +               pr_err("Cannot find regmap for %s: %ld\n", node->full_name,
 325 +                               PTR_ERR(regmap));
 326 +               return PTR_ERR(regmap);
 327 +       }
 328 +
 329 +       for (i = 0; i < num; i++) {
 330 +               const struct mtk_gate *gate = &clks[i];
 331 +
 332 +               clk = mtk_clk_register_gate(gate->name, gate->parent_name,
 333 +                               regmap,
 334 +                               gate->regs->set_ofs,
 335 +                               gate->regs->clr_ofs,
 336 +                               gate->regs->sta_ofs,
 337 +                               gate->shift, gate->ops);
 338 +
 339 +               if (IS_ERR(clk)) {
 340 +                       pr_err("Failed to register clk %s: %ld\n",
 341 +                                       gate->name, PTR_ERR(clk));
 342 +                       continue;
 343 +               }
 344 +
 345 +               clk_data->clks[gate->id] = clk;
 346 +       }
 347 +
 348 +       return 0;
 349 +}
 350 +
 351 +struct clk *mtk_clk_register_composite(const struct mtk_composite *mc,
 352 +               void __iomem *base, spinlock_t *lock)
 353 +{
 354 +       struct clk *clk;
 355 +       struct clk_mux *mux = NULL;
 356 +       struct clk_gate *gate = NULL;
 357 +       struct clk_divider *div = NULL;
 358 +       struct clk_hw *mux_hw = NULL, *gate_hw = NULL, *div_hw = NULL;
 359 +       const struct clk_ops *mux_ops = NULL, *gate_ops = NULL, *div_ops = NULL;
 360 +       const char * const *parent_names;
 361 +       const char *parent;
 362 +       int num_parents;
 363 +       int ret;
 364 +
 365 +       if (mc->mux_shift >= 0) {
 366 +               mux = kzalloc(sizeof(*mux), GFP_KERNEL);
 367 +               if (!mux)
 368 +                       return ERR_PTR(-ENOMEM);
 369 +
 370 +               mux->reg = base + mc->mux_reg;
 371 +               mux->mask = BIT(mc->mux_width) - 1;
 372 +               mux->shift = mc->mux_shift;
 373 +               mux->lock = lock;
 374 +
 375 +               mux_hw = &mux->hw;
 376 +               mux_ops = &clk_mux_ops;
 377 +
 378 +               parent_names = mc->parent_names;
 379 +               num_parents = mc->num_parents;
 380 +       } else {
 381 +               parent = mc->parent;
 382 +               parent_names = &parent;
 383 +               num_parents = 1;
 384 +       }
 385 +
 386 +       if (mc->gate_shift >= 0) {
 387 +               gate = kzalloc(sizeof(*gate), GFP_KERNEL);
 388 +               if (!gate) {
 389 +                       ret = -ENOMEM;
 390 +                       goto err_out;
 391 +               }
 392 +
 393 +               gate->reg = base + mc->gate_reg;
 394 +               gate->bit_idx = mc->gate_shift;
 395 +               gate->flags = CLK_GATE_SET_TO_DISABLE;
 396 +               gate->lock = lock;
 397 +
 398 +               gate_hw = &gate->hw;
 399 +               gate_ops = &clk_gate_ops;
 400 +       }
 401 +
 402 +       if (mc->divider_shift >= 0) {
 403 +               div = kzalloc(sizeof(*div), GFP_KERNEL);
 404 +               if (!div) {
 405 +                       ret = -ENOMEM;
 406 +                       goto err_out;
 407 +               }
 408 +
 409 +               div->reg = base + mc->divider_reg;
 410 +               div->shift = mc->divider_shift;
 411 +               div->width = mc->divider_width;
 412 +               div->lock = lock;
 413 +
 414 +               div_hw = &div->hw;
 415 +               div_ops = &clk_divider_ops;
 416 +       }
 417 +
 418 +       clk = clk_register_composite(NULL, mc->name, parent_names, num_parents,
 419 +               mux_hw, mux_ops,
 420 +               div_hw, div_ops,
 421 +               gate_hw, gate_ops,
 422 +               mc->flags);
 423 +
 424 +       if (IS_ERR(clk)) {
 425 +               kfree(gate);
 426 +               kfree(mux);
 427 +       }
 428 +
 429 +       return clk;
 430 +err_out:
 431 +       kfree(mux);
 432 +
 433 +       return ERR_PTR(ret);
 434 +}
 435 +
 436 +void mtk_clk_register_composites(const struct mtk_composite *mcs,
 437 +               int num, void __iomem *base, spinlock_t *lock,
 438 +               struct clk_onecell_data *clk_data)
 439 +{
 440 +       struct clk *clk;
 441 +       int i;
 442 +
 443 +       for (i = 0; i < num; i++) {
 444 +               const struct mtk_composite *mc = &mcs[i];
 445 +
 446 +               clk = mtk_clk_register_composite(mc, base, lock);
 447 +
 448 +               if (IS_ERR(clk)) {
 449 +                       pr_err("Failed to register clk %s: %ld\n",
 450 +                                       mc->name, PTR_ERR(clk));
 451 +                       continue;
 452 +               }
 453 +
 454 +               if (clk_data)
 455 +                       clk_data->clks[mc->id] = clk;
 456 +       }
 457 +}
 458 --- /dev/null
 459 +++ b/drivers/clk/mediatek/clk-mtk.h
 460 @@ -0,0 +1,159 @@
 461 +/*
 462 + * Copyright (c) 2014 MediaTek Inc.
 463 + * Author: James Liao <jamesjj.liao@mediatek.com>
 464 + *
 465 + * This program is free software; you can redistribute it and/or modify
 466 + * it under the terms of the GNU General Public License version 2 as
 467 + * published by the Free Software Foundation.
 468 + *
 469 + * This program is distributed in the hope that it will be useful,
 470 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 471 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 472 + * GNU General Public License for more details.
 473 + */
 474 +
 475 +#ifndef __DRV_CLK_MTK_H
 476 +#define __DRV_CLK_MTK_H
 477 +
 478 +#include <linux/regmap.h>
 479 +#include <linux/bitops.h>
 480 +#include <linux/clk.h>
 481 +#include <linux/clk-provider.h>
 482 +
 483 +#define MAX_MUX_GATE_BIT       31
 484 +#define INVALID_MUX_GATE_BIT   (MAX_MUX_GATE_BIT + 1)
 485 +
 486 +#define MHZ (1000 * 1000)
 487 +
 488 +struct mtk_fixed_factor {
 489 +       int id;
 490 +       const char *name;
 491 +       const char *parent_name;
 492 +       int mult;
 493 +       int div;
 494 +};
 495 +
 496 +#define FACTOR(_id, _name, _parent, _mult, _div) {     \
 497 +               .id = _id,                              \
 498 +               .name = _name,                          \
 499 +               .parent_name = _parent,                 \
 500 +               .mult = _mult,                          \
 501 +               .div = _div,                            \
 502 +       }
 503 +
 504 +extern void mtk_clk_register_factors(const struct mtk_fixed_factor *clks,
 505 +               int num, struct clk_onecell_data *clk_data);
 506 +
 507 +struct mtk_composite {
 508 +       int id;
 509 +       const char *name;
 510 +       const char * const * parent_names;
 511 +       const char *parent;
 512 +       unsigned flags;
 513 +
 514 +       uint32_t mux_reg;
 515 +       uint32_t divider_reg;
 516 +       uint32_t gate_reg;
 517 +
 518 +       signed char mux_shift;
 519 +       signed char mux_width;
 520 +       signed char gate_shift;
 521 +
 522 +       signed char divider_shift;
 523 +       signed char divider_width;
 524 +
 525 +       signed char num_parents;
 526 +};
 527 +
 528 +#define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) {  \
 529 +               .id = _id,                                              \
 530 +               .name = _name,                                          \
 531 +               .mux_reg = _reg,                                        \
 532 +               .mux_shift = _shift,                                    \
 533 +               .mux_width = _width,                                    \
 534 +               .gate_reg = _reg,                                       \
 535 +               .gate_shift = _gate,                                    \
 536 +               .divider_shift = -1,                                    \
 537 +               .parent_names = _parents,                               \
 538 +               .num_parents = ARRAY_SIZE(_parents),                    \
 539 +               .flags = CLK_SET_RATE_PARENT,                           \
 540 +       }
 541 +
 542 +#define MUX(_id, _name, _parents, _reg, _shift, _width) {              \
 543 +               .id = _id,                                              \
 544 +               .name = _name,                                          \
 545 +               .mux_reg = _reg,                                        \
 546 +               .mux_shift = _shift,                                    \
 547 +               .mux_width = _width,                                    \
 548 +               .gate_shift = -1,                                       \
 549 +               .divider_shift = -1,                                    \
 550 +               .parent_names = _parents,                               \
 551 +               .num_parents = ARRAY_SIZE(_parents),                    \
 552 +               .flags = CLK_SET_RATE_PARENT,                           \
 553 +       }
 554 +
 555 +#define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, _div_width, _div_shift) {      \
 556 +               .id = _id,                                              \
 557 +               .parent = _parent,                                      \
 558 +               .name = _name,                                          \
 559 +               .divider_reg = _div_reg,                                \
 560 +               .divider_shift = _div_shift,                            \
 561 +               .divider_width = _div_width,                            \
 562 +               .gate_reg = _gate_reg,                                  \
 563 +               .gate_shift = _gate_shift,                              \
 564 +               .mux_shift = -1,                                        \
 565 +               .flags = 0,                                             \
 566 +       }
 567 +
 568 +struct clk *mtk_clk_register_composite(const struct mtk_composite *mc,
 569 +               void __iomem *base, spinlock_t *lock);
 570 +
 571 +void mtk_clk_register_composites(const struct mtk_composite *mcs,
 572 +               int num, void __iomem *base, spinlock_t *lock,
 573 +               struct clk_onecell_data *clk_data);
 574 +
 575 +struct mtk_gate_regs {
 576 +       u32 sta_ofs;
 577 +       u32 clr_ofs;
 578 +       u32 set_ofs;
 579 +};
 580 +
 581 +struct mtk_gate {
 582 +       int id;
 583 +       const char *name;
 584 +       const char *parent_name;
 585 +       const struct mtk_gate_regs *regs;
 586 +       int shift;
 587 +       const struct clk_ops *ops;
 588 +};
 589 +
 590 +int mtk_clk_register_gates(struct device_node *node, const struct mtk_gate *clks,
 591 +               int num, struct clk_onecell_data *clk_data);
 592 +
 593 +struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num);
 594 +
 595 +#define HAVE_RST_BAR   BIT(0)
 596 +
 597 +struct mtk_pll_data {
 598 +       int id;
 599 +       const char *name;
 600 +       uint32_t reg;
 601 +       uint32_t pwr_reg;
 602 +       uint32_t en_mask;
 603 +       uint32_t pd_reg;
 604 +       uint32_t tuner_reg;
 605 +       int pd_shift;
 606 +       unsigned int flags;
 607 +       const struct clk_ops *ops;
 608 +       u32 rst_bar_mask;
 609 +       unsigned long fmax;
 610 +       int pcwbits;
 611 +       uint32_t pcw_reg;
 612 +       int pcw_shift;
 613 +};
 614 +
 615 +void __init mtk_clk_register_plls(struct device_node *node,
 616 +               const struct mtk_pll_data *plls, int num_plls,
 617 +               struct clk_onecell_data *clk_data);
 618 +
 619 +#endif /* __DRV_CLK_MTK_H */
 620 --- /dev/null
 621 +++ b/drivers/clk/mediatek/clk-pll.c
 622 @@ -0,0 +1,332 @@
 623 +/*
 624 + * Copyright (c) 2014 MediaTek Inc.
 625 + * Author: James Liao <jamesjj.liao@mediatek.com>
 626 + *
 627 + * This program is free software; you can redistribute it and/or modify
 628 + * it under the terms of the GNU General Public License version 2 as
 629 + * published by the Free Software Foundation.
 630 + *
 631 + * This program is distributed in the hope that it will be useful,
 632 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 633 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 634 + * GNU General Public License for more details.
 635 + */
 636 +
 637 +#include <linux/of.h>
 638 +#include <linux/of_address.h>
 639 +#include <linux/io.h>
 640 +#include <linux/slab.h>
 641 +#include <linux/clkdev.h>
 642 +#include <linux/delay.h>
 643 +
 644 +#include "clk-mtk.h"
 645 +
 646 +#define REG_CON0               0
 647 +#define REG_CON1               4
 648 +
 649 +#define CON0_BASE_EN           BIT(0)
 650 +#define CON0_PWR_ON            BIT(0)
 651 +#define CON0_ISO_EN            BIT(1)
 652 +#define CON0_PCW_CHG           BIT(31)
 653 +
 654 +#define AUDPLL_TUNER_EN                BIT(31)
 655 +
 656 +#define POSTDIV_MASK           0x7
 657 +#define INTEGER_BITS           7
 658 +
 659 +/*
 660 + * MediaTek PLLs are configured through their pcw value. The pcw value describes
 661 + * a divider in the PLL feedback loop which consists of 7 bits for the integer
 662 + * part and the remaining bits (if present) for the fractional part. Also they
 663 + * have a 3 bit power-of-two post divider.
 664 + */
 665 +
 666 +struct mtk_clk_pll {
 667 +       struct clk_hw   hw;
 668 +       void __iomem    *base_addr;
 669 +       void __iomem    *pd_addr;
 670 +       void __iomem    *pwr_addr;
 671 +       void __iomem    *tuner_addr;
 672 +       void __iomem    *pcw_addr;
 673 +       const struct mtk_pll_data *data;
 674 +};
 675 +
 676 +static inline struct mtk_clk_pll *to_mtk_clk_pll(struct clk_hw *hw)
 677 +{
 678 +       return container_of(hw, struct mtk_clk_pll, hw);
 679 +}
 680 +
 681 +static int mtk_pll_is_prepared(struct clk_hw *hw)
 682 +{
 683 +       struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
 684 +
 685 +       return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0;
 686 +}
 687 +
 688 +static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
 689 +               u32 pcw, int postdiv)
 690 +{
 691 +       int pcwbits = pll->data->pcwbits;
 692 +       int pcwfbits;
 693 +       u64 vco;
 694 +       u8 c = 0;
 695 +
 696 +       /* The fractional part of the PLL divider. */
 697 +       pcwfbits = pcwbits > INTEGER_BITS ? pcwbits - INTEGER_BITS : 0;
 698 +
 699 +       vco = (u64)fin * pcw;
 700 +
 701 +       if (pcwfbits && (vco & GENMASK(pcwfbits - 1, 0)))
 702 +               c = 1;
 703 +
 704 +       vco >>= pcwfbits;
 705 +
 706 +       if (c)
 707 +               vco++;
 708 +
 709 +       return ((unsigned long)vco + postdiv - 1) / postdiv;
 710 +}
 711 +
 712 +static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
 713 +               int postdiv)
 714 +{
 715 +       u32 con1, pd, val;
 716 +       int pll_en;
 717 +
 718 +       /* set postdiv */
 719 +       pd = readl(pll->pd_addr);
 720 +       pd &= ~(POSTDIV_MASK << pll->data->pd_shift);
 721 +       pd |= (ffs(postdiv) - 1) << pll->data->pd_shift;
 722 +       writel(pd, pll->pd_addr);
 723 +
 724 +       pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN;
 725 +
 726 +       /* set pcw */
 727 +       val = readl(pll->pcw_addr);
 728 +
 729 +       val &= ~GENMASK(pll->data->pcw_shift + pll->data->pcwbits - 1,
 730 +                       pll->data->pcw_shift);
 731 +       val |= pcw << pll->data->pcw_shift;
 732 +       writel(val, pll->pcw_addr);
 733 +
 734 +       con1 = readl(pll->base_addr + REG_CON1);
 735 +
 736 +       if (pll_en)
 737 +               con1 |= CON0_PCW_CHG;
 738 +
 739 +       writel(con1, pll->base_addr + REG_CON1);
 740 +       if (pll->tuner_addr)
 741 +               writel(con1 + 1, pll->tuner_addr);
 742 +
 743 +       if (pll_en)
 744 +               udelay(20);
 745 +}
 746 +
 747 +/*
 748 + * mtk_pll_calc_values - calculate good values for a given input frequency.
 749 + * @pll:       The pll
 750 + * @pcw:       The pcw value (output)
 751 + * @postdiv:   The post divider (output)
 752 + * @freq:      The desired target frequency
 753 + * @fin:       The input frequency
 754 + *
 755 + */
 756 +static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
 757 +               u32 freq, u32 fin)
 758 +{
 759 +       unsigned long fmin = 1000 * MHZ;
 760 +       u64 _pcw;
 761 +       u32 val;
 762 +
 763 +       if (freq > pll->data->fmax)
 764 +               freq = pll->data->fmax;
 765 +
 766 +       for (val = 0; val < 4; val++) {
 767 +               *postdiv = 1 << val;
 768 +               if (freq * *postdiv >= fmin)
 769 +                       break;
 770 +       }
 771 +
 772 +       /* _pcw = freq * postdiv / fin * 2^pcwfbits */
 773 +       _pcw = ((u64)freq << val) << (pll->data->pcwbits - INTEGER_BITS);
 774 +       do_div(_pcw, fin);
 775 +
 776 +       *pcw = (u32)_pcw;
 777 +}
 778 +
 779 +static int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 780 +               unsigned long parent_rate)
 781 +{
 782 +       struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
 783 +       u32 pcw = 0;
 784 +       u32 postdiv;
 785 +
 786 +       mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate);
 787 +       mtk_pll_set_rate_regs(pll, pcw, postdiv);
 788 +
 789 +       return 0;
 790 +}
 791 +
 792 +static unsigned long mtk_pll_recalc_rate(struct clk_hw *hw,
 793 +               unsigned long parent_rate)
 794 +{
 795 +       struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
 796 +       u32 postdiv;
 797 +       u32 pcw;
 798 +
 799 +       postdiv = (readl(pll->pd_addr) >> pll->data->pd_shift) & POSTDIV_MASK;
 800 +       postdiv = 1 << postdiv;
 801 +
 802 +       pcw = readl(pll->pcw_addr) >> pll->data->pcw_shift;
 803 +       pcw &= GENMASK(pll->data->pcwbits - 1, 0);
 804 +
 805 +       return __mtk_pll_recalc_rate(pll, parent_rate, pcw, postdiv);
 806 +}
 807 +
 808 +static long mtk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 809 +               unsigned long *prate)
 810 +{
 811 +       struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
 812 +       u32 pcw = 0;
 813 +       int postdiv;
 814 +
 815 +       mtk_pll_calc_values(pll, &pcw, &postdiv, rate, *prate);
 816 +
 817 +       return __mtk_pll_recalc_rate(pll, *prate, pcw, postdiv);
 818 +}
 819 +
 820 +static int mtk_pll_prepare(struct clk_hw *hw)
 821 +{
 822 +       struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
 823 +       u32 r;
 824 +
 825 +       r = readl(pll->pwr_addr) | CON0_PWR_ON;
 826 +       writel(r, pll->pwr_addr);
 827 +       udelay(1);
 828 +
 829 +       r = readl(pll->pwr_addr) & ~CON0_ISO_EN;
 830 +       writel(r, pll->pwr_addr);
 831 +       udelay(1);
 832 +
 833 +       r = readl(pll->base_addr + REG_CON0);
 834 +       r |= pll->data->en_mask;
 835 +       writel(r, pll->base_addr + REG_CON0);
 836 +
 837 +       if (pll->tuner_addr) {
 838 +               r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;
 839 +               writel(r, pll->tuner_addr);
 840 +       }
 841 +
 842 +       udelay(20);
 843 +
 844 +       if (pll->data->flags & HAVE_RST_BAR) {
 845 +               r = readl(pll->base_addr + REG_CON0);
 846 +               r |= pll->data->rst_bar_mask;
 847 +               writel(r, pll->base_addr + REG_CON0);
 848 +       }
 849 +
 850 +       return 0;
 851 +}
 852 +
 853 +static void mtk_pll_unprepare(struct clk_hw *hw)
 854 +{
 855 +       struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
 856 +       u32 r;
 857 +
 858 +       if (pll->data->flags & HAVE_RST_BAR) {
 859 +               r = readl(pll->base_addr + REG_CON0);
 860 +               r &= ~pll->data->rst_bar_mask;
 861 +               writel(r, pll->base_addr + REG_CON0);
 862 +       }
 863 +
 864 +       if (pll->tuner_addr) {
 865 +               r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;
 866 +               writel(r, pll->tuner_addr);
 867 +       }
 868 +
 869 +       r = readl(pll->base_addr + REG_CON0);
 870 +       r &= ~CON0_BASE_EN;
 871 +       writel(r, pll->base_addr + REG_CON0);
 872 +
 873 +       r = readl(pll->pwr_addr) | CON0_ISO_EN;
 874 +       writel(r, pll->pwr_addr);
 875 +
 876 +       r = readl(pll->pwr_addr) & ~CON0_PWR_ON;
 877 +       writel(r, pll->pwr_addr);
 878 +}
 879 +
 880 +static const struct clk_ops mtk_pll_ops = {
 881 +       .is_prepared    = mtk_pll_is_prepared,
 882 +       .prepare        = mtk_pll_prepare,
 883 +       .unprepare      = mtk_pll_unprepare,
 884 +       .recalc_rate    = mtk_pll_recalc_rate,
 885 +       .round_rate     = mtk_pll_round_rate,
 886 +       .set_rate       = mtk_pll_set_rate,
 887 +};
 888 +
 889 +static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data,
 890 +               void __iomem *base)
 891 +{
 892 +       struct mtk_clk_pll *pll;
 893 +       struct clk_init_data init;
 894 +       struct clk *clk;
 895 +       const char *parent_name = "clk26m";
 896 +
 897 +       pll = kzalloc(sizeof(*pll), GFP_KERNEL);
 898 +       if (!pll)
 899 +               return ERR_PTR(-ENOMEM);
 900 +
 901 +       pll->base_addr = base + data->reg;
 902 +       pll->pwr_addr = base + data->pwr_reg;
 903 +       pll->pd_addr = base + data->pd_reg;
 904 +       pll->pcw_addr = base + data->pcw_reg;
 905 +       if (data->tuner_reg)
 906 +               pll->tuner_addr = base + data->tuner_reg;
 907 +       pll->hw.init = &init;
 908 +       pll->data = data;
 909 +
 910 +       init.name = data->name;
 911 +       init.ops = &mtk_pll_ops;
 912 +       init.parent_names = &parent_name;
 913 +       init.num_parents = 1;
 914 +
 915 +       clk = clk_register(NULL, &pll->hw);
 916 +
 917 +       if (IS_ERR(clk))
 918 +               kfree(pll);
 919 +
 920 +       return clk;
 921 +}
 922 +
 923 +void __init mtk_clk_register_plls(struct device_node *node,
 924 +               const struct mtk_pll_data *plls, int num_plls, struct clk_onecell_data *clk_data)
 925 +{
 926 +       void __iomem *base;
 927 +       int r, i;
 928 +       struct clk *clk;
 929 +
 930 +       base = of_iomap(node, 0);
 931 +       if (!base) {
 932 +               pr_err("%s(): ioremap failed\n", __func__);
 933 +               return;
 934 +       }
 935 +
 936 +       for (i = 0; i < num_plls; i++) {
 937 +               const struct mtk_pll_data *pll = &plls[i];
 938 +
 939 +               clk = mtk_clk_register_pll(pll, base);
 940 +
 941 +               if (IS_ERR(clk)) {
 942 +                       pr_err("Failed to register clk %s: %ld\n",
 943 +                                       pll->name, PTR_ERR(clk));
 944 +                       continue;
 945 +               }
 946 +
 947 +               clk_data->clks[pll->id] = clk;
 948 +       }
 949 +
 950 +       r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 951 +       if (r)
 952 +               pr_err("%s(): could not register clock provider: %d\n",
 953 +                       __func__, r);
 954 +}