target/linux/mediatek/patches/0030-I2C-mediatek-Add-driver-for-MediaTek-I2C-controller.patch

   1 From 2471bc43c6079ab956a04f29ffd1ab8371b7bd73 Mon Sep 17 00:00:00 2001
   2 From: Xudong Chen <xudong.chen@mediatek.com>
   3 Date: Wed, 6 May 2015 16:37:06 +0800
   4 Subject: [PATCH 30/76] I2C: mediatek: Add driver for MediaTek I2C controller
   5
   6 The mediatek SoCs have I2C controller that handle I2C transfer.
   7 This patch include common I2C bus driver.
   8 This driver is compatible with I2C controller on mt65xx/mt81xx.
   9
  10 Signed-off-by: Xudong Chen <xudong.chen@mediatek.com>
  11 Signed-off-by: Liguo Zhang <liguo.zhang@mediatek.com>
  12 Signed-off-by: Eddie Huang <eddie.huang@mediatek.com>
  13 ---
  14  drivers/i2c/busses/Kconfig      |    9 +
  15  drivers/i2c/busses/Makefile     |    1 +
  16  drivers/i2c/busses/i2c-mt65xx.c |  700 +++++++++++++++++++++++++++++++++++++++
  17  3 files changed, 710 insertions(+)
  18  create mode 100644 drivers/i2c/busses/i2c-mt65xx.c
  19
  20 --- a/drivers/i2c/busses/Kconfig
  21 +++ b/drivers/i2c/busses/Kconfig
  22 @@ -620,6 +620,15 @@ config I2C_MPC
  23           This driver can also be built as a module.  If so, the module
  24           will be called i2c-mpc.
  25
  26 +config I2C_MT65XX
  27 +       tristate "MediaTek I2C adapter"
  28 +       depends on ARCH_MEDIATEK || COMPILE_TEST
  29 +       help
  30 +         This selects the MediaTek(R) Integrated Inter Circuit bus driver
  31 +         for MT65xx and MT81xx.
  32 +         If you want to use MediaTek(R) I2C interface, say Y or M here.
  33 +         If unsure, say N.
  34 +
  35  config I2C_MV64XXX
  36         tristate "Marvell mv64xxx I2C Controller"
  37         depends on MV64X60 || PLAT_ORION || ARCH_SUNXI
  38 --- a/drivers/i2c/busses/Makefile
  39 +++ b/drivers/i2c/busses/Makefile
  40 @@ -60,6 +60,7 @@ obj-$(CONFIG_I2C_JZ4780)      += i2c-jz4780.o
  41  obj-$(CONFIG_I2C_KEMPLD)       += i2c-kempld.o
  42  obj-$(CONFIG_I2C_MESON)                += i2c-meson.o
  43  obj-$(CONFIG_I2C_MPC)          += i2c-mpc.o
  44 +obj-$(CONFIG_I2C_MT65XX)       += i2c-mt65xx.o
  45  obj-$(CONFIG_I2C_MV64XXX)      += i2c-mv64xxx.o
  46  obj-$(CONFIG_I2C_MXS)          += i2c-mxs.o
  47  obj-$(CONFIG_I2C_NOMADIK)      += i2c-nomadik.o
  48 --- /dev/null
  49 +++ b/drivers/i2c/busses/i2c-mt65xx.c
  50 @@ -0,0 +1,700 @@
  51 +/*
  52 + * Copyright (c) 2014 MediaTek Inc.
  53 + * Author: Xudong.chen <xudong.chen@mediatek.com>
  54 + *
  55 + * This program is free software; you can redistribute it and/or modify
  56 + * it under the terms of the GNU General Public License version 2 as
  57 + * published by the Free Software Foundation.
  58 + *
  59 + * This program is distributed in the hope that it will be useful,
  60 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  61 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  62 + * GNU General Public License for more details.
  63 + */
  64 +
  65 +#include <linux/kernel.h>
  66 +#include <linux/module.h>
  67 +#include <linux/slab.h>
  68 +#include <linux/i2c.h>
  69 +#include <linux/init.h>
  70 +#include <linux/interrupt.h>
  71 +#include <linux/sched.h>
  72 +#include <linux/delay.h>
  73 +#include <linux/errno.h>
  74 +#include <linux/err.h>
  75 +#include <linux/device.h>
  76 +#include <linux/platform_device.h>
  77 +#include <linux/mm.h>
  78 +#include <linux/dma-mapping.h>
  79 +#include <linux/scatterlist.h>
  80 +#include <linux/io.h>
  81 +#include <linux/of_address.h>
  82 +#include <linux/of_irq.h>
  83 +#include <linux/clk.h>
  84 +#include <linux/completion.h>
  85 +
  86 +#define I2C_HS_NACKERR                 (1 << 2)
  87 +#define I2C_ACKERR                     (1 << 1)
  88 +#define I2C_TRANSAC_COMP               (1 << 0)
  89 +#define I2C_TRANSAC_START              (1 << 0)
  90 +#define I2C_TIMING_STEP_DIV_MASK       (0x3f << 0)
  91 +#define I2C_TIMING_SAMPLE_COUNT_MASK   (0x7 << 0)
  92 +#define I2C_TIMING_SAMPLE_DIV_MASK     (0x7 << 8)
  93 +#define I2C_TIMING_DATA_READ_MASK      (0x7 << 12)
  94 +#define I2C_DCM_DISABLE                        0x0000
  95 +#define I2C_IO_CONFIG_OPEN_DRAIN       0x0003
  96 +#define I2C_IO_CONFIG_PUSH_PULL                0x0000
  97 +#define I2C_SOFT_RST                   0x0001
  98 +#define I2C_FIFO_ADDR_CLR              0x0001
  99 +#define I2C_DELAY_LEN                  0x0002
 100 +#define I2C_ST_START_CON               0x8001
 101 +#define I2C_FS_START_CON               0x1800
 102 +#define I2C_TIME_CLR_VALUE             0x0000
 103 +#define I2C_TIME_DEFAULT_VALUE         0x0003
 104 +#define I2C_FS_TIME_INIT_VALUE         0x1303
 105 +#define I2C_WRRD_TRANAC_VALUE          0x0002
 106 +#define I2C_RD_TRANAC_VALUE            0x0001
 107 +
 108 +#define I2C_DMA_CON_TX                 0x0000
 109 +#define I2C_DMA_CON_RX                 0x0001
 110 +#define I2C_DMA_START_EN               0x0001
 111 +#define I2C_DMA_INT_FLAG_NONE          0x0000
 112 +#define I2C_DMA_CLR_FLAG               0x0000
 113 +
 114 +#define I2C_DEFAUT_SPEED               100000  /* hz */
 115 +#define MAX_FS_MODE_SPEED              400000
 116 +#define MAX_HS_MODE_SPEED              3400000
 117 +#define MAX_MSG_NUM_MT6577             1
 118 +#define MAX_DMA_TRANS_SIZE_MT6577      255
 119 +#define MAX_WRRD_TRANS_SIZE_MT6577     31
 120 +#define MAX_SAMPLE_CNT_DIV             8
 121 +#define MAX_STEP_CNT_DIV               64
 122 +#define MAX_HS_STEP_CNT_DIV            8
 123 +
 124 +#define I2C_CONTROL_RS                  (0x1 << 1)
 125 +#define I2C_CONTROL_DMA_EN              (0x1 << 2)
 126 +#define I2C_CONTROL_CLK_EXT_EN          (0x1 << 3)
 127 +#define I2C_CONTROL_DIR_CHANGE          (0x1 << 4)
 128 +#define I2C_CONTROL_ACKERR_DET_EN       (0x1 << 5)
 129 +#define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6)
 130 +#define I2C_CONTROL_WRAPPER             (0x1 << 0)
 131 +
 132 +#define I2C_DRV_NAME           "mt-i2c"
 133 +
 134 +enum DMA_REGS_OFFSET {
 135 +       OFFSET_INT_FLAG = 0x0,
 136 +       OFFSET_INT_EN = 0x04,
 137 +       OFFSET_EN = 0x08,
 138 +       OFFSET_CON = 0x18,
 139 +       OFFSET_TX_MEM_ADDR = 0x1c,
 140 +       OFFSET_RX_MEM_ADDR = 0x20,
 141 +       OFFSET_TX_LEN = 0x24,
 142 +       OFFSET_RX_LEN = 0x28,
 143 +};
 144 +
 145 +enum i2c_trans_st_rs {
 146 +       I2C_TRANS_STOP = 0,
 147 +       I2C_TRANS_REPEATED_START,
 148 +};
 149 +
 150 +enum mtk_trans_op {
 151 +       I2C_MASTER_WR = 1,
 152 +       I2C_MASTER_RD,
 153 +       I2C_MASTER_WRRD,
 154 +};
 155 +
 156 +enum I2C_REGS_OFFSET {
 157 +       OFFSET_DATA_PORT = 0x0,
 158 +       OFFSET_SLAVE_ADDR = 0x04,
 159 +       OFFSET_INTR_MASK = 0x08,
 160 +       OFFSET_INTR_STAT = 0x0c,
 161 +       OFFSET_CONTROL = 0x10,
 162 +       OFFSET_TRANSFER_LEN = 0x14,
 163 +       OFFSET_TRANSAC_LEN = 0x18,
 164 +       OFFSET_DELAY_LEN = 0x1c,
 165 +       OFFSET_TIMING = 0x20,
 166 +       OFFSET_START = 0x24,
 167 +       OFFSET_EXT_CONF = 0x28,
 168 +       OFFSET_FIFO_STAT = 0x30,
 169 +       OFFSET_FIFO_THRESH = 0x34,
 170 +       OFFSET_FIFO_ADDR_CLR = 0x38,
 171 +       OFFSET_IO_CONFIG = 0x40,
 172 +       OFFSET_RSV_DEBUG = 0x44,
 173 +       OFFSET_HS = 0x48,
 174 +       OFFSET_SOFTRESET = 0x50,
 175 +       OFFSET_DCM_EN = 0x54,
 176 +       OFFSET_PATH_DIR = 0x60,
 177 +       OFFSET_DEBUGSTAT = 0x64,
 178 +       OFFSET_DEBUGCTRL = 0x68,
 179 +       OFFSET_TRANSFER_LEN_AUX = 0x6c,
 180 +};
 181 +
 182 +struct mtk_i2c_data {
 183 +       unsigned int clk_frequency;     /* bus speed in Hz */
 184 +       unsigned int flags;
 185 +       unsigned int clk_src_div;
 186 +};
 187 +
 188 +struct mtk_i2c_compatible {
 189 +       const struct i2c_adapter_quirks *quirks;
 190 +       unsigned char pmic_i2c;
 191 +       unsigned char dcm;
 192 +};
 193 +
 194 +struct mtk_i2c {
 195 +       struct i2c_adapter adap;        /* i2c host adapter */
 196 +       struct device *dev;
 197 +       struct completion msg_complete;
 198 +
 199 +       /* set in i2c probe */
 200 +       void __iomem *base;             /* i2c base addr */
 201 +       void __iomem *pdmabase;         /* dma base address*/
 202 +       struct clk *clk_main;           /* main clock for i2c bus */
 203 +       struct clk *clk_dma;            /* DMA clock for i2c via DMA */
 204 +       struct clk *clk_pmic;           /* PMIC clock for i2c from PMIC */
 205 +       bool have_pmic;                 /* can use i2c pins from PMIC */
 206 +       bool use_push_pull;             /* IO config push-pull mode */
 207 +
 208 +       u16 irq_stat;                   /* interrupt status */
 209 +       unsigned int speed_hz;          /* The speed in transfer */
 210 +       enum mtk_trans_op op;
 211 +       u16 timing_reg;
 212 +       u16 high_speed_reg;
 213 +       const struct mtk_i2c_compatible *dev_comp;
 214 +};
 215 +
 216 +static const struct i2c_adapter_quirks mt6577_i2c_quirks = {
 217 +       .flags = I2C_AQ_COMB_WRITE_THEN_READ,
 218 +       .max_num_msgs = MAX_MSG_NUM_MT6577,
 219 +       .max_write_len = MAX_DMA_TRANS_SIZE_MT6577,
 220 +       .max_read_len = MAX_DMA_TRANS_SIZE_MT6577,
 221 +       .max_comb_1st_msg_len = MAX_DMA_TRANS_SIZE_MT6577,
 222 +       .max_comb_2nd_msg_len = MAX_WRRD_TRANS_SIZE_MT6577,
 223 +};
 224 +
 225 +static const struct mtk_i2c_compatible mt6577_compat = {
 226 +       .quirks = &mt6577_i2c_quirks,
 227 +       .pmic_i2c = 0,
 228 +       .dcm = 1,
 229 +};
 230 +
 231 +static const struct mtk_i2c_compatible mt6589_compat = {
 232 +       .quirks = &mt6577_i2c_quirks,
 233 +       .pmic_i2c = 1,
 234 +       .dcm = 0,
 235 +};
 236 +
 237 +static const struct of_device_id mtk_i2c_of_match[] = {
 238 +       { .compatible = "mediatek,mt6577-i2c", .data = (void *)&mt6577_compat },
 239 +       { .compatible = "mediatek,mt6589-i2c", .data = (void *)&mt6589_compat },
 240 +       {}
 241 +};
 242 +MODULE_DEVICE_TABLE(of, mtk_i2c_of_match);
 243 +
 244 +static inline void mtk_i2c_writew(u16 value, struct mtk_i2c *i2c, u8 offset)
 245 +{
 246 +       writew(value, i2c->base + offset);
 247 +}
 248 +
 249 +static inline u16 mtk_i2c_readw(struct mtk_i2c *i2c, u8 offset)
 250 +{
 251 +       return readw(i2c->base + offset);
 252 +}
 253 +
 254 +static inline void mtk_i2c_writel_dma(u32 value, struct mtk_i2c *i2c, u8 offset)
 255 +{
 256 +       writel(value, i2c->pdmabase + offset);
 257 +}
 258 +
 259 +static int mtk_i2c_clock_enable(struct mtk_i2c *i2c)
 260 +{
 261 +       int ret;
 262 +
 263 +       ret = clk_prepare_enable(i2c->clk_dma);
 264 +       if (ret)
 265 +               return ret;
 266 +
 267 +       ret = clk_prepare_enable(i2c->clk_main);
 268 +       if (ret)
 269 +               goto err_main;
 270 +
 271 +       if (i2c->have_pmic) {
 272 +               ret = clk_prepare_enable(i2c->clk_pmic);
 273 +               if (ret)
 274 +                       goto err_pmic;
 275 +       }
 276 +       return 0;
 277 +
 278 +err_pmic:
 279 +       clk_disable_unprepare(i2c->clk_main);
 280 +err_main:
 281 +       clk_disable_unprepare(i2c->clk_dma);
 282 +
 283 +       return ret;
 284 +}
 285 +
 286 +static void mtk_i2c_clock_disable(struct mtk_i2c *i2c)
 287 +{
 288 +       if (i2c->have_pmic)
 289 +               clk_disable_unprepare(i2c->clk_pmic);
 290 +
 291 +       clk_disable_unprepare(i2c->clk_main);
 292 +       clk_disable_unprepare(i2c->clk_dma);
 293 +}
 294 +
 295 +static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
 296 +{
 297 +       u16 control_reg;
 298 +
 299 +       mtk_i2c_writew(I2C_SOFT_RST, i2c, OFFSET_SOFTRESET);
 300 +       /* Set ioconfig */
 301 +       if (i2c->use_push_pull)
 302 +               mtk_i2c_writew(I2C_IO_CONFIG_PUSH_PULL, i2c, OFFSET_IO_CONFIG);
 303 +       else
 304 +               mtk_i2c_writew(I2C_IO_CONFIG_OPEN_DRAIN, i2c, OFFSET_IO_CONFIG);
 305 +
 306 +       if (i2c->dev_comp->dcm)
 307 +               mtk_i2c_writew(I2C_DCM_DISABLE, i2c, OFFSET_DCM_EN);
 308 +
 309 +       mtk_i2c_writew(i2c->timing_reg, i2c, OFFSET_TIMING);
 310 +       mtk_i2c_writew(i2c->high_speed_reg, i2c, OFFSET_HS);
 311 +
 312 +       /* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */
 313 +       if (i2c->have_pmic)
 314 +               mtk_i2c_writew(I2C_CONTROL_WRAPPER, i2c, OFFSET_PATH_DIR);
 315 +
 316 +       control_reg = I2C_CONTROL_ACKERR_DET_EN |
 317 +               I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN;
 318 +       mtk_i2c_writew(control_reg, i2c, OFFSET_CONTROL);
 319 +       mtk_i2c_writew(I2C_DELAY_LEN, i2c, OFFSET_DELAY_LEN);
 320 +}
 321 +
 322 +/* calculate i2c port speed */
 323 +static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int clk_src_in_hz)
 324 +{
 325 +       unsigned int khz;
 326 +       unsigned int step_cnt;
 327 +       unsigned int sample_cnt;
 328 +       unsigned int sclk;
 329 +       unsigned int hclk;
 330 +       unsigned int max_step_cnt;
 331 +       unsigned int sample_div = MAX_SAMPLE_CNT_DIV;
 332 +       unsigned int step_div;
 333 +       unsigned int min_div;
 334 +       unsigned int best_mul;
 335 +       unsigned int cnt_mul;
 336 +
 337 +       if (i2c->speed_hz > MAX_HS_MODE_SPEED)
 338 +               return -EINVAL;
 339 +       else if (i2c->speed_hz > MAX_FS_MODE_SPEED)
 340 +               max_step_cnt = MAX_HS_STEP_CNT_DIV;
 341 +       else
 342 +               max_step_cnt = MAX_STEP_CNT_DIV;
 343 +
 344 +       step_div = max_step_cnt;
 345 +       /* Find the best combination */
 346 +       khz = i2c->speed_hz / 1000;
 347 +       hclk = clk_src_in_hz / 1000;
 348 +       min_div = ((hclk >> 1) + khz - 1) / khz;
 349 +       best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt;
 350 +
 351 +       for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) {
 352 +               step_cnt = (min_div + sample_cnt - 1) / sample_cnt;
 353 +               cnt_mul = step_cnt * sample_cnt;
 354 +               if (step_cnt > max_step_cnt)
 355 +                       continue;
 356 +
 357 +               if (cnt_mul < best_mul) {
 358 +                       best_mul = cnt_mul;
 359 +                       sample_div = sample_cnt;
 360 +                       step_div = step_cnt;
 361 +                       if (best_mul == min_div)
 362 +                               break;
 363 +               }
 364 +       }
 365 +
 366 +       sample_cnt = sample_div;
 367 +       step_cnt = step_div;
 368 +       sclk = hclk / (2 * sample_cnt * step_cnt);
 369 +       if (sclk > khz) {
 370 +               dev_dbg(i2c->dev, "%s mode: unsupported speed (%ldkhz)\n",
 371 +                       (i2c->speed_hz > MAX_HS_MODE_SPEED) ? "HS" : "ST/FT",
 372 +                       (long int)khz);
 373 +               return -ENOTSUPP;
 374 +       }
 375 +
 376 +       step_cnt--;
 377 +       sample_cnt--;
 378 +
 379 +       if (i2c->speed_hz > MAX_FS_MODE_SPEED) {
 380 +               /* Set the hign speed mode register */
 381 +               i2c->timing_reg = I2C_FS_TIME_INIT_VALUE;
 382 +               i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE |
 383 +                       (sample_cnt & I2C_TIMING_SAMPLE_COUNT_MASK) << 12 |
 384 +                       (step_cnt & I2C_TIMING_SAMPLE_COUNT_MASK) << 8;
 385 +       } else {
 386 +               i2c->timing_reg =
 387 +                       (sample_cnt & I2C_TIMING_SAMPLE_COUNT_MASK) << 8 |
 388 +                       (step_cnt & I2C_TIMING_STEP_DIV_MASK) << 0;
 389 +               /* Disable the high speed transaction */
 390 +               i2c->high_speed_reg = I2C_TIME_CLR_VALUE;
 391 +       }
 392 +
 393 +       return 0;
 394 +}
 395 +
 396 +static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs)
 397 +{
 398 +       u16 addr_reg;
 399 +       u16 control_reg;
 400 +       dma_addr_t rpaddr = 0;
 401 +       dma_addr_t wpaddr = 0;
 402 +       int ret;
 403 +
 404 +       i2c->irq_stat = 0;
 405 +
 406 +       reinit_completion(&i2c->msg_complete);
 407 +
 408 +       control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) &
 409 +                       ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS);
 410 +       if (i2c->speed_hz > 400000)
 411 +               control_reg |= I2C_CONTROL_RS;
 412 +       if (i2c->op == I2C_MASTER_WRRD)
 413 +               control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS;
 414 +       mtk_i2c_writew(control_reg, i2c, OFFSET_CONTROL);
 415 +
 416 +       /* set start condition */
 417 +       if (i2c->speed_hz <= 100000)
 418 +               mtk_i2c_writew(I2C_ST_START_CON, i2c, OFFSET_EXT_CONF);
 419 +       else
 420 +               mtk_i2c_writew(I2C_FS_START_CON, i2c, OFFSET_EXT_CONF);
 421 +
 422 +       addr_reg = msgs->addr << 1;
 423 +       if (i2c->op == I2C_MASTER_RD)
 424 +               addr_reg |= 0x1;
 425 +       mtk_i2c_writew(addr_reg, i2c, OFFSET_SLAVE_ADDR);
 426 +
 427 +       /* Clear interrupt status */
 428 +       mtk_i2c_writew(I2C_HS_NACKERR | I2C_ACKERR | I2C_TRANSAC_COMP,
 429 +               i2c, OFFSET_INTR_STAT);
 430 +       mtk_i2c_writew(I2C_FIFO_ADDR_CLR, i2c, OFFSET_FIFO_ADDR_CLR);
 431 +
 432 +       /* Enable interrupt */
 433 +       mtk_i2c_writew(I2C_HS_NACKERR | I2C_ACKERR | I2C_TRANSAC_COMP,
 434 +               i2c, OFFSET_INTR_MASK);
 435 +
 436 +       /* Set transfer and transaction len */
 437 +       if (i2c->op == I2C_MASTER_WRRD) {
 438 +               mtk_i2c_writew(msgs->len | ((msgs + 1)->len) << 8,
 439 +                       i2c, OFFSET_TRANSFER_LEN);
 440 +               mtk_i2c_writew(I2C_WRRD_TRANAC_VALUE, i2c, OFFSET_TRANSAC_LEN);
 441 +       } else {
 442 +               mtk_i2c_writew(msgs->len, i2c, OFFSET_TRANSFER_LEN);
 443 +               mtk_i2c_writew(I2C_RD_TRANAC_VALUE, i2c, OFFSET_TRANSAC_LEN);
 444 +       }
 445 +
 446 +       /* Prepare buffer data to start transfer */
 447 +       if (i2c->op == I2C_MASTER_RD) {
 448 +               mtk_i2c_writel_dma(I2C_DMA_INT_FLAG_NONE, i2c, OFFSET_INT_FLAG);
 449 +               mtk_i2c_writel_dma(I2C_DMA_CON_RX, i2c, OFFSET_CON);
 450 +               rpaddr = dma_map_single(i2c->adap.dev.parent, msgs->buf,
 451 +                                               msgs->len, DMA_FROM_DEVICE);
 452 +               if (dma_mapping_error(i2c->adap.dev.parent, rpaddr))
 453 +                       return -ENOMEM;
 454 +               mtk_i2c_writel_dma((u32)rpaddr, i2c, OFFSET_RX_MEM_ADDR);
 455 +               mtk_i2c_writel_dma(msgs->len, i2c, OFFSET_RX_LEN);
 456 +       } else if (i2c->op == I2C_MASTER_WR) {
 457 +               mtk_i2c_writel_dma(I2C_DMA_INT_FLAG_NONE, i2c, OFFSET_INT_FLAG);
 458 +               mtk_i2c_writel_dma(I2C_DMA_CON_TX, i2c, OFFSET_CON);
 459 +               wpaddr = dma_map_single(i2c->adap.dev.parent, msgs->buf,
 460 +                                               msgs->len, DMA_TO_DEVICE);
 461 +               if (dma_mapping_error(i2c->adap.dev.parent, wpaddr))
 462 +                       return -ENOMEM;
 463 +               mtk_i2c_writel_dma((u32)wpaddr, i2c, OFFSET_TX_MEM_ADDR);
 464 +               mtk_i2c_writel_dma(msgs->len, i2c, OFFSET_TX_LEN);
 465 +       } else {
 466 +               mtk_i2c_writel_dma(I2C_DMA_CLR_FLAG, i2c, OFFSET_INT_FLAG);
 467 +               mtk_i2c_writel_dma(I2C_DMA_CLR_FLAG, i2c, OFFSET_CON);
 468 +               wpaddr = dma_map_single(i2c->adap.dev.parent, msgs->buf,
 469 +                                               msgs->len, DMA_TO_DEVICE);
 470 +               if (dma_mapping_error(i2c->adap.dev.parent, wpaddr))
 471 +                       return -ENOMEM;
 472 +               rpaddr = dma_map_single(i2c->adap.dev.parent, (msgs + 1)->buf,
 473 +                                               (msgs + 1)->len,
 474 +                                               DMA_FROM_DEVICE);
 475 +               if (dma_mapping_error(i2c->adap.dev.parent, rpaddr)) {
 476 +                       dma_unmap_single(i2c->adap.dev.parent, wpaddr,
 477 +                                               msgs->len, DMA_TO_DEVICE);
 478 +                       return -ENOMEM;
 479 +               }
 480 +               mtk_i2c_writel_dma((u32)wpaddr, i2c, OFFSET_TX_MEM_ADDR);
 481 +               mtk_i2c_writel_dma((u32)rpaddr, i2c, OFFSET_RX_MEM_ADDR);
 482 +               mtk_i2c_writel_dma(msgs->len, i2c, OFFSET_TX_LEN);
 483 +               mtk_i2c_writel_dma((msgs + 1)->len, i2c, OFFSET_RX_LEN);
 484 +       }
 485 +
 486 +       /* flush before sending start */
 487 +       mb();
 488 +       mtk_i2c_writel_dma(I2C_DMA_START_EN, i2c, OFFSET_EN);
 489 +       mtk_i2c_writew(I2C_TRANSAC_START, i2c, OFFSET_START);
 490 +
 491 +       ret = wait_for_completion_timeout(&i2c->msg_complete,
 492 +                               i2c->adap.timeout);
 493 +
 494 +       /* Clear interrupt mask */
 495 +       mtk_i2c_writew(~(I2C_HS_NACKERR | I2C_ACKERR
 496 +                       | I2C_TRANSAC_COMP), i2c, OFFSET_INTR_MASK);
 497 +
 498 +       if (i2c->op == I2C_MASTER_WR) {
 499 +               dma_unmap_single(i2c->adap.dev.parent, wpaddr,
 500 +                                       msgs->len, DMA_TO_DEVICE);
 501 +       } else if (i2c->op == I2C_MASTER_RD) {
 502 +               dma_unmap_single(i2c->adap.dev.parent, rpaddr,
 503 +                                       msgs->len, DMA_FROM_DEVICE);
 504 +       } else {
 505 +               dma_unmap_single(i2c->adap.dev.parent, wpaddr, msgs->len,
 506 +                                       DMA_TO_DEVICE);
 507 +               dma_unmap_single(i2c->adap.dev.parent, rpaddr, (msgs + 1)->len,
 508 +                                       DMA_FROM_DEVICE);
 509 +       }
 510 +
 511 +       if (ret == 0) {
 512 +               dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr);
 513 +               mtk_i2c_init_hw(i2c);
 514 +               return -ETIMEDOUT;
 515 +       }
 516 +
 517 +       completion_done(&i2c->msg_complete);
 518 +
 519 +       if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) {
 520 +               dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr);
 521 +               mtk_i2c_init_hw(i2c);
 522 +               return -EREMOTEIO;
 523 +       }
 524 +
 525 +       return 0;
 526 +}
 527 +
 528 +static int mtk_i2c_transfer(struct i2c_adapter *adap,
 529 +       struct i2c_msg msgs[], int num)
 530 +{
 531 +       int ret;
 532 +       int left_num = num;
 533 +       struct mtk_i2c *i2c = i2c_get_adapdata(adap);
 534 +
 535 +       ret = mtk_i2c_clock_enable(i2c);
 536 +       if (ret)
 537 +               return ret;
 538 +
 539 +       if (msgs->buf == NULL) {
 540 +               dev_dbg(i2c->dev, "data buffer is NULL.\n");
 541 +               ret = -EINVAL;
 542 +               goto err_exit;
 543 +       }
 544 +
 545 +       if (msgs->flags & I2C_M_RD)
 546 +               i2c->op = I2C_MASTER_RD;
 547 +       else
 548 +               i2c->op = I2C_MASTER_WR;
 549 +
 550 +       if (num > 1) {
 551 +               /* combined two messages into one transaction */
 552 +               i2c->op = I2C_MASTER_WRRD;
 553 +               left_num--;
 554 +       }
 555 +
 556 +       /* always use DMA mode. */
 557 +       ret = mtk_i2c_do_transfer(i2c, msgs);
 558 +       if (ret < 0)
 559 +               goto err_exit;
 560 +
 561 +       /* the return value is number of executed messages */
 562 +       ret = num;
 563 +
 564 +err_exit:
 565 +       mtk_i2c_clock_disable(i2c);
 566 +       return ret;
 567 +}
 568 +
 569 +static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id)
 570 +{
 571 +       struct mtk_i2c *i2c = dev_id;
 572 +
 573 +       i2c->irq_stat = mtk_i2c_readw(i2c, OFFSET_INTR_STAT);
 574 +       mtk_i2c_writew(I2C_HS_NACKERR | I2C_ACKERR
 575 +                       | I2C_TRANSAC_COMP, i2c, OFFSET_INTR_STAT);
 576 +
 577 +       complete(&i2c->msg_complete);
 578 +
 579 +       return IRQ_HANDLED;
 580 +}
 581 +
 582 +static u32 mtk_i2c_functionality(struct i2c_adapter *adap)
 583 +{
 584 +       return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 585 +}
 586 +
 587 +static const struct i2c_algorithm mtk_i2c_algorithm = {
 588 +       .master_xfer = mtk_i2c_transfer,
 589 +       .functionality = mtk_i2c_functionality,
 590 +};
 591 +
 592 +static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c,
 593 +       unsigned int *clk_src_div)
 594 +{
 595 +       int ret;
 596 +
 597 +       ret = of_property_read_u32(np, "clock-frequency", &i2c->speed_hz);
 598 +       if (ret < 0)
 599 +               i2c->speed_hz = I2C_DEFAUT_SPEED;
 600 +
 601 +       ret = of_property_read_u32(np, "clock-div", clk_src_div);
 602 +       if (ret < 0)
 603 +               return ret;
 604 +
 605 +       if (*clk_src_div == 0)
 606 +               return -EINVAL;
 607 +
 608 +       i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic");
 609 +       i2c->use_push_pull =
 610 +               of_property_read_bool(np, "mediatek,use-push-pull");
 611 +
 612 +       return 0;
 613 +}
 614 +
 615 +static int mtk_i2c_probe(struct platform_device *pdev)
 616 +{
 617 +       const struct of_device_id *of_id;
 618 +       int ret = 0;
 619 +       struct mtk_i2c *i2c;
 620 +       struct clk *clk;
 621 +       unsigned int clk_src_in_hz;
 622 +       unsigned int clk_src_div;
 623 +       struct resource *res;
 624 +       int irq;
 625 +
 626 +       i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
 627 +       if (i2c == NULL)
 628 +               return -ENOMEM;
 629 +
 630 +       ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c, &clk_src_div);
 631 +       if (ret)
 632 +               return -EINVAL;
 633 +
 634 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 635 +       i2c->base = devm_ioremap_resource(&pdev->dev, res);
 636 +       if (IS_ERR(i2c->base))
 637 +               return PTR_ERR(i2c->base);
 638 +
 639 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 640 +       i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res);
 641 +       if (IS_ERR(i2c->pdmabase))
 642 +               return PTR_ERR(i2c->pdmabase);
 643 +
 644 +       irq = platform_get_irq(pdev, 0);
 645 +       if (irq <= 0)
 646 +               return irq;
 647 +
 648 +       init_completion(&i2c->msg_complete);
 649 +
 650 +       of_id = of_match_node(mtk_i2c_of_match, pdev->dev.of_node);
 651 +       if (!of_id)
 652 +               return -EINVAL;
 653 +
 654 +       i2c->dev_comp = of_id->data;
 655 +       i2c->adap.dev.of_node = pdev->dev.of_node;
 656 +       i2c->dev = &i2c->adap.dev;
 657 +       i2c->adap.dev.parent = &pdev->dev;
 658 +       i2c->adap.owner = THIS_MODULE;
 659 +       i2c->adap.algo = &mtk_i2c_algorithm;
 660 +       i2c->adap.quirks = i2c->dev_comp->quirks;
 661 +       i2c->adap.timeout = 2 * HZ;
 662 +       i2c->adap.retries = 1;
 663 +
 664 +       if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c)
 665 +               return -EINVAL;
 666 +
 667 +       i2c->clk_main = devm_clk_get(&pdev->dev, "main");
 668 +       if (IS_ERR(i2c->clk_main)) {
 669 +               dev_err(&pdev->dev, "cannot get main clock\n");
 670 +               return PTR_ERR(i2c->clk_main);
 671 +       }
 672 +
 673 +       i2c->clk_dma = devm_clk_get(&pdev->dev, "dma");
 674 +       if (IS_ERR(i2c->clk_dma)) {
 675 +               dev_err(&pdev->dev, "cannot get dma clock\n");
 676 +               return PTR_ERR(i2c->clk_dma);
 677 +       }
 678 +
 679 +       clk = i2c->clk_main;
 680 +       if (i2c->have_pmic) {
 681 +               i2c->clk_pmic = devm_clk_get(&pdev->dev, "pmic");
 682 +               if (IS_ERR(i2c->clk_pmic)) {
 683 +                       dev_err(&pdev->dev, "cannot get pmic clock\n");
 684 +                       return PTR_ERR(i2c->clk_pmic);
 685 +               }
 686 +               clk = i2c->clk_pmic;
 687 +       }
 688 +       clk_src_in_hz = clk_get_rate(clk) / clk_src_div;
 689 +
 690 +       dev_dbg(&pdev->dev, "clock source %p,clock src frequency %d\n",
 691 +               i2c->clk_main, clk_src_in_hz);
 692 +       strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name));
 693 +
 694 +       ret = mtk_i2c_set_speed(i2c, clk_src_in_hz);
 695 +       if (ret) {
 696 +               dev_err(&pdev->dev, "Failed to set the speed.\n");
 697 +               return -EINVAL;
 698 +       }
 699 +
 700 +       ret = mtk_i2c_clock_enable(i2c);
 701 +       if (ret) {
 702 +               dev_err(&pdev->dev, "clock enable failed!\n");
 703 +               return ret;
 704 +       }
 705 +       mtk_i2c_init_hw(i2c);
 706 +       mtk_i2c_clock_disable(i2c);
 707 +
 708 +       ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq,
 709 +               IRQF_TRIGGER_NONE, I2C_DRV_NAME, i2c);
 710 +       if (ret < 0) {
 711 +               dev_err(&pdev->dev,
 712 +                       "Request I2C IRQ %d fail\n", irq);
 713 +               return ret;
 714 +       }
 715 +
 716 +       i2c_set_adapdata(&i2c->adap, i2c);
 717 +       ret = i2c_add_adapter(&i2c->adap);
 718 +       if (ret) {
 719 +               dev_err(&pdev->dev, "Failed to add i2c bus to i2c core\n");
 720 +               return ret;
 721 +       }
 722 +
 723 +       platform_set_drvdata(pdev, i2c);
 724 +
 725 +       return 0;
 726 +}
 727 +
 728 +static int mtk_i2c_remove(struct platform_device *pdev)
 729 +{
 730 +       struct mtk_i2c *i2c = platform_get_drvdata(pdev);
 731 +
 732 +       i2c_del_adapter(&i2c->adap);
 733 +
 734 +       return 0;
 735 +}
 736 +
 737 +static struct platform_driver mtk_i2c_driver = {
 738 +       .probe = mtk_i2c_probe,
 739 +       .remove = mtk_i2c_remove,
 740 +       .driver = {
 741 +               .name = I2C_DRV_NAME,
 742 +               .of_match_table = of_match_ptr(mtk_i2c_of_match),
 743 +       },
 744 +};
 745 +
 746 +module_platform_driver(mtk_i2c_driver);
 747 +
 748 +MODULE_LICENSE("GPL v2");
 749 +MODULE_DESCRIPTION("MediaTek I2C Bus Driver");
 750 +MODULE_AUTHOR("Xudong Chen <xudong.chen@mediatek.com>");