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mediatek: add support for the new MT7623 Arm SoC
[openwrt/openwrt.git] / target / linux / mediatek / patches / 0061-arm-mediatek-add-mt7623-clock.patch
1 From 7342787e992a70443081b9203d2131cbf6bc3562 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sat, 27 Jun 2015 13:12:38 +0200
4 Subject: [PATCH 61/76] arm: mediatek: add mt7623 clock
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 drivers/clk/mediatek/Makefile | 1 +
9 drivers/clk/mediatek/clk-mt7623.c | 634 ++++++++++++++++++++++++++++++++
10 include/dt-bindings/clock/mt7623-clk.h | 173 +++++++++
11 3 files changed, 808 insertions(+)
12 create mode 100644 drivers/clk/mediatek/clk-mt7623.c
13 create mode 100644 include/dt-bindings/clock/mt7623-clk.h
14
15 diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
16 index 8e4b2a4..19a3763 100644
17 --- a/drivers/clk/mediatek/Makefile
18 +++ b/drivers/clk/mediatek/Makefile
19 @@ -1,4 +1,5 @@
20 obj-y += clk-mtk.o clk-pll.o clk-gate.o
21 obj-$(CONFIG_RESET_CONTROLLER) += reset.o
22 +obj-y += clk-mt7623.o
23 obj-y += clk-mt8135.o
24 obj-y += clk-mt8173.o
25 diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c
26 new file mode 100644
27 index 0000000..07843bb
28 --- /dev/null
29 +++ b/drivers/clk/mediatek/clk-mt7623.c
30 @@ -0,0 +1,634 @@
31 +/*
32 + * Copyright (c) 2014 MediaTek Inc.
33 + * Author: James Liao <jamesjj.liao@mediatek.com>
34 + *
35 + * This program is free software; you can redistribute it and/or modify
36 + * it under the terms of the GNU General Public License version 2 as
37 + * published by the Free Software Foundation.
38 + *
39 + * This program is distributed in the hope that it will be useful,
40 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
41 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
42 + * GNU General Public License for more details.
43 + */
44 +
45 +#include <linux/of.h>
46 +#include <linux/of_address.h>
47 +#include <linux/slab.h>
48 +#include <linux/mfd/syscon.h>
49 +#include <dt-bindings/clock/mt7623-clk.h>
50 +
51 +#include "clk-mtk.h"
52 +#include "clk-gate.h"
53 +
54 +static DEFINE_SPINLOCK(mt7623_clk_lock);
55 +
56 +static struct clk_onecell_data *mt7623_top_clk_data;
57 +static struct clk_onecell_data *mt7623_pll_clk_data;
58 +
59 +static void mtk_clk_enable_critical(void)
60 +{
61 + if (!mt7623_top_clk_data || !mt7623_pll_clk_data)
62 + return;
63 +
64 + clk_prepare_enable(mt7623_pll_clk_data->clks[CLK_APMIXED_ARMPLL]);
65 + clk_prepare_enable(mt7623_top_clk_data->clks[CLK_TOP_MEM_SEL]);
66 + clk_prepare_enable(mt7623_top_clk_data->clks[CLK_TOP_DDR_SEL]);
67 + clk_prepare_enable(mt7623_top_clk_data->clks[CLK_TOP_RTC_SEL]);
68 +}
69 +
70 +static const struct mtk_fixed_factor root_clk_alias[] __initconst = {
71 + FACTOR(CLK_TOP_DSI0_LNTC_DSICLK, "dsi0_lntc_dsiclk", "clk_null", 1, 1),
72 + FACTOR(CLK_TOP_HDMITX_CLKDIG_CTS, "hdmitx_clkdig_cts", "clk_null", 1, 1),
73 + FACTOR(CLK_TOP_CLKPH_MCK, "clkph_mck", "clk_null", 1, 1),
74 + FACTOR(CLK_TOP_CPUM_TCK_IN, "cpum_tck_in", "clk_null", 1, 1),
75 +};
76 +
77 +static const struct mtk_fixed_factor top_divs[] __initconst = {
78 + FACTOR(CLK_TOP_MAINPLL_806M, "mainpll_650m", "mainpll", 1, 2),
79 + FACTOR(CLK_TOP_MAINPLL_537P3M, "mainpll_433p3m", "mainpll", 1, 3),
80 + FACTOR(CLK_TOP_MAINPLL_322P4M, "mainpll_260m", "mainpll", 1, 5),
81 + FACTOR(CLK_TOP_MAINPLL_230P3M, "mainpll_185p6m", "mainpll", 1, 7),
82 +
83 + FACTOR(CLK_TOP_UNIVPLL_624M, "univpll_624m", "univpll", 1, 2),
84 + FACTOR(CLK_TOP_UNIVPLL_416M, "univpll_416m", "univpll", 1, 3),
85 + FACTOR(CLK_TOP_UNIVPLL_249P6M, "univpll_249p6m", "univpll", 1, 5),
86 + FACTOR(CLK_TOP_UNIVPLL_178P3M, "univpll_178p3m", "univpll", 1, 7),
87 + FACTOR(CLK_TOP_UNIVPLL_48M, "univpll_48m", "univpll", 1, 26),
88 +
89 + FACTOR(CLK_TOP_AUDPLL_D4, "audpll_d4", "audpll", 1, 4),
90 + FACTOR(CLK_TOP_AUDPLL_D8, "audpll_d8", "audpll", 1, 8),
91 + FACTOR(CLK_TOP_AUDPLL_D16, "audpll_d16", "audpll", 1, 16),
92 + FACTOR(CLK_TOP_AUDPLL_24, "audpll_d24", "audpll", 1, 24),
93 +
94 + FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2),
95 + FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4),
96 + FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8),
97 + FACTOR(CLK_TOP_LVDS_ETH, "lvdspll_eth", "lvdspll", 1, 16),
98 +
99 + FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
100 +
101 + FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
102 +
103 + FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll_650m", 1, 2),
104 + FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "mainpll_650m", 1, 4),
105 + FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll_650m", 1, 8),
106 + FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "mainpll_650m", 1, 16),
107 + FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "mainpll_650m", 1, 2),
108 + FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "mainpll_650m", 1, 4),
109 + FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "mainpll_650m", 1, 8),
110 + FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll_650m", 1, 2),
111 + FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "mainpll_650m", 1, 4),
112 + FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll_650m", 1, 2),
113 + FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "mainpll_650m", 1, 4),
114 + FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll_433p3m", 1, 1),
115 + FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll_260m", 1, 1),
116 + FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll_185p6m", 1, 1),
117 +
118 + FACTOR(CLK_TOP_TVDPLL_d2, "tvdpll_d2", "tvdpll", 1, 2),
119 + FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
120 +
121 + FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_624m", 1, 2),
122 + FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_624m", 1, 4),
123 + FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_624m", 1, 8),
124 + FACTOR(CLK_TOP_UNIVPLL1_D10, "univpll1_d10", "univpll_624m", 1, 10),
125 +
126 + FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_416m", 1, 2),
127 + FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_416m", 1, 4),
128 + FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_416m", 1, 8),
129 +
130 + FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_624m", 1, 2),
131 + FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_624m", 1, 4),
132 + FACTOR(CLK_TOP_UNIVPLL1_D6, "univpll1_d6", "univpll_624m", 1, 6),
133 + FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_624m", 1, 8),
134 + FACTOR(CLK_TOP_UNIVPLL1_D10, "univpll1_d10", "univpll_624m", 1, 10),
135 +
136 + FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_416m", 1, 2),
137 + FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_416m", 1, 4),
138 + FACTOR(CLK_TOP_UNIVPLL2_D6, "univpll2_d6", "univpll_416m", 1, 6),
139 + FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_416m", 1, 8),
140 +
141 + FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_249p6m", 1, 1),
142 + FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_48m", 1, 1),
143 +
144 +
145 + FACTOR(CLK_TOP_MEMPLL_MCK_D4, "mempll_mck_d4", "clkph_mck", 1, 4),
146 +};
147 +
148 +static const char * const axi_parents[] __initconst = {
149 + "clk26m",
150 + "syspll1_d2",
151 + "syspll_d5",
152 + "syspll1_d4",
153 + "univpll_d5",
154 + "univpll2_d2",
155 + "dmpll_ck",
156 + "dmpll_d2"
157 +};
158 +
159 +static const char * const mem_parents[] __initconst = {
160 + "clk26m",
161 + "dmpll_ck",
162 +};
163 +
164 +static const char * const ddr_parents[] __initconst = {
165 + "clk26m",
166 + "syspll1_d8",
167 +};
168 +
169 +static const char * const mm_parents[] __initconst = {
170 + "clk26m",
171 + "clk26m",
172 + "vencpll_ck",
173 + "syspll1_d2",
174 + "syspll1_d4",
175 + "univpll_d5",
176 + "univpll1_d2",
177 + "univpll2_d2",
178 + "dmpll_ck"
179 +};
180 +
181 +static const char * const pwm_parents[] __initconst = {
182 + "clk26m",
183 + "univpll2_d4",
184 + "univpll3_d2",
185 + "univpll1_d4",
186 +};
187 +
188 +static const char * const vdec_parents[] __initconst = {
189 + "clk26m",
190 + "syspll1_d2",
191 + "syspll_d5",
192 + "syspll1_d4",
193 + "univpll_d5",
194 + "univpll2_d2",
195 + "univpll2_d4",
196 + "msdcpll_d2",
197 + "mmpll_d2",
198 +};
199 +
200 +static const char * const mfg_parents[] __initconst = {
201 + "clk26m",
202 + "mmpll_ck",
203 + "dmpll_x2_ck",
204 + "msdcpll_ck",
205 + "clk26m",
206 + "syspll_d3",
207 + "univpll_d3",
208 + "univpll1_d2",
209 +};
210 +
211 +static const char * const cam_parents[] __initconst = {
212 + "clk26m",
213 + "univpll_d26",
214 + "univpll2_d2",
215 + "syspll3_d2",
216 + "syspll3_d4",
217 + "msdcpll_d2",
218 + "mmpll_d2",
219 + "clk26m",
220 +};
221 +
222 +static const char * const uart_parents[] __initconst = {
223 + "clk26m",
224 + "univpll2_d8",
225 +};
226 +
227 +static const char * const spi_parents[] __initconst = {
228 + "clk26m",
229 + "syspll3_d2",
230 + "syspll4_d2",
231 + "univpll2_d4",
232 + "univpll1_d8",
233 +};
234 +
235 +static const char * const usb20_parents[] __initconst = {
236 + "clk26m",
237 + "univpll1_d8",
238 + "univpll3_d4",
239 + "clk26m",
240 +};
241 +
242 +static const char * const msdc_30_0_parents[] __initconst = {
243 + "clk26m",
244 + "msdcpll_d2",
245 + "syspll2_d2",
246 + "syspll1_d4",
247 + "univpll1_d4",
248 + "univpll2_d4",
249 + "clk26m",
250 + "clk26m",
251 +};
252 +
253 +static const char * const msdc_30_1_parents[] __initconst = {
254 + "clk26m",
255 + "msdcpll_d2",
256 + "syspll2_d2",
257 + "syspll1_d4",
258 + "univpll1_d4",
259 + "univpll2_d4",
260 + "clk26m",
261 + "clk26m",
262 +};
263 +
264 +static const char * const msdc_30_2_parents[] __initconst = {
265 + "clk26m",
266 + "msdcpll_d2",
267 + "syspll2_d2",
268 + "syspll1_d4",
269 + "univpll1_d4",
270 + "univpll2_d4",
271 + "clk26m",
272 + "clk26m",
273 +};
274 +
275 +static const char * const audio_parents[] __initconst = {
276 + "f_f26m_ck",
277 + "syspll1_d16",
278 +};
279 +
280 +static const char * const audio_intbus_parents[] __initconst = {
281 + "clk26m",
282 + "syspll1_d4",
283 + "syspll3_d2",
284 + "syspll4_d2",
285 + "univpll3_d2",
286 + "univpll2_d4",
287 +};
288 +
289 +static const char * const pmic_spi_parents[] __initconst = {
290 + "clk26m",
291 + "syspll1_d8",
292 + "syspll2_d4",
293 + "syspll4_d2",
294 + "syspll3_d4",
295 + "syspll2_d8",
296 + "syspll1_d16",
297 + "univpll3_d4",
298 + "univpll_d26",
299 + "dmpll_d2",
300 + "dmpll_d4",
301 +};
302 +
303 +static const char * const scp_parents[] __initconst = {
304 + "clk26m",
305 + "syspll1_d8",
306 + "dmpll_d2",
307 + "dmpll_d4",
308 +};
309 +
310 +static const char * const dpi0_parents[] __initconst = {
311 + "clk26m",
312 + "mipipll",
313 + "mipipll_d2",
314 + "mipipll_d4",
315 + "lvdspll",
316 + "lvdspll_d2",
317 + "lvdspll_d4",
318 + "lvdspll_d8",
319 +};
320 +
321 +static const char * const dpi1_parents[] __initconst = {
322 + "clk26m",
323 + "tvdpll",
324 + "tvdpll_d2",
325 + "tvdpll_d4",
326 +};
327 +
328 +static const char * const tve_parents[] __initconst = {
329 + "clk26m",
330 + "mipipll",
331 + "mipipll_d2",
332 + "mipipll_d4",
333 + "clk26m",
334 + "tvdpll",
335 + "tvdpll_d2",
336 + "tvdpll_d4",
337 +};
338 +
339 +static const char * const apll_parents[] __initconst = {
340 + "clk26m",
341 + "audpll",
342 + "audpll_d4",
343 + "audpll_d8",
344 + "audpll_d16",
345 + "audpll_d24",
346 + "clk26m",
347 + "clk26m",
348 +};
349 +
350 +static const char * const dpilvds_parents[] __initconst = {
351 + "clk26m",
352 + "lvdspll",
353 + "lvdspll_d2",
354 + "lvdspll_d4",
355 + "lvdspll_d8",
356 + "fpc_ck",
357 + "clk26m",
358 + "clk26m",
359 +};
360 +
361 +static const char * const rtc_parents[] __initconst = {
362 + "clk32k",
363 + "external_32k",
364 + "clk26m",
365 + "univpll3_d8",
366 +};
367 +
368 +static const char * const nfi2x_parents[] __initconst = {
369 + "clk26m",
370 + "syspll2_d2",
371 + "syspll_d7",
372 + "univpll3_d2",
373 + "syspll2_d4",
374 + "univpll3_d4",
375 + "syspll4_d4",
376 + "clk26m",
377 +};
378 +
379 +static const char * const eth_parents[] __initconst = {
380 + "clk26m",
381 + "syspll3_d4",
382 + "univpll2_d8",
383 + "lvdspll_eth",
384 + "univpll_d26",
385 + "syspll2_d8",
386 + "syspll4_d4",
387 + "univpll3_d8",
388 +};
389 +
390 +static const struct mtk_composite top_muxes[] __initconst = {
391 + /* CLK_CFG_0 */
392 + MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
393 + 0x0140, 0, 3, INVALID_MUX_GATE_BIT),
394 + MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0040, 8, 2, 15),
395 + MUX_GATE(CLK_TOP_DDR_SEL, "ddr_sel", ddr_parents, 0x0040, 16, 2, 23),
396 + MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents,
397 + 0x0140, 24, 3, INVALID_MUX_GATE_BIT),
398 + /* CLK_CFG_1 */
399 + MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0050, 0, 2, 7),
400 + MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x0050, 8, 4, 15),
401 + MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0050, 16, 3, 23),
402 + MUX_GATE(CLK_TOP_CAM_SEL, "cam_sel", cam_parents, 0x0050, 24, 3, 31),
403 + /* CLK_CFG_2 */
404 + MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0060, 0, 1, 7),
405 + MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0060, 8, 3, 15),
406 + MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x0060, 16, 2, 23),
407 + MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc_30_0_sel", msdc_30_0_parents, 0x0060, 24, 3, 31),
408 + /* CLK_CFG_3 */
409 + MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc_30_1_sel", msdc_30_1_parents, 0x0070, 0, 3, 7),
410 + MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc_30_2_sel", msdc_30_2_parents, 0x0070, 8, 3, 15),
411 + MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 0x0070, 16, 1, 23),
412 + MUX_GATE(CLK_TOP_AUDIO_INTBUS_SEL,
413 + "audio_intbus_sel", audio_intbus_parents, 0x0070, 24, 3, 31),
414 + /* CLK_CFG_4 */
415 + MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmic_spi_parents, 0x0080, 0, 4, 7),
416 + MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x0080, 8, 2, 15),
417 + MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x0080, 16, 3, 23),
418 + MUX_GATE(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents, 0x0080, 24, 2, 31),
419 + /* CLK_CFG_5 */
420 + MUX_GATE(CLK_TOP_TVE_SEL, "tve_sel", tve_parents, 0x0090, 0, 3, 7),
421 + MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents, 0x0090, 16, 3, 23),
422 + MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x0090, 24, 3, 31),
423 + /* CLK_CFG_6 */
424 + MUX_GATE(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x00a0, 0, 2, 7),
425 + MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents, 0x00a0, 8, 3, 15),
426 + MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents, 0x00a0, 16, 3, 23),
427 +};
428 +
429 +static const struct mtk_gate_regs infra_cg_regs = {
430 + .set_ofs = 0x0040,
431 + .clr_ofs = 0x0044,
432 + .sta_ofs = 0x0048,
433 +};
434 +
435 +#define GATE_ICG(_id, _name, _parent, _shift) { \
436 + .id = _id, \
437 + .name = _name, \
438 + .parent_name = _parent, \
439 + .regs = &infra_cg_regs, \
440 + .shift = _shift, \
441 + .ops = &mtk_clk_gate_ops_setclr, \
442 + }
443 +
444 +static const struct mtk_gate infra_clks[] __initconst = {
445 + GATE_ICG(CLK_INFRA_DBGCLK, "dbgclk_ck", "axi_sel", 0),
446 + GATE_ICG(CLK_INFRA_SMI, "smi_ck", "smi_sel", 1),
447 + GATE_ICG(CLK_INFRA_AUDIO, "audio_ck", "aud_intbus_sel", 5),
448 + GATE_ICG(CLK_INFRA_EFUSE, "efuse_ck", "axi_sel", 5),
449 + GATE_ICG(CLK_INFRA_EFUSE, "l2c_sram_ck", "axi_sel", 5),
450 + GATE_ICG(CLK_INFRA_M4U, "m4u_ck", "mem_sel", 8),
451 + GATE_ICG(CLK_INFRA_CONNMCU, "connmcu_ck", "axi_sel", 8),
452 + GATE_ICG(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 8),
453 + GATE_ICG(CLK_INFRA_CPUM, "cpum_ck", "cpum_tck_in", 15),
454 + GATE_ICG(CLK_INFRA_KP, "kp_ck", "axi_sel", 16),
455 + GATE_ICG(CLK_INFRA_CEC, "cec_ck", "axi_sel", 16),
456 + GATE_ICG(CLK_INFRA_IRRX, "irrx_ck", "axi_sel", 16),
457 + GATE_ICG(CLK_INFRA_PMICSPI, "pmicspi_ck", "pmicspi_sel", 22),
458 + GATE_ICG(CLK_INFRA_PMIC_WRAP, "pmic_wrap_ck", "axi_sel", 23),
459 +};
460 +
461 +static const struct mtk_gate_regs peri0_cg_regs = {
462 + .set_ofs = 0x0008,
463 + .clr_ofs = 0x0010,
464 + .sta_ofs = 0x0018,
465 +};
466 +
467 +static const struct mtk_gate_regs peri1_cg_regs = {
468 + .set_ofs = 0x000c,
469 + .clr_ofs = 0x0014,
470 + .sta_ofs = 0x001c,
471 +};
472 +
473 +#define GATE_PERI0(_id, _name, _parent, _shift) { \
474 + .id = _id, \
475 + .name = _name, \
476 + .parent_name = _parent, \
477 + .regs = &peri0_cg_regs, \
478 + .shift = _shift, \
479 + .ops = &mtk_clk_gate_ops_setclr, \
480 + }
481 +
482 +#define GATE_PERI1(_id, _name, _parent, _shift) { \
483 + .id = _id, \
484 + .name = _name, \
485 + .parent_name = _parent, \
486 + .regs = &peri1_cg_regs, \
487 + .shift = _shift, \
488 + .ops = &mtk_clk_gate_ops_setclr, \
489 + }
490 +
491 +static const struct mtk_gate peri_gates[] __initconst = {
492 + /* PERI0 */
493 + GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "axi_sel", 0),
494 + GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1),
495 + GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axi_sel", 2),
496 + GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axi_sel", 3),
497 + GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axi_sel", 4),
498 + GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axi_sel", 5),
499 + GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axi_sel", 6),
500 + GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axi_sel", 7),
501 + GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axi_sel", 8),
502 + GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9),
503 + GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10),
504 + GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11),
505 + GATE_PERI0(CLK_PERI_AP_DMA, "ap_dma_ck", "axi_sel", 12),
506 + GATE_PERI0(CLK_PERI_MSDC20_1, "msdc_20_1_ck", "msdc_30_0_sel", 13),
507 + GATE_PERI0(CLK_PERI_MSDC20_2, "msdc_20_2_ck", "msdc_30_1_sel", 14),
508 + GATE_PERI0(CLK_PERI_MSDC30_1, "msdc_30_1_ck", "msdc_30_2_sel", 15),
509 + GATE_PERI0(CLK_PERI_NLI, "nli_ck", "axi_sel", 16),
510 + GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 17),
511 + GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 18),
512 + GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 19),
513 + GATE_PERI0(CLK_PERI_UART3, "uart3_ck", "axi_sel", 20),
514 + GATE_PERI0(CLK_PERI_BTIF, "btif_ck", "axi_sel", 21),
515 + GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 22),
516 + GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 23),
517 + GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 24),
518 + GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "axi_sel", 25),
519 + GATE_PERI0(CLK_PERI_AUXADC, "auxadc_ck", "axi_sel", 26),
520 + GATE_PERI0(CLK_PERI_SPI0, "spi0_ck", "spi0_sel", 27),
521 + GATE_PERI0(CLK_PERI_ETH, "eth_ck", "eth_sel", 28),
522 + GATE_PERI0(CLK_PERI_USB0_MCU, "usb0_mcu", "axi_sel", 29),
523 + GATE_PERI0(CLK_PERI_USB1_MCU, "usb1_mcu","axi_sel", 30),
524 + GATE_PERI0(CLK_PERI_USB_SLV, "usb_slv", "axi_sel", 31),
525 +
526 + /* PERI1 */
527 + GATE_PERI1(CLK_PERI_GCPU, "gcpu_ck", "axi_sel", 0),
528 + GATE_PERI1(CLK_PERI_NFI_ECC, "nfi_ecc_ck", "axi_sel", 1),
529 + GATE_PERI1(CLK_PERI_NFI_PAD, "nfi_pad_ck", "axi_sel", 2),
530 +};
531 +
532 +static const char * const uart_ck_sel_parents[] __initconst = {
533 + "clk26m",
534 + "uart_sel",
535 +};
536 +
537 +static const struct mtk_composite peri_clks[] __initconst = {
538 + MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1),
539 + MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1),
540 + MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1),
541 + MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),
542 +};
543 +
544 +static void __init mtk_topckgen_init(struct device_node *node)
545 +{
546 + struct clk_onecell_data *clk_data;
547 + void __iomem *base;
548 + int r;
549 +
550 + base = of_iomap(node, 0);
551 + if (!base) {
552 + pr_err("%s(): ioremap failed\n", __func__);
553 + return;
554 + }
555 +
556 + mt7623_top_clk_data = clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
557 +
558 + mtk_clk_register_factors(root_clk_alias, ARRAY_SIZE(root_clk_alias), clk_data);
559 + mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
560 + mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
561 + &mt7623_clk_lock, clk_data);
562 +
563 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
564 + if (r)
565 + pr_err("%s(): could not register clock provider: %d\n",
566 + __func__, r);
567 +
568 + mtk_clk_enable_critical();
569 +}
570 +CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt7623-topckgen", mtk_topckgen_init);
571 +
572 +static void __init mtk_infrasys_init(struct device_node *node)
573 +{
574 + struct clk_onecell_data *clk_data;
575 + int r;
576 +
577 + clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
578 +
579 + mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
580 + clk_data);
581 +
582 + clk_prepare_enable(clk_data->clks[CLK_INFRA_M4U]);
583 +
584 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
585 + if (r)
586 + pr_err("%s(): could not register clock provider: %d\n",
587 + __func__, r);
588 +
589 + mtk_register_reset_controller(node, 2, 0x30);
590 +}
591 +CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt7623-infracfg", mtk_infrasys_init);
592 +
593 +static void __init mtk_pericfg_init(struct device_node *node)
594 +{
595 + struct clk_onecell_data *clk_data;
596 + int r;
597 + void __iomem *base;
598 +
599 + base = of_iomap(node, 0);
600 + if (!base) {
601 + pr_err("%s(): ioremap failed\n", __func__);
602 + return;
603 + }
604 +
605 + clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
606 +
607 + mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates),
608 + clk_data);
609 + mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base,
610 + &mt7623_clk_lock, clk_data);
611 +
612 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
613 + if (r)
614 + pr_err("%s(): could not register clock provider: %d\n",
615 + __func__, r);
616 +
617 + mtk_register_reset_controller(node, 2, 0);
618 +}
619 +CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt7623-pericfg", mtk_pericfg_init);
620 +
621 +#define MT7623_PLL_FMAX (2000 * MHZ)
622 +#define CON0_MT7623_RST_BAR BIT(27)
623 +
624 +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \
625 + .id = _id, \
626 + .name = _name, \
627 + .reg = _reg, \
628 + .pwr_reg = _pwr_reg, \
629 + .en_mask = _en_mask, \
630 + .flags = _flags, \
631 + .rst_bar_mask = CON0_MT7623_RST_BAR, \
632 + .fmax = MT7623_PLL_FMAX, \
633 + .pcwbits = _pcwbits, \
634 + .pd_reg = _pd_reg, \
635 + .pd_shift = _pd_shift, \
636 + .tuner_reg = _tuner_reg, \
637 + .pcw_reg = _pcw_reg, \
638 + .pcw_shift = _pcw_shift, \
639 + }
640 +
641 +static const struct mtk_pll_data plls[] = {
642 + PLL(CLK_APMIXED_ARMPLL, "armpll", 0x200, 0x20c, 0x00000001, 0, 21, 0x204, 24, 0x0, 0x204, 0),
643 + PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x210, 0x21c, 0x78000001, HAVE_RST_BAR, 21, 0x214, 6, 0x0, 0x214, 0),
644 + PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x220, 0x22c, 0xFC000001, HAVE_RST_BAR, 7, 0x224, 6, 0x0, 0x224, 0),
645 + PLL(CLK_APMIXED_MMPLL, "mmpll", 0x230, 0x23c, 0x00000001, 0, 21, 0x254, 6, 0x0, 0x258, 0),
646 + PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x240, 0x24c, 0x00000001, 0, 21, 0x244, 6, 0x0, 0x244, 0),
647 + PLL(CLK_APMIXED_AUDPLL, "audpll", 0x250, 0x25c, 0x00000001, 0, 31, 0x2e8, 6, 0x2f8, 0x254, 0),
648 + PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x260, 0x26c, 0x00000001, 0, 31, 0x294, 6, 0x0, 0x298, 0),
649 + PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x270, 0x27c, 0x00000001, 0, 21, 0x2b0, 6, 0x0, 0x2b4, 0),
650 +};
651 +
652 +static void __init mtk_apmixedsys_init(struct device_node *node)
653 +{
654 + struct clk_onecell_data *clk_data;
655 +
656 + mt7623_pll_clk_data = clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
657 + if (!clk_data)
658 + return;
659 +
660 + mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
661 + mtk_clk_enable_critical();
662 +}
663 +CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt7623-apmixedsys",
664 + mtk_apmixedsys_init);
665 diff --git a/include/dt-bindings/clock/mt7623-clk.h b/include/dt-bindings/clock/mt7623-clk.h
666 new file mode 100644
667 index 0000000..cb1e8a9
668 --- /dev/null
669 +++ b/include/dt-bindings/clock/mt7623-clk.h
670 @@ -0,0 +1,173 @@
671 +/*
672 + * Copyright c 2014 MediaTek Inc.
673 + * Author: James Liao <jamesjj.liao@mediatek.com>
674 + *
675 + * This program is free software; you can redistribute it and/or modify
676 + * it under the terms of the GNU General Public License version 2 as
677 + * published by the Free Software Foundation.
678 + *
679 + * This program is distributed in the hope that it will be useful,
680 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
681 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
682 + * GNU General Public License for more details.
683 + */
684 +
685 +#ifndef _DT_BINDINGS_CLK_MT7623_H
686 +#define _DT_BINDINGS_CLK_MT7623_H
687 +
688 +/* TOPCKGEN */
689 +
690 +#define CLK_TOP_AUDPLL_24 1
691 +#define CLK_TOP_AUDPLL_D16 2
692 +#define CLK_TOP_AUDPLL_D4 3
693 +#define CLK_TOP_AUDPLL_D8 4
694 +#define CLK_TOP_CLKPH_MCK 5
695 +#define CLK_TOP_CPUM_TCK_IN 6
696 +#define CLK_TOP_DSI0_LNTC_DSICLK 7
697 +#define CLK_TOP_HDMITX_CLKDIG_CTS 8
698 +#define CLK_TOP_LVDS_ETH 9
699 +#define CLK_TOP_LVDSPLL_D2 10
700 +#define CLK_TOP_LVDSPLL_D4 11
701 +#define CLK_TOP_LVDSPLL_D8 12
702 +#define CLK_TOP_MAINPLL_230P3M 13
703 +#define CLK_TOP_MAINPLL_322P4M 14
704 +#define CLK_TOP_MAINPLL_537P3M 15
705 +#define CLK_TOP_MAINPLL_806M 16
706 +#define CLK_TOP_MEMPLL_MCK_D4 17
707 +#define CLK_TOP_MMPLL_D2 18
708 +#define CLK_TOP_MSDCPLL_D2 19
709 +#define CLK_TOP_SYSPLL1_D16 20
710 +#define CLK_TOP_SYSPLL1_D2 21
711 +#define CLK_TOP_SYSPLL1_D4 22
712 +#define CLK_TOP_SYSPLL1_D8 23
713 +#define CLK_TOP_SYSPLL2_D2 24
714 +#define CLK_TOP_SYSPLL2_D4 25
715 +#define CLK_TOP_SYSPLL2_D8 26
716 +#define CLK_TOP_SYSPLL3_D2 27
717 +#define CLK_TOP_SYSPLL3_D4 28
718 +#define CLK_TOP_SYSPLL4_D2 29
719 +#define CLK_TOP_SYSPLL4_D4 30
720 +#define CLK_TOP_SYSPLL_D3 31
721 +#define CLK_TOP_SYSPLL_D5 32
722 +#define CLK_TOP_SYSPLL_D7 33
723 +#define CLK_TOP_TVDPLL_d2 34
724 +#define CLK_TOP_TVDPLL_D4 35
725 +#define CLK_TOP_UNIVPLL_178P3M 36
726 +#define CLK_TOP_UNIVPLL1_D10 37
727 +#define CLK_TOP_UNIVPLL1_D2 38
728 +#define CLK_TOP_UNIVPLL1_D4 39
729 +#define CLK_TOP_UNIVPLL1_D6 40
730 +#define CLK_TOP_UNIVPLL1_D8 41
731 +#define CLK_TOP_UNIVPLL_249P6M 42
732 +#define CLK_TOP_UNIVPLL2_D2 43
733 +#define CLK_TOP_UNIVPLL2_D4 44
734 +#define CLK_TOP_UNIVPLL2_D6 45
735 +#define CLK_TOP_UNIVPLL2_D8 46
736 +#define CLK_TOP_UNIVPLL_416M 47
737 +#define CLK_TOP_UNIVPLL_48M 48
738 +#define CLK_TOP_UNIVPLL_624M 49
739 +#define CLK_TOP_UNIVPLL_D26 50
740 +#define CLK_TOP_UNIVPLL_D5 51
741 +#define CLK_TOP_APLL_SEL 52
742 +#define CLK_TOP_AUDIO_INTBUS_SEL 53
743 +#define CLK_TOP_AUDIO_SEL 54
744 +#define CLK_TOP_AXI_SEL 55
745 +#define CLK_TOP_CAM_SEL 56
746 +#define CLK_TOP_DDR_SEL 57
747 +#define CLK_TOP_DPI0_SEL 58
748 +#define CLK_TOP_DPI1_SEL 59
749 +#define CLK_TOP_DPILVDS_SEL 60
750 +#define CLK_TOP_ETH_SEL 61
751 +#define CLK_TOP_MEM_SEL 62
752 +#define CLK_TOP_MFG_SEL 63
753 +#define CLK_TOP_MM_SEL 64
754 +#define CLK_TOP_MSDC30_0_SEL 65
755 +#define CLK_TOP_MSDC30_1_SEL 66
756 +#define CLK_TOP_MSDC30_2_SEL 67
757 +#define CLK_TOP_NFI2X_SEL 68
758 +#define CLK_TOP_PMICSPI_SEL 69
759 +#define CLK_TOP_PWM_SEL 70
760 +#define CLK_TOP_RTC_SEL 71
761 +#define CLK_TOP_SCP_SEL 72
762 +#define CLK_TOP_SPI_SEL 73
763 +#define CLK_TOP_TVE_SEL 74
764 +#define CLK_TOP_UART_SEL 75
765 +#define CLK_TOP_USB20_SEL 76
766 +#define CLK_TOP_VDEC_SEL 77
767 +#define CLK_TOP_NR_CLK 78
768 +
769 +/* APMIXED_SYS */
770 +
771 +#define CLK_APMIXED_ARMPLL 1
772 +#define CLK_APMIXED_MAINPLL 2
773 +#define CLK_APMIXED_MSDCPLL 3
774 +#define CLK_APMIXED_UNIVPLL 4
775 +#define CLK_APMIXED_MMPLL 5
776 +#define CLK_APMIXED_VENCPLL 6
777 +#define CLK_APMIXED_TVDPLL 7
778 +#define CLK_APMIXED_LVDSPLL 8
779 +#define CLK_APMIXED_AUDPLL 9
780 +
781 +/* INFRA_SYS */
782 +
783 +#define CLK_INFRA_DBGCLK 0
784 +#define CLK_INFRA_SMI 1
785 +#define CLK_INFRA_AUDIO 5
786 +#define CLK_INFRA_EFUSE 6
787 +#define CLK_INFRA_L2C_SRAM 7
788 +#define CLK_INFRA_M4U 8
789 +#define CLK_INFRA_CONNMCU 12
790 +#define CLK_INFRA_TRNG 13
791 +#define CLK_INFRA_CPUM 15
792 +#define CLK_INFRA_KP 16
793 +#define CLK_INFRA_CEC 18
794 +#define CLK_INFRA_IRRX 19
795 +#define CLK_INFRA_PMICSPI 22
796 +#define CLK_INFRA_PMIC_WRAP 23
797 +#define CLK_INFRA_NR_CLK 24
798 +
799 +/* PERI_SYS */
800 +
801 +#define CLK_PERI_NFI 0
802 +#define CLK_PERI_THERM 1
803 +#define CLK_PERI_PWM1 2
804 +#define CLK_PERI_PWM2 3
805 +#define CLK_PERI_PWM3 4
806 +#define CLK_PERI_PWM4 5
807 +#define CLK_PERI_PWM5 6
808 +#define CLK_PERI_PWM6 7
809 +#define CLK_PERI_PWM7 8
810 +#define CLK_PERI_PWM 9
811 +#define CLK_PERI_USB0 10
812 +#define CLK_PERI_USB1 11
813 +#define CLK_PERI_AP_DMA 12
814 +#define CLK_PERI_MSDC20_1 13
815 +#define CLK_PERI_MSDC20_2 14
816 +#define CLK_PERI_MSDC30_1 15
817 +#define CLK_PERI_NLI 16
818 +#define CLK_PERI_UART0 17
819 +#define CLK_PERI_UART1 18
820 +#define CLK_PERI_UART2 19
821 +#define CLK_PERI_UART3 20
822 +#define CLK_PERI_BTIF 21
823 +#define CLK_PERI_I2C0 22
824 +#define CLK_PERI_I2C1 23
825 +#define CLK_PERI_I2C2 24
826 +#define CLK_PERI_I2C3 25
827 +#define CLK_PERI_AUXADC 26
828 +#define CLK_PERI_SPI0 27
829 +#define CLK_PERI_ETH 28
830 +#define CLK_PERI_USB0_MCU 29
831 +#define CLK_PERI_USB1_MCU 30
832 +#define CLK_PERI_USB_SLV 31
833 +#define CLK_PERI_GCPU 32
834 +#define CLK_PERI_NFI_ECC 33
835 +#define CLK_PERI_NFI_PAD 34
836 +#define CLK_PERI_UART0_SEL 35
837 +#define CLK_PERI_UART1_SEL 36
838 +#define CLK_PERI_UART2_SEL 37
839 +#define CLK_PERI_UART3_SEL 38
840 +#define CLK_PERI_NR_CLK 39
841 +
842 +#endif /* _DT_BINDINGS_CLK_MT7623_H */
843 +
844 --
845 1.7.10.4
846
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