7263bb21816b36733b561b749de589d4b010d718
[openwrt/openwrt.git] / target / linux / mediatek / patches / 0063-arm-mediatek-add-SDK-ethernet.patch
1 From e3aece79d5003b6879298b05551e113117d5cdd8 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sat, 27 Jun 2015 13:13:36 +0200
4 Subject: [PATCH 63/76] arm: mediatek: add SDK ethernet
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 drivers/net/ethernet/Kconfig | 1 +
9 drivers/net/ethernet/Makefile | 1 +
10 drivers/net/ethernet/raeth/Kconfig | 415 ++
11 drivers/net/ethernet/raeth/Makefile | 67 +
12 drivers/net/ethernet/raeth/Makefile.release | 60 +
13 drivers/net/ethernet/raeth/csr_netlink.h | 27 +
14 drivers/net/ethernet/raeth/dvt/pkt_gen.c | 88 +
15 drivers/net/ethernet/raeth/dvt/pkt_gen_tcp_frag.c | 138 +
16 drivers/net/ethernet/raeth/dvt/pkt_gen_udp_frag.c | 191 +
17 drivers/net/ethernet/raeth/dvt/raether_pdma_dvt.c | 1527 +++++
18 drivers/net/ethernet/raeth/dvt/raether_pdma_dvt.h | 75 +
19 drivers/net/ethernet/raeth/ethtool_readme.txt | 44 +
20 drivers/net/ethernet/raeth/mcast.c | 187 +
21 drivers/net/ethernet/raeth/mii_mgr.c | 603 ++
22 drivers/net/ethernet/raeth/ra2882ethreg.h | 1985 +++++++
23 drivers/net/ethernet/raeth/ra_ethtool.c | 515 ++
24 drivers/net/ethernet/raeth/ra_ethtool.h | 13 +
25 drivers/net/ethernet/raeth/ra_ioctl.h | 102 +
26 drivers/net/ethernet/raeth/ra_mac.c | 2645 +++++++++
27 drivers/net/ethernet/raeth/ra_mac.h | 57 +
28 drivers/net/ethernet/raeth/ra_netlink.c | 142 +
29 drivers/net/ethernet/raeth/ra_netlink.h | 10 +
30 drivers/net/ethernet/raeth/ra_qos.c | 655 +++
31 drivers/net/ethernet/raeth/ra_qos.h | 18 +
32 drivers/net/ethernet/raeth/ra_rfrw.c | 66 +
33 drivers/net/ethernet/raeth/ra_rfrw.h | 6 +
34 drivers/net/ethernet/raeth/raether.c | 6401 +++++++++++++++++++++
35 drivers/net/ethernet/raeth/raether.h | 126 +
36 drivers/net/ethernet/raeth/raether_hwlro.c | 347 ++
37 drivers/net/ethernet/raeth/raether_pdma.c | 1121 ++++
38 drivers/net/ethernet/raeth/raether_qdma.c | 1407 +++++
39 drivers/net/ethernet/raeth/raether_qdma_mt7623.c | 1020 ++++
40 drivers/net/ethernet/raeth/smb_hook.c | 17 +
41 drivers/net/ethernet/raeth/smb_nf.c | 177 +
42 drivers/net/ethernet/raeth/sync_write.h | 103 +
43 35 files changed, 20357 insertions(+)
44 create mode 100644 drivers/net/ethernet/raeth/Kconfig
45 create mode 100644 drivers/net/ethernet/raeth/Makefile
46 create mode 100644 drivers/net/ethernet/raeth/Makefile.release
47 create mode 100644 drivers/net/ethernet/raeth/csr_netlink.h
48 create mode 100755 drivers/net/ethernet/raeth/dvt/pkt_gen.c
49 create mode 100755 drivers/net/ethernet/raeth/dvt/pkt_gen_tcp_frag.c
50 create mode 100755 drivers/net/ethernet/raeth/dvt/pkt_gen_udp_frag.c
51 create mode 100755 drivers/net/ethernet/raeth/dvt/raether_pdma_dvt.c
52 create mode 100755 drivers/net/ethernet/raeth/dvt/raether_pdma_dvt.h
53 create mode 100644 drivers/net/ethernet/raeth/ethtool_readme.txt
54 create mode 100644 drivers/net/ethernet/raeth/mcast.c
55 create mode 100644 drivers/net/ethernet/raeth/mii_mgr.c
56 create mode 100644 drivers/net/ethernet/raeth/ra2882ethreg.h
57 create mode 100644 drivers/net/ethernet/raeth/ra_ethtool.c
58 create mode 100644 drivers/net/ethernet/raeth/ra_ethtool.h
59 create mode 100644 drivers/net/ethernet/raeth/ra_ioctl.h
60 create mode 100644 drivers/net/ethernet/raeth/ra_mac.c
61 create mode 100644 drivers/net/ethernet/raeth/ra_mac.h
62 create mode 100644 drivers/net/ethernet/raeth/ra_netlink.c
63 create mode 100644 drivers/net/ethernet/raeth/ra_netlink.h
64 create mode 100644 drivers/net/ethernet/raeth/ra_qos.c
65 create mode 100644 drivers/net/ethernet/raeth/ra_qos.h
66 create mode 100644 drivers/net/ethernet/raeth/ra_rfrw.c
67 create mode 100644 drivers/net/ethernet/raeth/ra_rfrw.h
68 create mode 100644 drivers/net/ethernet/raeth/raether.c
69 create mode 100644 drivers/net/ethernet/raeth/raether.h
70 create mode 100755 drivers/net/ethernet/raeth/raether_hwlro.c
71 create mode 100755 drivers/net/ethernet/raeth/raether_pdma.c
72 create mode 100644 drivers/net/ethernet/raeth/raether_qdma.c
73 create mode 100644 drivers/net/ethernet/raeth/raether_qdma_mt7623.c
74 create mode 100644 drivers/net/ethernet/raeth/smb_hook.c
75 create mode 100644 drivers/net/ethernet/raeth/smb_nf.c
76 create mode 100644 drivers/net/ethernet/raeth/sync_write.h
77
78 diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig
79 index eadcb05..627e1d4 100644
80 --- a/drivers/net/ethernet/Kconfig
81 +++ b/drivers/net/ethernet/Kconfig
82 @@ -17,6 +17,7 @@ config MDIO
83 config SUNGEM_PHY
84 tristate
85
86 +source "drivers/net/ethernet/raeth/Kconfig"
87 source "drivers/net/ethernet/3com/Kconfig"
88 source "drivers/net/ethernet/adaptec/Kconfig"
89 source "drivers/net/ethernet/aeroflex/Kconfig"
90 diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile
91 index 1367afc..abdd636 100644
92 --- a/drivers/net/ethernet/Makefile
93 +++ b/drivers/net/ethernet/Makefile
94 @@ -84,3 +84,4 @@ obj-$(CONFIG_NET_VENDOR_VIA) += via/
95 obj-$(CONFIG_NET_VENDOR_WIZNET) += wiznet/
96 obj-$(CONFIG_NET_VENDOR_XILINX) += xilinx/
97 obj-$(CONFIG_NET_VENDOR_XIRCOM) += xircom/
98 +obj-$(CONFIG_RAETH) += raeth/
99 diff --git a/drivers/net/ethernet/raeth/Kconfig b/drivers/net/ethernet/raeth/Kconfig
100 new file mode 100644
101 index 0000000..c252c85
102 --- /dev/null
103 +++ b/drivers/net/ethernet/raeth/Kconfig
104 @@ -0,0 +1,415 @@
105 +config ARCH_MT7623
106 + bool
107 + default y
108 +
109 +config RA_NAT_NONE
110 + bool
111 + default y
112 +
113 +config RAETH
114 + tristate "Ralink GMAC"
115 + ---help---
116 + This driver supports Ralink gigabit ethernet family of
117 + adapters.
118 +
119 +config PDMA_NEW
120 + bool
121 + default y if (RALINK_MT7620 || RALINK_MT7621 || ARCH_MT7623)
122 + depends on RAETH
123 +
124 +config RAETH_SCATTER_GATHER_RX_DMA
125 + bool
126 + default y if (RALINK_MT7620 || RALINK_MT7621 || ARCH_MT7623)
127 + depends on RAETH
128 +
129 +
130 +choice
131 + prompt "Network BottomHalves"
132 + depends on RAETH
133 + default RA_NETWORK_WORKQUEUE_BH
134 +
135 + config RA_NETWORK_TASKLET_BH
136 + bool "Tasklet"
137 +
138 + config RA_NETWORK_WORKQUEUE_BH
139 + bool "Work Queue"
140 +
141 + config RAETH_NAPI
142 + bool "NAPI"
143 +
144 +endchoice
145 +
146 +#config TASKLET_WORKQUEUE_SW
147 +# bool "Tasklet and Workqueue switch"
148 +# depends on RA_NETWORK_TASKLET_BH
149 +
150 +config RAETH_SKB_RECYCLE_2K
151 + bool "SKB Recycling"
152 + depends on RAETH
153 +
154 +config RAETH_SPECIAL_TAG
155 + bool "Ralink Special Tag (0x810x)"
156 + depends on RAETH && RT_3052_ESW
157 +
158 +#config RAETH_JUMBOFRAME
159 +# bool "Jumbo Frame up to 4K bytes"
160 +# depends on RAETH && !(RALINK_RT3052 || RALINK_RT3352 || RALINK_RT5350 || RALINK_MT7628)
161 +
162 +config RAETH_CHECKSUM_OFFLOAD
163 + bool "TCP/UDP/IP checksum offload"
164 + default y
165 + depends on RAETH && !RALINK_RT2880
166 +
167 +#config RAETH_SW_FC
168 +# bool "When TX ring is full, inform kernel stop transmit and stop RX handler"
169 +# default n
170 +# depends on RAETH
171 +
172 +#config RAETH_8023AZ_EEE
173 +# bool "Enable Embeded Switch EEE"
174 +# default n
175 +# depends on RAETH && (RALINK_MT7620 || RALINK_MT7621 || RALINK_MT7628)
176 +
177 +
178 +
179 +config 32B_DESC
180 + bool "32bytes TX/RX description"
181 + default n
182 + depends on RAETH && (RALINK_MT7620 || RALINK_MT7621)
183 + ---help---
184 + At this moment, you cannot enable 32B description with Multiple RX ring at the same time.
185 +
186 +config RAETH_LRO
187 + bool "LRO (Large Receive Offload )"
188 + select INET_LRO
189 + depends on RAETH && (RALINK_RT6855A || RALINK_MT7620 || RALINK_MT7621 || ARCH_MT7623)
190 +
191 +config RAETH_HW_LRO
192 + bool "HW LRO (Large Receive Offload)"
193 + default n
194 + depends on RAETH
195 +
196 +config RAETH_HW_LRO_DBG
197 + bool "HW LRO Debug"
198 + default n
199 + depends on RAETH_HW_LRO
200 +
201 +config RAETH_HW_LRO_AUTO_ADJ_DBG
202 + bool "HW LRO Auto Adjustment Debug"
203 + default y
204 + depends on RAETH_HW_LRO
205 +
206 +config RAETH_HW_LRO_REASON_DBG
207 + bool "HW LRO Flush Reason Debug"
208 + default n
209 + depends on RAETH_HW_LRO
210 +
211 +config RAETH_HW_VLAN_TX
212 + bool "Transmit VLAN HW (DoubleVLAN is not supported)"
213 + depends on RAETH && !(RALINK_RT5350 || RALINK_MT7628)
214 + ---help---
215 + Please disable HW_VLAN_TX if you need double vlan
216 +
217 +config RAETH_HW_VLAN_RX
218 + bool "Receive VLAN HW (DoubleVLAN is not supported)"
219 + depends on RAETH && RALINK_MT7621
220 + ---help---
221 + Please disable HW_VLAN_RX if you need double vlan
222 +
223 +config RAETH_TSO
224 + bool "TSOV4 (Tcp Segmentaton Offload)"
225 + depends on (RAETH_HW_VLAN_TX && (RALINK_RT6855 || RALINK_RT6855A || RALINK_MT7620))||((RALINK_MT7621 || ARCH_MT7623) &&(RAETH_HW_VLAN_TX || RAETH_GMAC2 ))
226 +
227 +config RAETH_TSOV6
228 + bool "TSOV6 (Tcp Segmentaton Offload)"
229 + depends on RAETH_TSO
230 +
231 +config RAETH_RW_PDMAPTR_FROM_VAR
232 + bool
233 + default y if RALINK_RT6855A || RALINK_MT7620
234 + depends on RAETH
235 +
236 +config MTK_SMB_HOOK
237 + bool "Samba Speedup Module"
238 + depends on RAETH
239 +
240 +config SPLICE_NET_SUPPORT
241 + default y if MTK_SMB_HOOK
242 + depends on MTK_SMB_HOOK
243 + bool
244 +
245 +
246 +config RAETH_DVT
247 + bool "RAETH DVT"
248 + depends on RAETH && (RALINK_MT7621 || ARCH_MT7623)
249 +
250 +config RAETH_PDMA_DVT
251 + bool "PDMA DVT"
252 + depends on RAETH_DVT
253 +
254 +config RAETH_PDMA_LEGACY_MODE
255 + bool "PDMA legacy mode"
256 + depends on RAETH_PDMA_DVT
257 +
258 +#config RAETH_QOS
259 +# bool "QoS Feature"
260 +# depends on RAETH && !RALINK_RT2880 && !RALINK_MT7620 && !RALINK_MT7621 && !RAETH_TSO
261 +
262 +choice
263 + prompt "QoS Type"
264 + depends on RAETH_QOS
265 + default DSCP_QOS_DSCP
266 +
267 +config RAETH_QOS_DSCP_BASED
268 + bool "DSCP-based"
269 + depends on RAETH_QOS
270 +
271 +config RAETH_QOS_VPRI_BASED
272 + bool "VPRI-based"
273 + depends on RAETH_QOS
274 +
275 +endchoice
276 +
277 +config RAETH_QDMA
278 + bool "Choose QDMA instead PDMA"
279 + default n
280 + depends on RAETH && (RALINK_MT7621 || ARCH_MT7623)
281 +
282 +config RAETH_QDMATX_QDMARX
283 + bool "Choose QDMA RX instead PDMA RX"
284 + default n
285 + depends on RAETH_QDMA && !RALINK_MT7621
286 +
287 +
288 +
289 +choice
290 + prompt "GMAC is connected to"
291 + depends on RAETH
292 + default GE1_RGMII_FORCE_1000
293 +
294 +config GE1_MII_FORCE_100
295 + bool "MII_FORCE_100 (10/100M Switch)"
296 + depends on (RALINK_RT2880 || RALINK_RT3883 || RALINK_MT7621)
297 +
298 +config GE1_MII_AN
299 + bool "MII_AN (100Phy)"
300 + depends on (RALINK_RT2880 || RALINK_RT3883 || RALINK_MT7621)
301 +
302 +config GE1_RVMII_FORCE_100
303 + bool "RvMII_FORCE_100 (CPU)"
304 + depends on (RALINK_RT2880 || RALINK_RT3883 || RALINK_MT7621)
305 +
306 +config GE1_RGMII_FORCE_1000
307 + bool "RGMII_FORCE_1000 (GigaSW, CPU)"
308 + depends on (RALINK_RT2880 || RALINK_RT3883)
309 + select RALINK_SPI
310 +
311 +config GE1_RGMII_FORCE_1000
312 + bool "RGMII_FORCE_1000 (GigaSW, CPU)"
313 + depends on (RALINK_MT7621 || ARCH_MT7623)
314 + select RT_3052_ESW
315 +
316 +config GE1_TRGMII_FORCE_1200
317 + bool "TRGMII_FORCE_1200 (GigaSW, CPU)"
318 + depends on (RALINK_MT7621)
319 + select RT_3052_ESW
320 +
321 +config GE1_TRGMII_FORCE_2000
322 + bool "TRGMII_FORCE_2000 (GigaSW, CPU, for MT7623 and MT7683)"
323 + depends on (ARCH_MT7623)
324 + select RT_3052_ESW
325 +
326 +config GE1_TRGMII_FORCE_2600
327 + bool "TRGMII_FORCE_2600 (GigaSW, CPU, MT7623 only)"
328 + depends on (ARCH_MT7623)
329 + select RT_3052_ESW
330 +
331 +config GE1_RGMII_AN
332 + bool "RGMII_AN (GigaPhy)"
333 + depends on (RALINK_RT2880 || RALINK_RT3883 || RALINK_MT7621 || ARCH_MT7623)
334 +
335 +config GE1_RGMII_NONE
336 + bool "NONE (NO CONNECT)"
337 + depends on (RALINK_MT7621 || ARCH_MT7623)
338 +
339 +endchoice
340 +
341 +config HW_SFQ
342 + bool "HW_SFQ"
343 + default n
344 + depends on RAETH_QDMA && (ARCH_MT7623)
345 +
346 +
347 +config RT_3052_ESW
348 + bool "Ralink Embedded Switch"
349 + default y
350 + depends on RAETH && (RALINK_RT3052 || RALINK_RT3352 || RALINK_RT5350 || RALINK_RT6855 || RALINK_RT6855A || RALINK_MT7620 || RALINK_MT7621 || RALINK_MT7628 || ARCH_MT7623)
351 +
352 +config LAN_WAN_SUPPORT
353 + bool "LAN/WAN Partition"
354 + depends on RAETH && (RAETH_ROUTER || RT_3052_ESW)
355 +
356 +config ETH_MEMORY_OPTIMIZATION
357 + bool "Ethernet memory optimization"
358 + depends on RALINK_MT7628
359 +
360 +config ETH_ONE_PORT_ONLY
361 + bool "One Port Only"
362 + depends on RALINK_MT7628
363 +
364 +choice
365 + prompt "Switch Board Layout Type"
366 + depends on LAN_WAN_SUPPORT || P5_RGMII_TO_MAC_MODE || GE1_RGMII_FORCE_1000 || GE1_TRGMII_FORCE_1200 || GE2_RGMII_FORCE_1000
367 + default WAN_AT_P0
368 +
369 + config WAN_AT_P4
370 + bool "LLLL/W"
371 +
372 + config WAN_AT_P0
373 + bool "W/LLLL"
374 +endchoice
375 +
376 +config RALINK_VISTA_BASIC
377 + bool 'Vista Basic Logo for IC+ 175C'
378 + depends on LAN_WAN_SUPPORT && (RALINK_RT2880 || RALINK_RT3883)
379 +
380 +config ESW_DOUBLE_VLAN_TAG
381 + bool
382 + default y if RT_3052_ESW
383 +
384 +config RAETH_HAS_PORT4
385 + bool "Port 4 Support"
386 + depends on RAETH && RALINK_MT7620
387 +choice
388 + prompt "Target Mode"
389 + depends on RAETH_HAS_PORT4
390 + default P4_RGMII_TO_MAC_MODE
391 +
392 + config P4_MAC_TO_PHY_MODE
393 + bool "Giga_Phy (RGMII)"
394 + config GE_RGMII_MT7530_P0_AN
395 + bool "GE_RGMII_MT7530_P0_AN (MT7530 Internal GigaPhy)"
396 + config GE_RGMII_MT7530_P4_AN
397 + bool "GE_RGMII_MT7530_P4_AN (MT7530 Internal GigaPhy)"
398 + config P4_RGMII_TO_MAC_MODE
399 + bool "Giga_SW/iNIC (RGMII)"
400 + config P4_MII_TO_MAC_MODE
401 + bool "External_CPU (MII_RvMII)"
402 + config P4_RMII_TO_MAC_MODE
403 + bool "External_CPU (RvMII_MII)"
404 +endchoice
405 +
406 +config MAC_TO_GIGAPHY_MODE_ADDR2
407 + hex "Port4 Phy Address"
408 + default 0x4
409 + depends on P4_MAC_TO_PHY_MODE
410 +
411 +config RAETH_HAS_PORT5
412 + bool "Port 5 Support"
413 + depends on RAETH && (RALINK_RT3052 || RALINK_RT3352 || RALINK_RT6855 || RALINK_RT6855A || RALINK_MT7620)
414 +choice
415 + prompt "Target Mode"
416 + depends on RAETH_HAS_PORT5
417 + default P5_RGMII_TO_MAC_MODE
418 +
419 + config P5_MAC_TO_PHY_MODE
420 + bool "Giga_Phy (RGMII)"
421 + config P5_RGMII_TO_MAC_MODE
422 + bool "Giga_SW/iNIC (RGMII)"
423 + config P5_RGMII_TO_MT7530_MODE
424 + bool "MT7530 Giga_SW (RGMII)"
425 + depends on RALINK_MT7620
426 + config P5_MII_TO_MAC_MODE
427 + bool "External_CPU (MII_RvMII)"
428 + config P5_RMII_TO_MAC_MODE
429 + bool "External_CPU (RvMII_MII)"
430 +endchoice
431 +
432 +config MAC_TO_GIGAPHY_MODE_ADDR
433 + hex "GE1 Phy Address"
434 + default 0x1F
435 + depends on GE1_MII_AN || GE1_RGMII_AN
436 +
437 +config MAC_TO_GIGAPHY_MODE_ADDR
438 + hex "Port5 Phy Address"
439 + default 0x5
440 + depends on P5_MAC_TO_PHY_MODE
441 +
442 +config RAETH_GMAC2
443 + bool "GMAC2 Support"
444 + depends on RAETH && (RALINK_RT3883 || RALINK_MT7621 || ARCH_MT7623)
445 +
446 +choice
447 + prompt "GMAC2 is connected to"
448 + depends on RAETH_GMAC2
449 + default GE2_RGMII_AN
450 +
451 +config GE2_MII_FORCE_100
452 + bool "MII_FORCE_100 (10/100M Switch)"
453 + depends on RAETH_GMAC2
454 +
455 +config GE2_MII_AN
456 + bool "MII_AN (100Phy)"
457 + depends on RAETH_GMAC2
458 +
459 +config GE2_RVMII_FORCE_100
460 + bool "RvMII_FORCE_100 (CPU)"
461 + depends on RAETH_GMAC2
462 +
463 +config GE2_RGMII_FORCE_1000
464 + bool "RGMII_FORCE_1000 (GigaSW, CPU)"
465 + depends on RAETH_GMAC2
466 + select RALINK_SPI
467 +
468 +config GE2_RGMII_AN
469 + bool "RGMII_AN (External GigaPhy)"
470 + depends on RAETH_GMAC2
471 +
472 +config GE2_INTERNAL_GPHY
473 + bool "RGMII_AN (Internal GigaPny)"
474 + depends on RAETH_GMAC2
475 + select LAN_WAN_SUPPORT
476 +
477 +endchoice
478 +
479 +config GE_RGMII_INTERNAL_P0_AN
480 + bool
481 + depends on GE2_INTERNAL_GPHY
482 + default y if WAN_AT_P0
483 +
484 +config GE_RGMII_INTERNAL_P4_AN
485 + bool
486 + depends on GE2_INTERNAL_GPHY
487 + default y if WAN_AT_P4
488 +
489 +config MAC_TO_GIGAPHY_MODE_ADDR2
490 + hex
491 + default 0 if GE_RGMII_INTERNAL_P0_AN
492 + default 4 if GE_RGMII_INTERNAL_P4_AN
493 + depends on GE_RGMII_INTERNAL_P0_AN || GE_RGMII_INTERNAL_P4_AN
494 +
495 +config MAC_TO_GIGAPHY_MODE_ADDR2
496 + hex "GE2 Phy Address"
497 + default 0x1E
498 + depends on GE2_MII_AN || GE2_RGMII_AN
499 +
500 +#force 100M
501 +config RAETH_ROUTER
502 +bool
503 +default y if GE1_MII_FORCE_100 || GE2_MII_FORCE_100 || GE1_RVMII_FORCE_100 || GE2_RVMII_FORCE_100
504 +
505 +#force 1000M
506 +config MAC_TO_MAC_MODE
507 +bool
508 +default y if GE1_RGMII_FORCE_1000 || GE2_RGMII_FORCE_1000
509 +depends on (RALINK_RT2880 || RALINK_RT3883)
510 +
511 +#AN
512 +config GIGAPHY
513 +bool
514 +default y if GE1_RGMII_AN || GE2_RGMII_AN
515 +
516 +#AN
517 +config 100PHY
518 +bool
519 +default y if GE1_MII_AN || GE2_MII_AN
520 diff --git a/drivers/net/ethernet/raeth/Makefile b/drivers/net/ethernet/raeth/Makefile
521 new file mode 100644
522 index 0000000..563af05
523 --- /dev/null
524 +++ b/drivers/net/ethernet/raeth/Makefile
525 @@ -0,0 +1,67 @@
526 +obj-$(CONFIG_RAETH) += raeth.o
527 +raeth-objs := ra_mac.o mii_mgr.o ra_rfrw.o
528 +
529 +ifeq ($(CONFIG_MTK_SMB_HOOK),y)
530 +obj-y += smb_hook.o
531 +obj-m += smb.o
532 +smb-objs := smb_nf.o
533 +endif
534 +
535 +#EXTRA_CFLAGS += -DCONFIG_RAETH_MULTIPLE_RX_RING
536 +
537 +ifeq ($(CONFIG_RAETH_QOS),y)
538 +raeth-objs += ra_qos.o
539 +endif
540 +
541 +ifeq ($(CONFIG_RAETH_QDMA),y)
542 +raeth-objs += raether_qdma.o
543 +endif
544 +
545 +ifneq ($(CONFIG_RAETH_QDMA),y)
546 +raeth-objs += raether_pdma.o
547 +endif
548 +
549 +raeth-objs += raether.o
550 +
551 +ifeq ($(CONFIG_ETHTOOL),y)
552 +raeth-objs += ra_ethtool.o
553 +endif
554 +
555 +ifeq ($(CONFIG_RALINK_RT3052_MP2),y)
556 +raeth-objs += mcast.o
557 +endif
558 +
559 +ifeq ($(CONFIG_RAETH_NETLINK),y)
560 +raeth-objs += ra_netlink.o
561 +endif
562 +
563 +ifeq ($(CONFIG_RAETH_PDMA_DVT),y)
564 +raeth-objs += dvt/raether_pdma_dvt.o
565 +obj-m += dvt/pkt_gen.o
566 +obj-m += dvt/pkt_gen_udp_frag.o
567 +obj-m += dvt/pkt_gen_tcp_frag.o
568 +endif
569 +
570 +ifeq ($(CONFIG_RAETH_HW_LRO),y)
571 +raeth-objs += raether_hwlro.o
572 +endif
573 +
574 +ifeq ($(CONFIG_RAETH_GMAC2),y)
575 +EXTRA_CFLAGS += -DCONFIG_PSEUDO_SUPPORT
576 +endif
577 +
578 +ifeq ($(CONFIG_ETH_MEMORY_OPTIMIZATION),y)
579 +EXTRA_CFLAGS += -DMEMORY_OPTIMIZATION
580 +endif
581 +
582 +ifeq ($(CONFIG_RT2860V2_AP_MEMORY_OPTIMIZATION),y)
583 +EXTRA_CFLAGS += -DMEMORY_OPTIMIZATION
584 +endif
585 +
586 +ifeq ($(CONFIG_RA_NETWORK_WORKQUEUE_BH),y)
587 +EXTRA_CFLAGS += -DWORKQUEUE_BH
588 +endif
589 +
590 +ifeq ($(CONFIG_TASKLET_WORKQUEUE_SW),y)
591 +EXTRA_CFLAGS += -DTASKLET_WORKQUEUE_SW
592 +endif
593 diff --git a/drivers/net/ethernet/raeth/Makefile.release b/drivers/net/ethernet/raeth/Makefile.release
594 new file mode 100644
595 index 0000000..ecdeeda
596 --- /dev/null
597 +++ b/drivers/net/ethernet/raeth/Makefile.release
598 @@ -0,0 +1,60 @@
599 +obj-$(CONFIG_RAETH) += raeth.o
600 +raeth-objs := ra_mac.o mii_mgr.o ra_rfrw.o
601 +
602 +ifeq ($(CONFIG_MTK_SMB_HOOK),y)
603 +obj-y += smb_hook.o
604 +obj-m += smb.o
605 +smb-objs := smb_nf.o
606 +endif
607 +
608 +#EXTRA_CFLAGS += -DCONFIG_RAETH_MULTIPLE_RX_RING
609 +
610 +ifeq ($(CONFIG_RAETH_QOS),y)
611 +raeth-objs += ra_qos.o
612 +endif
613 +
614 +ifeq ($(CONFIG_RAETH_QDMA),y)
615 +raeth-objs += raether_qdma.o
616 +endif
617 +
618 +ifneq ($(CONFIG_RAETH_QDMA),y)
619 +raeth-objs += raether_pdma.o
620 +endif
621 +
622 +raeth-objs += raether.o
623 +
624 +ifeq ($(CONFIG_ETHTOOL),y)
625 +raeth-objs += ra_ethtool.o
626 +endif
627 +
628 +ifeq ($(CONFIG_RALINK_RT3052_MP2),y)
629 +raeth-objs += mcast.o
630 +endif
631 +
632 +ifeq ($(CONFIG_RAETH_NETLINK),y)
633 +raeth-objs += ra_netlink.o
634 +endif
635 +
636 +ifeq ($(CONFIG_RAETH_HW_LRO),y)
637 +raeth-objs += raether_hwlro.o
638 +endif
639 +
640 +ifeq ($(CONFIG_RAETH_GMAC2),y)
641 +EXTRA_CFLAGS += -DCONFIG_PSEUDO_SUPPORT
642 +endif
643 +
644 +ifeq ($(CONFIG_ETH_MEMORY_OPTIMIZATION),y)
645 +EXTRA_CFLAGS += -DMEMORY_OPTIMIZATION
646 +endif
647 +
648 +ifeq ($(CONFIG_RT2860V2_AP_MEMORY_OPTIMIZATION),y)
649 +EXTRA_CFLAGS += -DMEMORY_OPTIMIZATION
650 +endif
651 +
652 +ifeq ($(CONFIG_RA_NETWORK_WORKQUEUE_BH),y)
653 +EXTRA_CFLAGS += -DWORKQUEUE_BH
654 +endif
655 +
656 +ifeq ($(CONFIG_TASKLET_WORKQUEUE_SW),y)
657 +EXTRA_CFLAGS += -DTASKLET_WORKQUEUE_SW
658 +endif
659 diff --git a/drivers/net/ethernet/raeth/csr_netlink.h b/drivers/net/ethernet/raeth/csr_netlink.h
660 new file mode 100644
661 index 0000000..add7745
662 --- /dev/null
663 +++ b/drivers/net/ethernet/raeth/csr_netlink.h
664 @@ -0,0 +1,27 @@
665 +#ifndef CSR_NETLINK_H
666 +#define CSR_NETLINK_H
667 +
668 +#define CSR_NETLINK 30
669 +#define CSR_READ 0
670 +#define CSR_WRITE 1
671 +#define CSR_TEST 2
672 +
673 +#define RALINK_CSR_GROUP 2882
674 +
675 +typedef struct rt2880_csr_msg {
676 + int enable;
677 + char reg_name[32];
678 + unsigned long address;
679 + unsigned long default_value;
680 + unsigned long reserved_bits; /* 1 : not reserved, 0 : reserved */
681 + unsigned long write_mask;
682 + unsigned long write_value;
683 + int status;
684 +} CSR_MSG;
685 +
686 +int csr_msg_send(CSR_MSG* msg);
687 +int csr_msg_recv(void);
688 +
689 +// static CSR_MSG input_csr_msg;
690 +
691 +#endif
692 diff --git a/drivers/net/ethernet/raeth/dvt/pkt_gen.c b/drivers/net/ethernet/raeth/dvt/pkt_gen.c
693 new file mode 100755
694 index 0000000..b351b21
695 --- /dev/null
696 +++ b/drivers/net/ethernet/raeth/dvt/pkt_gen.c
697 @@ -0,0 +1,88 @@
698 +//#include <linux/config.h>
699 +#include <linux/version.h>
700 +#include <linux/module.h>
701 +#include <linux/skbuff.h>
702 +#include <linux/kernel.h>
703 +#include <linux/init.h>
704 +#include <linux/netfilter.h>
705 +#include <linux/netdevice.h>
706 +#include <linux/types.h>
707 +#include <asm/uaccess.h>
708 +#include <linux/moduleparam.h>
709 +
710 +char *ifname="eth3";
711 +
712 +static int32_t PktGenInitMod(void)
713 +{
714 +
715 + struct net_dev *dev;
716 + struct sk_buff *skb;
717 + int i=0;
718 +
719 + unsigned char pkt[]={
720 + //0xff, 0xff, 0xff, 0xff, 0xff, 0xff, // dest bcast mac
721 + 0x00, 0x21, 0x86, 0xee, 0xe3, 0x95, // dest macA
722 + //0x00, 0x30, 0xdb, 0x02, 0x02, 0x01, // dest macB
723 + 0x00, 0x0c, 0x43, 0x28, 0x80, 0x33, // src mac
724 + 0x81, 0x00, // vlan tag
725 + //0x81, 0x10, // vlan tag
726 + //0x87, 0x39, // do not learn
727 + //0xc1, 0x03, // vlan tag SA=0, VID=2, LV=1
728 + 0x00, 0x03, // pri=0, vlan=3
729 + 0x08, 0x00, // eth type=ip
730 + 0x45, 0x00, 0x00, 0x30, 0x12, 0x34, 0x40, 0x00, 0xff, 0x06,
731 + 0x40, 0x74, 0x0a, 0x0a, 0x1e, 0x0a, 0x0a, 0x0a, 0x1e, 0x0b,
732 + 0x00, 0x1e, 0x00, 0x28, 0x00, 0x1c, 0x81, 0x06, 0x00, 0x00,
733 + 0x00, 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
734 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
735 +
736 + skb = alloc_skb(256, GFP_ATOMIC);
737 +
738 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
739 + if((dev=dev_get_by_name(&init_net,ifname))){
740 +#else
741 + if((dev=dev_get_by_name(ifname))){
742 +#endif
743 +
744 +
745 +
746 + skb->dev=dev;
747 + skb_put(skb,sizeof(pkt));
748 + memcpy(skb->data, pkt, sizeof(pkt));
749 +
750 + printk("send pkt(len=%d) to %s\n", skb->len, skb->dev->name);
751 +
752 +
753 + for(i=0;i<sizeof(pkt);i++){
754 + if(i%16==0) {
755 + printk("\n");
756 + }
757 + printk("%02X-",skb->data[i]);
758 + }
759 +
760 + dev_queue_xmit(skb);
761 + }else{
762 + printk("interface %s not found\n",ifname);
763 + return 1;
764 + }
765 +
766 + return 0;
767 +}
768 +
769 +static void PktGenCleanupMod(void)
770 +{
771 +}
772 +
773 +module_init(PktGenInitMod);
774 +module_exit(PktGenCleanupMod);
775 +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,12)
776 +MODULE_PARM (ifname, "s");
777 +#else
778 +module_param (ifname, charp, 0);
779 +#endif
780 +
781 +MODULE_DESCRIPTION("Ralink PktGen Module");
782 +MODULE_AUTHOR("Steven Liu");
783 +MODULE_LICENSE("Proprietary");
784 +MODULE_PARM_DESC (ifname, "interface name");
785 +
786 diff --git a/drivers/net/ethernet/raeth/dvt/pkt_gen_tcp_frag.c b/drivers/net/ethernet/raeth/dvt/pkt_gen_tcp_frag.c
787 new file mode 100755
788 index 0000000..e78c65a
789 --- /dev/null
790 +++ b/drivers/net/ethernet/raeth/dvt/pkt_gen_tcp_frag.c
791 @@ -0,0 +1,138 @@
792 +//#include <linux/config.h>
793 +#include <linux/version.h>
794 +#include <linux/module.h>
795 +#include <linux/skbuff.h>
796 +#include <linux/kernel.h>
797 +#include <linux/init.h>
798 +#include <linux/netfilter.h>
799 +#include <linux/netdevice.h>
800 +#include <linux/types.h>
801 +#include <asm/uaccess.h>
802 +#include <linux/moduleparam.h>
803 +
804 +char *ifname="eth3";
805 +
806 +
807 +static int32_t PktGenInitMod(void)
808 +{
809 + unsigned char pkt_1[]={
810 + 0x00, 0x21, 0x86, 0xee, 0xe3, 0x90, // dest mac
811 + 0x00, 0x0c, 0x43, 0x28, 0x80, 0x33, // src mac
812 + 0x08, 0x00, // type: ip
813 + 0x45, 0x00, 0x00, 0x34, // ip: ..., total len (0x034 = 52)
814 + 0xa1, 0x78, 0x20, 0x00, // ip: id, frag, frag offset
815 + 0x80, 0x06, 0x63, 0x07, // ip: ttl, protocol, hdr checksum (0x6307)
816 + 0x0a, 0x0a, 0x1e, 0x7b, // src ip (10.10.30.123)
817 + 0x0a, 0x0a, 0x1e, 0x05, // dst ip (10.10.30.5)
818 + 0x0d, 0xd5, //tcp src port
819 + 0x13, 0x89, //tcp dst port
820 + 0x40, 0xf5, 0x15, 0x04, //tcp sequence number
821 + 0xf6, 0x4f, 0x1e, 0x31, //tcp ack number
822 + 0x50, 0x10, 0xfc, 0x00, //tcp flags, win size
823 + 0xf1, 0xfe, 0x00, 0x00, //tcp checksum (0xf1fe)
824 + 0x01, 0x02, 0x03, 0x04, 0x05, //payload (12 bytes)
825 + 0x06, 0x07, 0x08, 0x09, 0x0a,
826 + 0x0b, 0x0c
827 + };
828 +
829 + unsigned char pkt_2[]={
830 + 0x00, 0x21, 0x86, 0xee, 0xe3, 0x90, // dest mac
831 + 0x00, 0x0c, 0x43, 0x28, 0x80, 0x33, // src mac
832 + 0x08, 0x00, // type: ip
833 + 0x45, 0x00, 0x00, 0x20, // ip: ..., total len (0x020 = 32)
834 + 0xa1, 0x78, 0x00, 0x04, // ip: id, frag, frag offset (32)
835 + 0x40, 0x11, 0x63, 0x07, // ip: ttl, protocol, hdr checksum (0x6307)
836 + 0x0a, 0x0a, 0x1e, 0x7b, // src ip (10.10.30.123)
837 + 0x0a, 0x0a, 0x1e, 0x05, // dst ip (10.10.30.5)
838 + 0x11, 0x12, 0x13, 0x14, 0x15, //payload (12 bytes)
839 + 0x16, 0x17, 0x18, 0x19, 0x1a,
840 + 0x1b, 0x1c
841 + };
842 +
843 + struct net_dev *dev;
844 + struct sk_buff *skb_1;
845 + struct sk_buff *skb_2;
846 + int i=0;
847 +
848 + skb_1 = alloc_skb(256, GFP_ATOMIC);
849 + skb_2 = alloc_skb(256, GFP_ATOMIC);
850 +
851 +
852 +#if 1
853 +/* send packet 1 */
854 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
855 + if((dev=dev_get_by_name(&init_net,ifname))){
856 +#else
857 + if((dev=dev_get_by_name(ifname))){
858 +#endif
859 +
860 + skb_1->dev=dev;
861 + skb_put(skb_1,sizeof(pkt_1));
862 + memcpy(skb_1->data, pkt_1, sizeof(pkt_1));
863 +
864 + printk("send pkt(len=%d) to %s\n", skb_1->len, skb_1->dev->name);
865 +
866 +
867 + for(i=0;i<sizeof(pkt_1);i++){
868 + if(i%16==0) {
869 + printk("\n");
870 + }
871 + printk("%02X-",skb_1->data[i]);
872 + }
873 +
874 + dev_queue_xmit(skb_1);
875 + }else{
876 + printk("interface %s not found\n",ifname);
877 + return 1;
878 + }
879 +#endif
880 +
881 +#if 1
882 +/* send packet 2 */
883 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
884 + if((dev=dev_get_by_name(&init_net,ifname))){
885 +#else
886 + if((dev=dev_get_by_name(ifname))){
887 +#endif
888 +
889 + skb_2->dev=dev;
890 + skb_put(skb_2,sizeof(pkt_2));
891 + memcpy(skb_2->data, pkt_2, sizeof(pkt_2));
892 +
893 + printk("send pkt(len=%d) to %s\n", skb_2->len, skb_2->dev->name);
894 +
895 +
896 + for(i=0;i<sizeof(pkt_2);i++){
897 + if(i%16==0) {
898 + printk("\n");
899 + }
900 + printk("%02X-",skb_2->data[i]);
901 + }
902 +
903 + dev_queue_xmit(skb_2);
904 + }else{
905 + printk("interface %s not found\n",ifname);
906 + return 1;
907 + }
908 +#endif
909 +
910 + return 0;
911 +}
912 +
913 +static void PktGenCleanupMod(void)
914 +{
915 +}
916 +
917 +module_init(PktGenInitMod);
918 +module_exit(PktGenCleanupMod);
919 +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,12)
920 +MODULE_PARM (ifname, "s");
921 +#else
922 +module_param (ifname, charp, 0);
923 +#endif
924 +
925 +MODULE_DESCRIPTION("Ralink PktGen Module");
926 +MODULE_AUTHOR("Steven Liu");
927 +MODULE_LICENSE("Proprietary");
928 +MODULE_PARM_DESC (ifname, "interface name");
929 +
930 diff --git a/drivers/net/ethernet/raeth/dvt/pkt_gen_udp_frag.c b/drivers/net/ethernet/raeth/dvt/pkt_gen_udp_frag.c
931 new file mode 100755
932 index 0000000..917e7ad
933 --- /dev/null
934 +++ b/drivers/net/ethernet/raeth/dvt/pkt_gen_udp_frag.c
935 @@ -0,0 +1,191 @@
936 +//#include <linux/config.h>
937 +#include <linux/version.h>
938 +#include <linux/module.h>
939 +#include <linux/skbuff.h>
940 +#include <linux/kernel.h>
941 +#include <linux/init.h>
942 +#include <linux/netfilter.h>
943 +#include <linux/netdevice.h>
944 +#include <linux/types.h>
945 +#include <asm/uaccess.h>
946 +#include <linux/moduleparam.h>
947 +
948 +char *ifname="eth3";
949 +
950 +
951 +static int32_t PktGenInitMod(void)
952 +{
953 +#if 0
954 + unsigned char pkt_0[]={
955 +// 0x00, 0x21, 0x86, 0xee, 0xe3, 0x95, // dest mac
956 + 0x00, 0x21, 0x86, 0xee, 0xe3, 0x90, // dest mac
957 + 0x00, 0x0c, 0x43, 0x28, 0x80, 0x33, // src mac
958 + 0x08, 0x00, // type: ip
959 + 0x45, 0x00, 0x00, 0x26, // ip: ..., total len (0x026 = 38)
960 +// 0xa1, 0x78, 0x20, 0x00, // ip: id, frag, frag offset
961 + 0xa1, 0x78, 0x40, 0x00, // ip: id, frag, frag offset
962 + 0x40, 0x11, 0x63, 0x07, // ip: ttl, protocol, hdr checksum (0x6307)
963 + 0x0a, 0x0a, 0x1e, 0x7b, // src ip (10.10.30.123)
964 +// 0x0a, 0x0a, 0x1e, 0x03, // dst ip (10.10.30.3)
965 + 0x0a, 0x0a, 0x1e, 0x05, // dst ip (10.10.30.5)
966 + 0xca, 0x7b, //udp src port
967 + 0x13, 0x89, //udp dst port
968 + 0x00, 0x12, //udp len (0x01c = 18)
969 + 0x2f, 0x96, //udp checksum (0x2f96)
970 + 0x01, 0x02, 0x03, 0x04, 0x05, //payload (10 bytes)
971 + 0x06, 0x07, 0x08, 0x09, 0x0a
972 + };
973 +#endif
974 +
975 + unsigned char pkt_1[]={
976 +// 0x00, 0x21, 0x86, 0xee, 0xe3, 0x95, // dest mac
977 + 0x00, 0x21, 0x86, 0xee, 0xe3, 0x90, // dest mac
978 + 0x00, 0x0c, 0x43, 0x28, 0x80, 0x33, // src mac
979 + 0x08, 0x00, // type: ip
980 + 0x45, 0x00, 0x00, 0x24, // ip: ..., total len (0x024 = 36)
981 + 0xa1, 0x78, 0x20, 0x00, // ip: id, frag, frag offset
982 +// 0xa1, 0x78, 0x40, 0x00, // ip: id, frag, frag offset
983 + 0x40, 0x11, 0x63, 0x07, // ip: ttl, protocol, hdr checksum (0x6307)
984 + 0x0a, 0x0a, 0x1e, 0x7b, // src ip (10.10.30.123)
985 +// 0x0a, 0x0a, 0x1e, 0x03, // dst ip (10.10.30.3)
986 + 0x0a, 0x0a, 0x1e, 0x05, // dst ip (10.10.30.5)
987 + 0xca, 0x7b, //udp src port
988 + 0x13, 0x89, //udp dst port
989 + 0x00, 0x1a, //udp len (0x01a = 26)
990 + 0x2f, 0x96, //udp checksum (0x2f96)
991 + 0x01, 0x02, 0x03, 0x04, 0x05, //payload (8 bytes)
992 + 0x06, 0x07, 0x08
993 + };
994 +
995 + unsigned char pkt_2[]={
996 +// 0x00, 0x21, 0x86, 0xee, 0xe3, 0x95, // dest mac
997 + 0x00, 0x21, 0x86, 0xee, 0xe3, 0x90, // dest mac
998 + 0x00, 0x0c, 0x43, 0x28, 0x80, 0x33, // src mac
999 + 0x08, 0x00, // type: ip
1000 + 0x45, 0x00, 0x00, 0x1e, // ip: ..., total len (0x01e = 30)
1001 + 0xa1, 0x78, 0x00, 0x02, // ip: id, frag, frag offset (16)
1002 + 0x40, 0x11, 0x63, 0x07, // ip: ttl, protocol, hdr checksum (0x6307)
1003 + 0x0a, 0x0a, 0x1e, 0x7b, // src ip (10.10.30.123)
1004 +// 0x0a, 0x0a, 0x1e, 0x03, // dst ip (10.10.30.3)
1005 + 0x0a, 0x0a, 0x1e, 0x05, // dst ip (10.10.30.5)
1006 + 0x11, 0x12, 0x13, 0x14, 0x15, //payload (10 bytes)
1007 + 0x16, 0x17, 0x18, 0x19, 0x1a
1008 + };
1009 +
1010 + struct net_dev *dev;
1011 +// struct sk_buff *skb_0;
1012 + struct sk_buff *skb_1;
1013 + struct sk_buff *skb_2;
1014 + int i=0;
1015 +
1016 +// skb_0 = alloc_skb(256, GFP_ATOMIC);
1017 + skb_1 = alloc_skb(256, GFP_ATOMIC);
1018 + skb_2 = alloc_skb(256, GFP_ATOMIC);
1019 +
1020 +#if 0
1021 +/* send packet 0 */
1022 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
1023 + if((dev=dev_get_by_name(&init_net,ifname))){
1024 +#else
1025 + if((dev=dev_get_by_name(ifname))){
1026 +#endif
1027 +
1028 + skb_0->dev=dev;
1029 + skb_put(skb_0,sizeof(pkt_0));
1030 + memcpy(skb_0->data, pkt_0, sizeof(pkt_0));
1031 +
1032 + printk("send pkt(len=%d) to %s\n", skb_0->len, skb_0->dev->name);
1033 +
1034 +
1035 + for(i=0;i<sizeof(pkt_0);i++){
1036 + if(i%16==0) {
1037 + printk("\n");
1038 + }
1039 + printk("%02X-",skb_0->data[i]);
1040 + }
1041 +
1042 + dev_queue_xmit(skb_0);
1043 + }else{
1044 + printk("interface %s not found\n",ifname);
1045 + return 1;
1046 + }
1047 +#endif
1048 +
1049 +#if 1
1050 +/* send packet 1 */
1051 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
1052 + if((dev=dev_get_by_name(&init_net,ifname))){
1053 +#else
1054 + if((dev=dev_get_by_name(ifname))){
1055 +#endif
1056 +
1057 + skb_1->dev=dev;
1058 + skb_put(skb_1,sizeof(pkt_1));
1059 + memcpy(skb_1->data, pkt_1, sizeof(pkt_1));
1060 +
1061 + printk("send pkt(len=%d) to %s\n", skb_1->len, skb_1->dev->name);
1062 +
1063 +
1064 + for(i=0;i<sizeof(pkt_1);i++){
1065 + if(i%16==0) {
1066 + printk("\n");
1067 + }
1068 + printk("%02X-",skb_1->data[i]);
1069 + }
1070 +
1071 + dev_queue_xmit(skb_1);
1072 + }else{
1073 + printk("interface %s not found\n",ifname);
1074 + return 1;
1075 + }
1076 +#endif
1077 +
1078 +#if 1
1079 +/* send packet 2 */
1080 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
1081 + if((dev=dev_get_by_name(&init_net,ifname))){
1082 +#else
1083 + if((dev=dev_get_by_name(ifname))){
1084 +#endif
1085 +
1086 + skb_2->dev=dev;
1087 + skb_put(skb_2,sizeof(pkt_2));
1088 + memcpy(skb_2->data, pkt_2, sizeof(pkt_2));
1089 +
1090 + printk("send pkt(len=%d) to %s\n", skb_2->len, skb_2->dev->name);
1091 +
1092 +
1093 + for(i=0;i<sizeof(pkt_2);i++){
1094 + if(i%16==0) {
1095 + printk("\n");
1096 + }
1097 + printk("%02X-",skb_2->data[i]);
1098 + }
1099 +
1100 + dev_queue_xmit(skb_2);
1101 + }else{
1102 + printk("interface %s not found\n",ifname);
1103 + return 1;
1104 + }
1105 +#endif
1106 +
1107 + return 0;
1108 +}
1109 +
1110 +static void PktGenCleanupMod(void)
1111 +{
1112 +}
1113 +
1114 +module_init(PktGenInitMod);
1115 +module_exit(PktGenCleanupMod);
1116 +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,12)
1117 +MODULE_PARM (ifname, "s");
1118 +#else
1119 +module_param (ifname, charp, 0);
1120 +#endif
1121 +
1122 +MODULE_DESCRIPTION("Ralink PktGen Module");
1123 +MODULE_AUTHOR("Steven Liu");
1124 +MODULE_LICENSE("Proprietary");
1125 +MODULE_PARM_DESC (ifname, "interface name");
1126 +
1127 diff --git a/drivers/net/ethernet/raeth/dvt/raether_pdma_dvt.c b/drivers/net/ethernet/raeth/dvt/raether_pdma_dvt.c
1128 new file mode 100755
1129 index 0000000..971a821
1130 --- /dev/null
1131 +++ b/drivers/net/ethernet/raeth/dvt/raether_pdma_dvt.c
1132 @@ -0,0 +1,1527 @@
1133 +#include <linux/module.h>
1134 +#include <linux/version.h>
1135 +#include <linux/kernel.h>
1136 +#include <linux/types.h>
1137 +#include <linux/pci.h>
1138 +#include <linux/init.h>
1139 +#include <linux/skbuff.h>
1140 +#include <linux/if_vlan.h>
1141 +#include <linux/if_ether.h>
1142 +#include <linux/fs.h>
1143 +#include <asm/uaccess.h>
1144 +#include <asm/rt2880/surfboardint.h>
1145 +#if defined(CONFIG_RAETH_TSO)
1146 +#include <linux/tcp.h>
1147 +#include <net/ipv6.h>
1148 +#include <linux/ip.h>
1149 +#include <net/ip.h>
1150 +#include <net/tcp.h>
1151 +#include <linux/in.h>
1152 +#include <linux/ppp_defs.h>
1153 +#include <linux/if_pppox.h>
1154 +#endif
1155 +#if defined(CONFIG_RAETH_LRO)
1156 +#include <linux/inet_lro.h>
1157 +#endif
1158 +#include <linux/delay.h>
1159 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)
1160 +#include <linux/sched.h>
1161 +#endif
1162 +
1163 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 0)
1164 +#include <asm/rt2880/rt_mmap.h>
1165 +#else
1166 +#include <linux/libata-compat.h>
1167 +#endif
1168 +
1169 +#include "../ra2882ethreg.h"
1170 +#include "../raether.h"
1171 +#include "../ra_mac.h"
1172 +#include "../ra_ioctl.h"
1173 +#include "../ra_rfrw.h"
1174 +#ifdef CONFIG_RAETH_NETLINK
1175 +#include "../ra_netlink.h"
1176 +#endif
1177 +#if defined(CONFIG_RAETH_QOS)
1178 +#include "../ra_qos.h"
1179 +#endif
1180 +#include "raether_pdma_dvt.h"
1181 +
1182 +/* Global variables */
1183 +static unsigned int g_pdma_dvt_show_config;
1184 +static unsigned int g_pdma_dvt_rx_test_config;
1185 +static unsigned int g_pdma_dvt_tx_test_config;
1186 +static unsigned int g_pdma_dvt_debug_test_config;
1187 +static unsigned int g_pdma_dvt_lro_test_config;
1188 +
1189 +unsigned int g_pdma_dev_lanport = 0;
1190 +unsigned int g_pdma_dev_wanport = 0;
1191 +
1192 +void skb_dump(struct sk_buff *sk)
1193 +{
1194 + unsigned int i;
1195 +
1196 + printk("skb_dump: from %s with len %d (%d) headroom=%d tailroom=%d\n",
1197 + sk->dev ? sk->dev->name : "ip stack", sk->len, sk->truesize,
1198 + skb_headroom(sk), skb_tailroom(sk));
1199 +
1200 + /* for(i=(unsigned int)sk->head;i<=(unsigned int)sk->tail;i++) { */
1201 + /* for(i=(unsigned int)sk->head;i<=(unsigned int)sk->data+20;i++) { */
1202 + for (i = (unsigned int)sk->head; i <= (unsigned int)sk->data + 60; i++) {
1203 + if ((i % 20) == 0)
1204 + printk("\n");
1205 + if (i == (unsigned int)sk->data)
1206 + printk("{");
1207 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 21)
1208 + if (i == (unsigned int)sk->transport_header)
1209 + printk("#");
1210 + if (i == (unsigned int)sk->network_header)
1211 + printk("|");
1212 + if (i == (unsigned int)sk->mac_header)
1213 + printk("*");
1214 +#else
1215 + if (i == (unsigned int)sk->h.raw)
1216 + printk("#");
1217 + if (i == (unsigned int)sk->nh.raw)
1218 + printk("|");
1219 + if (i == (unsigned int)sk->mac.raw)
1220 + printk("*");
1221 +#endif
1222 + printk("%02X-", *((unsigned char *)i));
1223 + if (i == (unsigned int)sk->tail)
1224 + printk("}");
1225 + }
1226 + printk("\n");
1227 +}
1228 +
1229 +#if defined(CONFIG_RAETH_HW_LRO)
1230 +/* PDMA LRO test functions start */
1231 +int pdma_lro_disable_dvt(void)
1232 +{
1233 + unsigned int regVal = 0;
1234 +
1235 + printk("pdma_lro_disable_dvt()\n");
1236 +
1237 + /* 1. Invalid LRO ring1~3 */
1238 + SET_PDMA_RXRING_VALID(ADMA_RX_RING1, 0);
1239 + SET_PDMA_RXRING_VALID(ADMA_RX_RING2, 0);
1240 + SET_PDMA_RXRING_VALID(ADMA_RX_RING3, 0);
1241 +
1242 + /* 2 Polling relinguish */
1243 + while (sysRegRead(ADMA_LRO_CTRL_DW0) & PDMA_LRO_RELINGUISH) {;
1244 + }
1245 +
1246 + /* 3. Disable LRO */
1247 + regVal = sysRegRead(ADMA_LRO_CTRL_DW0);
1248 + regVal &= ~(PDMA_LRO_EN);
1249 + sysRegWrite(ADMA_LRO_CTRL_DW0, regVal);
1250 +
1251 +#if 0
1252 + /* 4. Disable non-lro multiple rx */
1253 + SET_PDMA_NON_LRO_MULTI_EN(0);
1254 +
1255 + /* 5.1. Set GDM1 to ring0 */
1256 + SET_GDM_PID1_RXID_SEL(0);
1257 + /* 5.2. Set GDM2 to ring0 */
1258 + SET_GDM_PID2_RXID_SEL(0);
1259 +#endif
1260 +
1261 + return 0;
1262 +}
1263 +
1264 +int pdma_lro_force_aggre_dvt(void)
1265 +{
1266 + unsigned int regVal = 0;
1267 + unsigned int ip;
1268 +
1269 + printk("pdma_lro_force_aggre_dvt()\n");
1270 +
1271 +/* pdma rx ring1 */
1272 + /* 1. Set RX ring mode to force port */
1273 + SET_PDMA_RXRING_MODE(ADMA_RX_RING1, PDMA_RX_FORCE_PORT);
1274 +
1275 + /* 2. Configure lro ring */
1276 + /* 2.1 set src/destination TCP ports */
1277 + SET_PDMA_RXRING_TCP_SRC_PORT(ADMA_RX_RING1, 3423);
1278 + SET_PDMA_RXRING_TCP_DEST_PORT(ADMA_RX_RING1, 2301);
1279 + /* 2.2 set src/destination IPs */
1280 + str_to_ip(&ip, "10.10.10.3");
1281 + sysRegWrite(LRO_RX_RING1_SIP_DW0, ip);
1282 + str_to_ip(&ip, "10.10.10.100");
1283 + sysRegWrite(LRO_RX_RING1_DIP_DW0, ip);
1284 + SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING1, 1);
1285 +
1286 + /* 2.3 Valid LRO ring */
1287 + SET_PDMA_RXRING_VALID(ADMA_RX_RING1, 1);
1288 +
1289 + /* 2.4 Set AGE timer */
1290 + SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING1, 0);
1291 +
1292 + /* 2.5 Set max AGG timer */
1293 + SET_PDMA_RXRING_AGG_TIME(ADMA_RX_RING1, 0);
1294 +
1295 + /* 2.6 Set max LRO agg count */
1296 + SET_PDMA_RXRING_MAX_AGG_CNT(ADMA_RX_RING1, HW_LRO_MAX_AGG_CNT);
1297 +
1298 + /* 3. IPv4 checksum update enable */
1299 + SET_PDMA_LRO_IPV4_CSUM_UPDATE_EN(1);
1300 +
1301 + /* 4. Polling relinguish */
1302 + while (sysRegRead(ADMA_LRO_CTRL_DW0) & PDMA_LRO_RELINGUISH) {;
1303 + }
1304 +
1305 + /* 5. Enable LRO */
1306 + regVal = sysRegRead(ADMA_LRO_CTRL_DW0);
1307 + regVal |= PDMA_LRO_EN;
1308 + sysRegWrite(ADMA_LRO_CTRL_DW0, regVal);
1309 +
1310 + return 0;
1311 +}
1312 +
1313 +int pdma_lro_auto_aggre_dvt(void)
1314 +{
1315 + unsigned int regVal = 0;
1316 + unsigned int ip;
1317 +
1318 + printk("pdma_lro_auto_aggre_dvt()\n");
1319 +
1320 + /* 1.1 Set my IP_1 */
1321 + str_to_ip(&ip, "10.10.10.254");
1322 + sysRegWrite(LRO_RX_RING0_DIP_DW0, ip);
1323 + sysRegWrite(LRO_RX_RING0_DIP_DW1, 0);
1324 + sysRegWrite(LRO_RX_RING0_DIP_DW2, 0);
1325 + sysRegWrite(LRO_RX_RING0_DIP_DW3, 0);
1326 + SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING0, 1);
1327 +
1328 + /* 1.2 Set my IP_2 */
1329 + str_to_ip(&ip, "10.10.20.254");
1330 + sysRegWrite(LRO_RX_RING1_DIP_DW0, ip);
1331 + sysRegWrite(LRO_RX_RING1_DIP_DW1, 0);
1332 + sysRegWrite(LRO_RX_RING1_DIP_DW2, 0);
1333 + sysRegWrite(LRO_RX_RING1_DIP_DW3, 0);
1334 + SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING1, 1);
1335 +
1336 + /* 1.3 Set my IP_3 */
1337 + sysRegWrite(LRO_RX_RING2_DIP_DW3, 0x20010238);
1338 + sysRegWrite(LRO_RX_RING2_DIP_DW2, 0x08000000);
1339 + sysRegWrite(LRO_RX_RING2_DIP_DW1, 0x00000000);
1340 + sysRegWrite(LRO_RX_RING2_DIP_DW0, 0x00000254);
1341 + SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING2, 1);
1342 +
1343 + /* 1.4 Set my IP_4 */
1344 + sysRegWrite(LRO_RX_RING3_DIP_DW3, 0x20010238);
1345 + sysRegWrite(LRO_RX_RING3_DIP_DW2, 0x08010000);
1346 + sysRegWrite(LRO_RX_RING3_DIP_DW1, 0x00000000);
1347 + sysRegWrite(LRO_RX_RING3_DIP_DW0, 0x00000254);
1348 + SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING3, 1);
1349 +
1350 + /* 2.1 Set RX ring1~3 to auto-learn modes */
1351 + SET_PDMA_RXRING_MODE(ADMA_RX_RING1, PDMA_RX_AUTO_LEARN);
1352 + SET_PDMA_RXRING_MODE(ADMA_RX_RING2, PDMA_RX_AUTO_LEARN);
1353 + SET_PDMA_RXRING_MODE(ADMA_RX_RING3, PDMA_RX_AUTO_LEARN);
1354 +
1355 + /* 2.2 Valid LRO ring */
1356 + SET_PDMA_RXRING_VALID(ADMA_RX_RING0, 1);
1357 + SET_PDMA_RXRING_VALID(ADMA_RX_RING1, 1);
1358 + SET_PDMA_RXRING_VALID(ADMA_RX_RING2, 1);
1359 + SET_PDMA_RXRING_VALID(ADMA_RX_RING3, 1);
1360 +
1361 + /* 2.3 Set AGE timer */
1362 + SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING1, 0);
1363 + SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING2, 0);
1364 + SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING3, 0);
1365 +
1366 + /* 2.4 Set max AGG timer */
1367 + SET_PDMA_RXRING_AGG_TIME(ADMA_RX_RING1, 0);
1368 + SET_PDMA_RXRING_AGG_TIME(ADMA_RX_RING2, 0);
1369 + SET_PDMA_RXRING_AGG_TIME(ADMA_RX_RING3, 0);
1370 +
1371 + /* 2.5 Set max LRO agg count */
1372 + SET_PDMA_RXRING_MAX_AGG_CNT(ADMA_RX_RING1, HW_LRO_MAX_AGG_CNT);
1373 + SET_PDMA_RXRING_MAX_AGG_CNT(ADMA_RX_RING2, HW_LRO_MAX_AGG_CNT);
1374 + SET_PDMA_RXRING_MAX_AGG_CNT(ADMA_RX_RING3, HW_LRO_MAX_AGG_CNT);
1375 +
1376 + /* 3.0 IPv6 LRO enable */
1377 + SET_PDMA_LRO_IPV6_EN(1);
1378 +
1379 + /* 3.1 IPv4 checksum update disable */
1380 + SET_PDMA_LRO_IPV4_CSUM_UPDATE_EN(1);
1381 +
1382 + /* 3.2 switch priority comparision to byte count mode */
1383 + SET_PDMA_LRO_ALT_SCORE_MODE(PDMA_LRO_ALT_BYTE_CNT_MODE);
1384 +
1385 + /* 3.3 bandwidth threshold setting */
1386 + SET_PDMA_LRO_BW_THRESHOLD(0);
1387 +
1388 + /* 3.4 auto-learn score delta setting */
1389 + sysRegWrite(LRO_ALT_SCORE_DELTA, 0);
1390 +
1391 + /* 3.5 Set ALT timer to 20us: (unit: 20us) */
1392 + SET_PDMA_LRO_ALT_REFRESH_TIMER_UNIT(HW_LRO_TIMER_UNIT);
1393 + /* 3.6 Set ALT refresh timer to 1 sec. (unit: 20us) */
1394 + SET_PDMA_LRO_ALT_REFRESH_TIMER(HW_LRO_REFRESH_TIME);
1395 +
1396 + /* 4. Polling relinguish */
1397 + while (sysRegRead(ADMA_LRO_CTRL_DW0) & PDMA_LRO_RELINGUISH) {;
1398 + }
1399 +
1400 + /* 5. Enable LRO */
1401 + regVal = sysRegRead(ADMA_LRO_CTRL_DW0);
1402 + regVal |= PDMA_LRO_EN;
1403 + sysRegWrite(ADMA_LRO_CTRL_DW0, regVal);
1404 +
1405 + return 0;
1406 +}
1407 +
1408 +int pdma_lro_auto_ipv6_dvt(void)
1409 +{
1410 + unsigned int regVal = 0;
1411 +
1412 + printk("pdma_lro_auto_ipv6_dvt()\n");
1413 +
1414 + /* 1. Set my IP */
1415 + sysRegWrite(LRO_RX_RING1_DIP_DW3, 0x20010238);
1416 + sysRegWrite(LRO_RX_RING1_DIP_DW2, 0x08000000);
1417 + sysRegWrite(LRO_RX_RING1_DIP_DW1, 0x00000000);
1418 + sysRegWrite(LRO_RX_RING1_DIP_DW0, 0x00000254);
1419 +
1420 + /* 2.1 Set RX ring1~3 to auto-learn modes */
1421 + SET_PDMA_RXRING_MODE(ADMA_RX_RING1, PDMA_RX_AUTO_LEARN);
1422 + SET_PDMA_RXRING_MODE(ADMA_RX_RING2, PDMA_RX_AUTO_LEARN);
1423 + SET_PDMA_RXRING_MODE(ADMA_RX_RING3, PDMA_RX_AUTO_LEARN);
1424 +
1425 + /* 2.2 Valid LRO ring */
1426 + SET_PDMA_RXRING_VALID(ADMA_RX_RING1, 1);
1427 + SET_PDMA_RXRING_VALID(ADMA_RX_RING2, 1);
1428 + SET_PDMA_RXRING_VALID(ADMA_RX_RING3, 1);
1429 +
1430 + /* 2.3 Set AGE timer */
1431 + SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING1, HW_LRO_AGE_TIME);
1432 + SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING2, HW_LRO_AGE_TIME);
1433 + SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING3, HW_LRO_AGE_TIME);
1434 +
1435 + /* 3.0 IPv6 LRO enable */
1436 + SET_PDMA_LRO_IPV6_EN(1);
1437 +
1438 + /* 3.1 IPv4 checksum update disable */
1439 + SET_PDMA_LRO_IPV4_CSUM_UPDATE_EN(1);
1440 +
1441 + /* 3.2 switch priority comparision to byte count mode */
1442 + SET_PDMA_LRO_ALT_SCORE_MODE(PDMA_LRO_ALT_BYTE_CNT_MODE);
1443 +
1444 + /* 3.3 bandwidth threshold setting */
1445 + SET_PDMA_LRO_BW_THRESHOLD(0);
1446 +
1447 + /* 3.4 auto-learn score delta setting */
1448 + sysRegWrite(LRO_ALT_SCORE_DELTA, 0);
1449 +
1450 + /* 3.5 Set ALT timer to 500us: (unit: 20us) */
1451 + SET_PDMA_LRO_ALT_REFRESH_TIMER_UNIT(25);
1452 + /* 3.6 Set ALT refresh timer to 1 sec. (unit: 500us) */
1453 + SET_PDMA_LRO_ALT_REFRESH_TIMER(2000);
1454 +
1455 + /* 3.7 Set max AGG timer: 10 msec. */
1456 + SET_PDMA_LRO_MAX_AGG_TIME(HW_LRO_AGG_TIME);
1457 +
1458 + /* 4. Polling relinguish */
1459 + while (sysRegRead(ADMA_LRO_CTRL_DW0) & PDMA_LRO_RELINGUISH) {;
1460 + }
1461 +
1462 + /* 5. Enable LRO */
1463 + regVal = sysRegRead(ADMA_LRO_CTRL_DW0);
1464 + regVal |= PDMA_LRO_EN;
1465 + sysRegWrite(ADMA_LRO_CTRL_DW0, regVal);
1466 +
1467 + return 0;
1468 +}
1469 +
1470 +int pdma_lro_auto_myIP_dvt(void)
1471 +{
1472 + unsigned int regVal = 0;
1473 + unsigned int ip;
1474 +
1475 + printk("pdma_lro_auto_myIP_dvt()\n");
1476 +
1477 + /* 1.1 Set my IP_1 */
1478 + str_to_ip(&ip, "10.10.10.254");
1479 + sysRegWrite(LRO_RX_RING0_DIP_DW0, ip);
1480 + sysRegWrite(LRO_RX_RING0_DIP_DW1, 0);
1481 + sysRegWrite(LRO_RX_RING0_DIP_DW2, 0);
1482 + sysRegWrite(LRO_RX_RING0_DIP_DW3, 0);
1483 + SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING0, 1);
1484 + /* 1.2 Set my IP_2 */
1485 + str_to_ip(&ip, "10.10.20.254");
1486 + sysRegWrite(LRO_RX_RING1_DIP_DW0, ip);
1487 + sysRegWrite(LRO_RX_RING1_DIP_DW1, 0);
1488 + sysRegWrite(LRO_RX_RING1_DIP_DW2, 0);
1489 + sysRegWrite(LRO_RX_RING1_DIP_DW3, 0);
1490 + SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING1, 1);
1491 + /* 1.3 Set my IP_3 */
1492 + sysRegWrite(LRO_RX_RING2_DIP_DW3, 0x20010238);
1493 + sysRegWrite(LRO_RX_RING2_DIP_DW2, 0x08000000);
1494 + sysRegWrite(LRO_RX_RING2_DIP_DW1, 0x00000000);
1495 + sysRegWrite(LRO_RX_RING2_DIP_DW0, 0x00000254);
1496 + SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING2, 1);
1497 + /* 1.4 Set my IP_4 */
1498 + sysRegWrite(LRO_RX_RING3_DIP_DW3, 0x20010238);
1499 + sysRegWrite(LRO_RX_RING3_DIP_DW2, 0x08010000);
1500 + sysRegWrite(LRO_RX_RING3_DIP_DW1, 0x00000000);
1501 + sysRegWrite(LRO_RX_RING3_DIP_DW0, 0x00000254);
1502 + SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING3, 1);
1503 +
1504 + /* 2.1 Set RX ring1~3 to auto-learn modes */
1505 + SET_PDMA_RXRING_MODE(ADMA_RX_RING1, PDMA_RX_AUTO_LEARN);
1506 + SET_PDMA_RXRING_MODE(ADMA_RX_RING2, PDMA_RX_AUTO_LEARN);
1507 + SET_PDMA_RXRING_MODE(ADMA_RX_RING3, PDMA_RX_AUTO_LEARN);
1508 +
1509 + /* 2.2 Valid LRO ring */
1510 + SET_PDMA_RXRING_VALID(ADMA_RX_RING0, 1);
1511 + SET_PDMA_RXRING_VALID(ADMA_RX_RING1, 1);
1512 + SET_PDMA_RXRING_VALID(ADMA_RX_RING2, 1);
1513 + SET_PDMA_RXRING_VALID(ADMA_RX_RING3, 1);
1514 +
1515 + /* 2.3 Set AGE timer */
1516 + SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING1, HW_LRO_AGE_TIME);
1517 + SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING2, HW_LRO_AGE_TIME);
1518 + SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING3, HW_LRO_AGE_TIME);
1519 +
1520 + /* 3.0 IPv6 LRO enable */
1521 + SET_PDMA_LRO_IPV6_EN(1);
1522 +
1523 + /* 3.1 IPv4 checksum update disable */
1524 + SET_PDMA_LRO_IPV4_CSUM_UPDATE_EN(1);
1525 +
1526 + /* 3.2 switch priority comparision to byte count mode */
1527 + SET_PDMA_LRO_ALT_SCORE_MODE(PDMA_LRO_ALT_BYTE_CNT_MODE);
1528 +
1529 + /* 3.3 bandwidth threshold setting */
1530 + SET_PDMA_LRO_BW_THRESHOLD(0);
1531 +
1532 + /* 3.4 auto-learn score delta setting */
1533 + sysRegWrite(LRO_ALT_SCORE_DELTA, 0);
1534 +
1535 + /* 3.5 Set ALT timer to 500us: (unit: 20us) */
1536 + SET_PDMA_LRO_ALT_REFRESH_TIMER_UNIT(25);
1537 + /* 3.6 Set ALT refresh timer to 1 sec. (unit: 500us) */
1538 + SET_PDMA_LRO_ALT_REFRESH_TIMER(2000);
1539 +
1540 + /* 3.7 Set max AGG timer: 10 msec. */
1541 + SET_PDMA_LRO_MAX_AGG_TIME(HW_LRO_AGG_TIME);
1542 +
1543 + /* 4. Polling relinguish */
1544 + while (sysRegRead(ADMA_LRO_CTRL_DW0) & PDMA_LRO_RELINGUISH) {;
1545 + }
1546 +
1547 + /* 5. Enable LRO */
1548 + regVal = sysRegRead(ADMA_LRO_CTRL_DW0);
1549 + regVal |= PDMA_LRO_EN;
1550 + sysRegWrite(ADMA_LRO_CTRL_DW0, regVal);
1551 +
1552 + return 0;
1553 +}
1554 +
1555 +int pdma_lro_dly_int_dvt(int index)
1556 +{
1557 + unsigned int regVal = 0;
1558 + unsigned int ip;
1559 +
1560 + printk("pdma_lro_dly_int_dvt(%d)\n", index);
1561 +
1562 +#if 0
1563 + /* 1.1 Set my IP_1 */
1564 + /* str_to_ip( &ip, "10.10.10.254" ); */
1565 + str_to_ip(&ip, "10.10.10.100");
1566 + sysRegWrite(LRO_RX_RING0_DIP_DW0, ip);
1567 + sysRegWrite(LRO_RX_RING0_DIP_DW1, 0);
1568 + sysRegWrite(LRO_RX_RING0_DIP_DW2, 0);
1569 + sysRegWrite(LRO_RX_RING0_DIP_DW3, 0);
1570 +#else
1571 + /* 1.1 set src/destination TCP ports */
1572 + SET_PDMA_RXRING_TCP_SRC_PORT(ADMA_RX_RING1, 3423);
1573 + SET_PDMA_RXRING_TCP_DEST_PORT(ADMA_RX_RING1, 2301);
1574 + SET_PDMA_RXRING_TCP_SRC_PORT(ADMA_RX_RING2, 3423);
1575 + SET_PDMA_RXRING_TCP_DEST_PORT(ADMA_RX_RING2, 2301);
1576 + SET_PDMA_RXRING_TCP_SRC_PORT(ADMA_RX_RING3, 3423);
1577 + SET_PDMA_RXRING_TCP_DEST_PORT(ADMA_RX_RING3, 2301);
1578 + /* 1.2 set src/destination IPs */
1579 + str_to_ip(&ip, "10.10.10.3");
1580 + sysRegWrite(LRO_RX_RING1_SIP_DW0, ip);
1581 + str_to_ip(&ip, "10.10.10.100");
1582 + sysRegWrite(LRO_RX_RING1_DIP_DW0, ip);
1583 + str_to_ip(&ip, "10.10.10.3");
1584 + sysRegWrite(LRO_RX_RING2_SIP_DW0, ip);
1585 + str_to_ip(&ip, "10.10.10.100");
1586 + sysRegWrite(LRO_RX_RING2_DIP_DW0, ip);
1587 + str_to_ip(&ip, "10.10.10.3");
1588 + sysRegWrite(LRO_RX_RING3_SIP_DW0, ip);
1589 + str_to_ip(&ip, "10.10.10.100");
1590 + sysRegWrite(LRO_RX_RING3_DIP_DW0, ip);
1591 + SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING1, 1);
1592 + SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING2, 1);
1593 + SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING3, 1);
1594 +#endif
1595 +
1596 + if (index == 0) {
1597 + /* 1.2 Disable DLY_INT for lro ring */
1598 + SET_PDMA_LRO_DLY_INT_EN(0);
1599 + } else {
1600 + /* 1.2 Enable DLY_INT for lro ring */
1601 + SET_PDMA_LRO_DLY_INT_EN(1);
1602 + }
1603 +
1604 + /* 1.3 LRO ring DLY_INT setting */
1605 + if (index == 1) {
1606 + sysRegWrite(LRO_RX1_DLY_INT, DELAY_INT_INIT);
1607 + } else if (index == 2) {
1608 + sysRegWrite(LRO_RX2_DLY_INT, DELAY_INT_INIT);
1609 + } else if (index == 3) {
1610 + sysRegWrite(LRO_RX3_DLY_INT, DELAY_INT_INIT);
1611 + }
1612 +#if 0
1613 + /* 2.1 Set RX rings to auto-learn modes */
1614 + SET_PDMA_RXRING_MODE(ADMA_RX_RING1, PDMA_RX_AUTO_LEARN);
1615 + SET_PDMA_RXRING_MODE(ADMA_RX_RING2, PDMA_RX_AUTO_LEARN);
1616 + SET_PDMA_RXRING_MODE(ADMA_RX_RING3, PDMA_RX_AUTO_LEARN);
1617 +#else
1618 + /* 2.0 set rx ring mode */
1619 + SET_PDMA_RXRING_MODE(ADMA_RX_RING1, PDMA_RX_FORCE_PORT);
1620 + SET_PDMA_RXRING_MODE(ADMA_RX_RING2, PDMA_RX_FORCE_PORT);
1621 + SET_PDMA_RXRING_MODE(ADMA_RX_RING3, PDMA_RX_FORCE_PORT);
1622 +
1623 + /* 2.1 IPv4 force port mode */
1624 + SET_PDMA_RXRING_IPV4_FORCE_MODE(ADMA_RX_RING1, 1);
1625 + SET_PDMA_RXRING_IPV4_FORCE_MODE(ADMA_RX_RING2, 1);
1626 + SET_PDMA_RXRING_IPV4_FORCE_MODE(ADMA_RX_RING3, 1);
1627 +#endif
1628 +
1629 + /* 2.2 Valid LRO ring */
1630 + SET_PDMA_RXRING_VALID(ADMA_RX_RING0, 1);
1631 + if ((index == 0) || (index == 1)) {
1632 + SET_PDMA_RXRING_VALID(ADMA_RX_RING1, 1);
1633 + SET_PDMA_RXRING_VALID(ADMA_RX_RING2, 0);
1634 + SET_PDMA_RXRING_VALID(ADMA_RX_RING3, 0);
1635 + } else if (index == 2) {
1636 + SET_PDMA_RXRING_VALID(ADMA_RX_RING1, 0);
1637 + SET_PDMA_RXRING_VALID(ADMA_RX_RING2, 1);
1638 + SET_PDMA_RXRING_VALID(ADMA_RX_RING3, 0);
1639 + } else {
1640 + SET_PDMA_RXRING_VALID(ADMA_RX_RING1, 0);
1641 + SET_PDMA_RXRING_VALID(ADMA_RX_RING2, 0);
1642 + SET_PDMA_RXRING_VALID(ADMA_RX_RING3, 1);
1643 + }
1644 +
1645 + /* 2.3 Set AGE timer */
1646 + SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING1, HW_LRO_AGE_TIME);
1647 + SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING2, HW_LRO_AGE_TIME);
1648 + SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING3, HW_LRO_AGE_TIME);
1649 +
1650 + /* 3.1 IPv4 checksum update enable */
1651 + SET_PDMA_LRO_IPV4_CSUM_UPDATE_EN(1);
1652 +
1653 + /* 3.2 switch priority comparision to byte count mode */
1654 + SET_PDMA_LRO_ALT_SCORE_MODE(PDMA_LRO_ALT_BYTE_CNT_MODE);
1655 +
1656 + /* 3.3 bandwidth threshold setting */
1657 + SET_PDMA_LRO_BW_THRESHOLD(0);
1658 +
1659 + /* 3.4 auto-learn score delta setting */
1660 + sysRegWrite(LRO_ALT_SCORE_DELTA, 0);
1661 +
1662 + /* 3.5 Set ALT timer to 500us: (unit: 20us) */
1663 + SET_PDMA_LRO_ALT_REFRESH_TIMER_UNIT(25);
1664 + /* 3.6 Set ALT refresh timer to 1 sec. (unit: 500us) */
1665 + SET_PDMA_LRO_ALT_REFRESH_TIMER(2000);
1666 +
1667 + /* 3.7 Set max AGG timer */
1668 + SET_PDMA_LRO_MAX_AGG_TIME(HW_LRO_AGG_TIME);
1669 +
1670 + /* 4. Polling relinguish */
1671 + while (sysRegRead(ADMA_LRO_CTRL_DW0) & PDMA_LRO_RELINGUISH) {;
1672 + }
1673 +
1674 + /* 5. Enable LRO */
1675 + regVal = sysRegRead(ADMA_LRO_CTRL_DW0);
1676 + regVal |= PDMA_LRO_EN;
1677 + sysRegWrite(ADMA_LRO_CTRL_DW0, regVal);
1678 +
1679 + return 0;
1680 +}
1681 +
1682 +int pdma_lro_dly_int0_dvt(void)
1683 +{
1684 + return pdma_lro_dly_int_dvt(0);
1685 +}
1686 +
1687 +int pdma_lro_dly_int1_dvt(void)
1688 +{
1689 + return pdma_lro_dly_int_dvt(1);
1690 +}
1691 +
1692 +int pdma_lro_dly_int2_dvt(void)
1693 +{
1694 + return pdma_lro_dly_int_dvt(2);
1695 +}
1696 +
1697 +int pdma_lro_dly_int3_dvt(void)
1698 +{
1699 + return pdma_lro_dly_int_dvt(3);
1700 +}
1701 +
1702 +#endif /* CONFIG_RAETH_HW_LRO */
1703 +
1704 +#if defined(CONFIG_RAETH_MULTIPLE_RX_RING)
1705 +int pdma_gdm_rxid_config(void)
1706 +{
1707 + unsigned int regVal = 0;
1708 +
1709 + printk("pdma_gdm_rxid_config()\n");
1710 +
1711 + /* 1. Set RX ring1~3 to pse modes */
1712 + SET_PDMA_RXRING_MODE(ADMA_RX_RING1, PDMA_RX_PSE_MODE);
1713 + SET_PDMA_RXRING_MODE(ADMA_RX_RING2, PDMA_RX_PSE_MODE);
1714 + SET_PDMA_RXRING_MODE(ADMA_RX_RING3, PDMA_RX_PSE_MODE);
1715 +
1716 + /* 2. Enable non-lro multiple rx */
1717 + SET_PDMA_NON_LRO_MULTI_EN(1);
1718 +
1719 + return 0;
1720 +}
1721 +
1722 +int pdma_non_lro_portid_dvt(void)
1723 +{
1724 + unsigned int regVal = 0;
1725 +
1726 + printk("pdma_non_lro_portid_dvt()\n");
1727 +
1728 + /* 1. Set GDM1 to ring3 */
1729 + SET_GDM_PID1_RXID_SEL(3);
1730 +#if 0
1731 + /* 2. Set GDM2 to ring1 */
1732 + SET_GDM_PID2_RXID_SEL(1);
1733 +#endif
1734 +
1735 + /* 3. Set priority rule: pid */
1736 + SET_GDM_RXID_PRI_SEL(GDM_PRI_PID);
1737 +
1738 + /* PDMA multi-rx enable */
1739 + pdma_gdm_rxid_config();
1740 +
1741 + return 0;
1742 +}
1743 +
1744 +int pdma_non_lro_stag_dvt(void)
1745 +{
1746 + unsigned int regVal = 0;
1747 +
1748 + printk("pdma_non_lro_stag_dvt()\n");
1749 +
1750 + /* 1. Set STAG4 to ring0 */
1751 + GDM_STAG_RXID_SEL(4, 0);
1752 + /* 2. Set STAG3 to ring1 */
1753 + GDM_STAG_RXID_SEL(3, 1);
1754 + /* 3. Set STAG2 to ring2 */
1755 + GDM_STAG_RXID_SEL(2, 2);
1756 + /* 4. Set STAG1 to ring3 */
1757 + GDM_STAG_RXID_SEL(1, 3);
1758 +
1759 + /* 5. Set priority rule: stag/pid */
1760 + SET_GDM_RXID_PRI_SEL(GDM_PRI_PID);
1761 +
1762 + /* PDMA multi-rx enable */
1763 + pdma_gdm_rxid_config();
1764 +
1765 + return 0;
1766 +}
1767 +
1768 +int pdma_non_lro_vlan_dvt(void)
1769 +{
1770 + unsigned int regVal = 0;
1771 +
1772 + printk("pdma_non_lro_vlan_dvt()\n");
1773 +
1774 + /* 1. Set vlan priority=3 to ring1 */
1775 + SET_GDM_VLAN_PRI_RXID_SEL(3, 1);
1776 + /* 2. Set vlan priority=2 to ring2 */
1777 + SET_GDM_VLAN_PRI_RXID_SEL(2, 2);
1778 + /* 3. Set vlan priority=1 to ring3 */
1779 + SET_GDM_VLAN_PRI_RXID_SEL(1, 3);
1780 + /* 4. Set vlan priority=0 to ring3 */
1781 + SET_GDM_VLAN_PRI_RXID_SEL(0, 3);
1782 +
1783 + /* 1. Set vlan priority=4 to ring1 */
1784 + SET_GDM_VLAN_PRI_RXID_SEL(4, 1);
1785 + /* 2. Set vlan priority=5 to ring2 */
1786 + SET_GDM_VLAN_PRI_RXID_SEL(5, 2);
1787 + /* 3. Set vlan priority=6 to ring3 */
1788 + SET_GDM_VLAN_PRI_RXID_SEL(6, 3);
1789 + /* 4. Set vlan priority=7 to ring3 */
1790 + SET_GDM_VLAN_PRI_RXID_SEL(7, 3);
1791 +
1792 + /* 4. Set priority rule: vlan > pid */
1793 + SET_GDM_RXID_PRI_SEL(GDM_PRI_VLAN_PID);
1794 +
1795 + /* PDMA multi-rx enable */
1796 + pdma_gdm_rxid_config();
1797 +
1798 + return 0;
1799 +}
1800 +
1801 +int pdma_non_lro_tcpack_dvt(void)
1802 +{
1803 + unsigned int regVal = 0;
1804 +
1805 + printk("pdma_non_lro_tcpack_dvt()\n");
1806 +
1807 + /* 1. Enable TCP ACK with zero payload check */
1808 + SET_GDM_TCP_ACK_WZPC(1);
1809 + /* 2. Set TCP ACK to ring3 */
1810 + SET_GDM_TCP_ACK_RXID_SEL(3);
1811 +
1812 + /* 3. Set priority rule: ack > pid */
1813 + SET_GDM_RXID_PRI_SEL(GDM_PRI_ACK_PID);
1814 +
1815 + /* PDMA multi-rx enable */
1816 + pdma_gdm_rxid_config();
1817 +
1818 + return 0;
1819 +}
1820 +
1821 +int pdma_non_lro_pri1_dvt(void)
1822 +{
1823 + unsigned int regVal = 0;
1824 +
1825 + printk("pdma_non_lro_pri1_dvt()\n");
1826 +
1827 + /* 1. Set GDM1 to ring0 */
1828 + SET_GDM_PID1_RXID_SEL(0);
1829 +
1830 + /* 2.1 Disable TCP ACK with zero payload check */
1831 + SET_GDM_TCP_ACK_WZPC(0);
1832 + /* 2.2 Set TCP ACK to ring1 */
1833 + SET_GDM_TCP_ACK_RXID_SEL(1);
1834 +
1835 + /* 3. Set vlan priority=1 to ring2 */
1836 + SET_GDM_VLAN_PRI_RXID_SEL(1, 2);
1837 +
1838 + /* 4. Set priority rule: vlan > ack > pid */
1839 + SET_GDM_RXID_PRI_SEL(GDM_PRI_VLAN_ACK_PID);
1840 +
1841 + /* PDMA multi-rx enable */
1842 + pdma_gdm_rxid_config();
1843 +
1844 + return 0;
1845 +}
1846 +
1847 +int pdma_non_lro_pri2_dvt(void)
1848 +{
1849 + unsigned int regVal = 0;
1850 +
1851 + printk("pdma_non_lro_pri2_dvt()\n");
1852 +
1853 + /* 1. Set GDM1 to ring0 */
1854 + SET_GDM_PID1_RXID_SEL(0);
1855 +
1856 + /* 2.1 Disable TCP ACK with zero payload check */
1857 + SET_GDM_TCP_ACK_WZPC(0);
1858 + /* 2.2 Set TCP ACK to ring1 */
1859 + SET_GDM_TCP_ACK_RXID_SEL(1);
1860 +
1861 + /* 3. Set vlan priority=1 to ring2 */
1862 + SET_GDM_VLAN_PRI_RXID_SEL(1, 2);
1863 +
1864 + /* 4. Set priority rule: ack > vlan > pid */
1865 + SET_GDM_RXID_PRI_SEL(GDM_PRI_ACK_VLAN_PID);
1866 +
1867 + /* PDMA multi-rx enable */
1868 + pdma_gdm_rxid_config();
1869 +
1870 + return 0;
1871 +}
1872 +#endif /* CONFIG_RAETH_MULTIPLE_RX_RING */
1873 +const static PDMA_LRO_DVT_FUNC pdma_dvt_lro_func[] = {
1874 +#if defined(CONFIG_RAETH_HW_LRO)
1875 + [0] = pdma_lro_disable_dvt, /* PDMA_TEST_LRO_DISABLE */
1876 + [1] = pdma_lro_force_aggre_dvt, /* PDMA_TEST_LRO_FORCE_PORT */
1877 + [2] = pdma_lro_auto_aggre_dvt, /* PDMA_TEST_LRO_AUTO_LEARN */
1878 + [3] = pdma_lro_auto_ipv6_dvt, /* PDMA_TEST_LRO_AUTO_IPV6 */
1879 + [4] = pdma_lro_auto_myIP_dvt, /* PDMA_TEST_LRO_AUTO_MYIP */
1880 + [5] = pdma_lro_force_aggre_dvt, /* PDMA_TEST_LRO_FORCE_AGGREGATE */
1881 +#endif /* CONFIG_RAETH_HW_LRO */
1882 +#if defined(CONFIG_RAETH_MULTIPLE_RX_RING)
1883 + [6] = pdma_non_lro_portid_dvt, /* PDMA_TEST_NON_LRO_PORT_ID */
1884 + [7] = pdma_non_lro_stag_dvt, /* PDMA_TEST_NON_LRO_STAG */
1885 + [8] = pdma_non_lro_vlan_dvt, /* PDMA_TEST_NON_LRO_VLAN */
1886 + [9] = pdma_non_lro_tcpack_dvt, /* PDMA_TEST_NON_LRO_TCP_ACK */
1887 + [10] = pdma_non_lro_pri1_dvt, /* PDMA_TEST_NON_LRO_PRI1 */
1888 + [11] = pdma_non_lro_pri2_dvt, /* PDMA_TEST_NON_LRO_PRI2 */
1889 +#endif /* CONFIG_RAETH_MULTIPLE_RX_RING */
1890 +#if defined(CONFIG_RAETH_HW_LRO)
1891 + [12] = pdma_lro_dly_int0_dvt, /* PDMA_TEST_LRO_DLY_INT0 */
1892 + [13] = pdma_lro_dly_int1_dvt, /* PDMA_TEST_LRO_DLY_INT1 */
1893 + [14] = pdma_lro_dly_int2_dvt, /* PDMA_TEST_LRO_DLY_INT2 */
1894 + [15] = pdma_lro_dly_int3_dvt, /* PDMA_TEST_LRO_DLY_INT3 */
1895 +#endif /* CONFIG_RAETH_HW_LRO */
1896 +};
1897 +
1898 +/* PDMA LRO test functions end */
1899 +
1900 +#if defined(CONFIG_RAETH_HW_LRO) || defined(CONFIG_RAETH_MULTIPLE_RX_RING)
1901 +void raeth_pdma_lro_dvt(int rx_ring_no, END_DEVICE *ei_local,
1902 + int rx_dma_owner_idx0)
1903 +{
1904 + if (pdma_dvt_get_show_config() & PDMA_SHOW_RX_DESC) {
1905 + if (rx_ring_no == 1) {
1906 + printk("------- rt2880_eth_recv (ring1) --------\n");
1907 + printk("rx_info1=0x%x\n",
1908 + *(unsigned int *)
1909 + &ei_local->rx_ring1[rx_dma_owner_idx0].
1910 + rxd_info1);
1911 + printk("rx_info2=0x%x\n",
1912 + *(unsigned int *)
1913 + &ei_local->rx_ring1[rx_dma_owner_idx0].
1914 + rxd_info2);
1915 + printk("rx_info3=0x%x\n",
1916 + *(unsigned int *)
1917 + &ei_local->rx_ring1[rx_dma_owner_idx0].
1918 + rxd_info3);
1919 + printk("rx_info4=0x%x\n",
1920 + *(unsigned int *)
1921 + &ei_local->rx_ring1[rx_dma_owner_idx0].
1922 + rxd_info4);
1923 + printk("-------------------------------\n");
1924 + } else if (rx_ring_no == 2) {
1925 + printk("------- rt2880_eth_recv (ring2) --------\n");
1926 + printk("rx_info1=0x%x\n",
1927 + *(unsigned int *)
1928 + &ei_local->rx_ring2[rx_dma_owner_idx0].
1929 + rxd_info1);
1930 + printk("rx_info2=0x%x\n",
1931 + *(unsigned int *)
1932 + &ei_local->rx_ring2[rx_dma_owner_idx0].
1933 + rxd_info2);
1934 + printk("rx_info3=0x%x\n",
1935 + *(unsigned int *)
1936 + &ei_local->rx_ring2[rx_dma_owner_idx0].
1937 + rxd_info3);
1938 + printk("rx_info4=0x%x\n",
1939 + *(unsigned int *)
1940 + &ei_local->rx_ring2[rx_dma_owner_idx0].
1941 + rxd_info4);
1942 + printk("-------------------------------\n");
1943 + } else if (rx_ring_no == 3) {
1944 + printk("------- rt2880_eth_recv (ring3) --------\n");
1945 + printk("rx_info1=0x%x\n",
1946 + *(unsigned int *)
1947 + &ei_local->rx_ring3[rx_dma_owner_idx0].
1948 + rxd_info1);
1949 + printk("rx_info2=0x%x\n",
1950 + *(unsigned int *)
1951 + &ei_local->rx_ring3[rx_dma_owner_idx0].
1952 + rxd_info2);
1953 + printk("rx_info3=0x%x\n",
1954 + *(unsigned int *)
1955 + &ei_local->rx_ring3[rx_dma_owner_idx0].
1956 + rxd_info3);
1957 + printk("rx_info4=0x%x\n",
1958 + *(unsigned int *)
1959 + &ei_local->rx_ring3[rx_dma_owner_idx0].
1960 + rxd_info4);
1961 + printk("-------------------------------\n");
1962 + }
1963 +#if 0
1964 + else {
1965 + printk("------- rt2880_eth_recv (ring0) --------\n");
1966 + printk("rx_info1=0x%x\n",
1967 + *(unsigned int *)
1968 + &ei_local->rx_ring0[rx_dma_owner_idx0].
1969 + rxd_info1);
1970 + printk("rx_info2=0x%x\n",
1971 + *(unsigned int *)
1972 + &ei_local->rx_ring0[rx_dma_owner_idx0].
1973 + rxd_info2);
1974 + printk("rx_info3=0x%x\n",
1975 + *(unsigned int *)
1976 + &ei_local->rx_ring0[rx_dma_owner_idx0].
1977 + rxd_info3);
1978 + printk("rx_info4=0x%x\n",
1979 + *(unsigned int *)
1980 + &ei_local->rx_ring0[rx_dma_owner_idx0].
1981 + rxd_info4);
1982 + printk("-------------------------------\n");
1983 + }
1984 +#endif
1985 + }
1986 + if ((pdma_dvt_get_show_config() & PDMA_SHOW_DETAIL_RX_DESC) ||
1987 + (pdma_dvt_get_lro_test_config()==PDMA_TEST_LRO_FORCE_PORT)) {
1988 + if (rx_ring_no == 1) {
1989 + printk("------- rt2880_eth_recv (ring1) --------\n");
1990 + printk("rx_info1.PDP0=0x%x\n",
1991 + ei_local->rx_ring1[rx_dma_owner_idx0].
1992 + rxd_info1.PDP0);
1993 + printk("rx_info2.DDONE_bit=0x%x\n",
1994 + ei_local->rx_ring1[rx_dma_owner_idx0].
1995 + rxd_info2.DDONE_bit);
1996 + printk("rx_info2.LS0=0x%x\n",
1997 + ei_local->rx_ring1[rx_dma_owner_idx0].
1998 + rxd_info2.LS0);
1999 + printk("rx_info2.PLEN0=0x%x\n",
2000 + ei_local->rx_ring1[rx_dma_owner_idx0].
2001 + rxd_info2.PLEN0);
2002 + printk("rx_info2.TAG=0x%x\n",
2003 + ei_local->rx_ring1[rx_dma_owner_idx0].
2004 + rxd_info2.TAG);
2005 +#if defined(CONFIG_ARCH_MT7623)
2006 + printk("rx_info2.LRO_AGG_CNT=0x%x\n",
2007 + ei_local->rx_ring1[rx_dma_owner_idx0].
2008 + rxd_info2.LRO_AGG_CNT);
2009 + printk("rx_info2.REV=0x%x\n",
2010 + ei_local->rx_ring1[rx_dma_owner_idx0].
2011 + rxd_info2.REV);
2012 +#else
2013 + printk("rx_info2.LS1=0x%x\n",
2014 + ei_local->rx_ring1[rx_dma_owner_idx0].
2015 + rxd_info2.LS1);
2016 +#endif /* CONFIG_RAETH_HW_LRO */
2017 + printk("rx_info2.PLEN1=0x%x\n",
2018 + ei_local->rx_ring1[rx_dma_owner_idx0].
2019 + rxd_info2.PLEN1);
2020 + printk("rx_info3.TPID=0x%x\n",
2021 + ei_local->rx_ring1[rx_dma_owner_idx0].
2022 + rxd_info3.TPID);
2023 + printk("rx_info3.VID=0x%x\n",
2024 + ei_local->rx_ring1[rx_dma_owner_idx0].
2025 + rxd_info3.VID);
2026 + printk("rx_info4.IP6=0x%x\n",
2027 + ei_local->rx_ring1[rx_dma_owner_idx0].
2028 + rxd_info4.IP6);
2029 + printk("rx_info4.IP4=0x%x\n",
2030 + ei_local->rx_ring1[rx_dma_owner_idx0].
2031 + rxd_info4.IP4);
2032 + printk("rx_info4.IP4F=0x%x\n",
2033 + ei_local->rx_ring1[rx_dma_owner_idx0].
2034 + rxd_info4.IP4F);
2035 + printk("rx_info4.TACK=0x%x\n",
2036 + ei_local->rx_ring1[rx_dma_owner_idx0].
2037 + rxd_info4.TACK);
2038 + printk("rx_info4.L4VLD=0x%x\n",
2039 + ei_local->rx_ring1[rx_dma_owner_idx0].
2040 + rxd_info4.L4VLD);
2041 + printk("rx_info4.L4F=0x%x\n",
2042 + ei_local->rx_ring1[rx_dma_owner_idx0].
2043 + rxd_info4.L4F);
2044 + printk("rx_info4.SPORT=0x%x\n",
2045 + ei_local->rx_ring1[rx_dma_owner_idx0].
2046 + rxd_info4.SP);
2047 + printk("rx_info4.CRSN=0x%x\n",
2048 + ei_local->rx_ring1[rx_dma_owner_idx0].
2049 + rxd_info4.CRSN);
2050 + printk("rx_info4.FOE_Entry=0x%x\n",
2051 + ei_local->rx_ring1[rx_dma_owner_idx0].
2052 + rxd_info4.FOE_Entry);
2053 + printk("-------------------------------\n");
2054 + } else if (rx_ring_no == 2) {
2055 + printk("------- rt2880_eth_recv (ring2) --------\n");
2056 + printk("rx_info1.PDP0=0x%x\n",
2057 + ei_local->rx_ring2[rx_dma_owner_idx0].
2058 + rxd_info1.PDP0);
2059 + printk("rx_info2.DDONE_bit=0x%x\n",
2060 + ei_local->rx_ring2[rx_dma_owner_idx0].
2061 + rxd_info2.DDONE_bit);
2062 + printk("rx_info2.LS0=0x%x\n",
2063 + ei_local->rx_ring2[rx_dma_owner_idx0].
2064 + rxd_info2.LS0);
2065 + printk("rx_info2.PLEN0=0x%x\n",
2066 + ei_local->rx_ring2[rx_dma_owner_idx0].
2067 + rxd_info2.PLEN0);
2068 + printk("rx_info2.TAG=0x%x\n",
2069 + ei_local->rx_ring2[rx_dma_owner_idx0].
2070 + rxd_info2.TAG);
2071 +#if defined(CONFIG_ARCH_MT7623)
2072 + printk("rx_info2.LRO_AGG_CNT=0x%x\n",
2073 + ei_local->rx_ring2[rx_dma_owner_idx0].
2074 + rxd_info2.LRO_AGG_CNT);
2075 + printk("rx_info2.REV=0x%x\n",
2076 + ei_local->rx_ring2[rx_dma_owner_idx0].
2077 + rxd_info2.REV);
2078 +#else
2079 + printk("rx_info2.LS1=0x%x\n",
2080 + ei_local->rx_ring2[rx_dma_owner_idx0].
2081 + rxd_info2.LS1);
2082 +#endif /* CONFIG_RAETH_HW_LRO */
2083 + printk("rx_info2.PLEN1=0x%x\n",
2084 + ei_local->rx_ring2[rx_dma_owner_idx0].
2085 + rxd_info2.PLEN1);
2086 + printk("rx_info3.TPID=0x%x\n",
2087 + ei_local->rx_ring2[rx_dma_owner_idx0].
2088 + rxd_info3.TPID);
2089 + printk("rx_info3.VID=0x%x\n",
2090 + ei_local->rx_ring2[rx_dma_owner_idx0].
2091 + rxd_info3.VID);
2092 + printk("rx_info4.IP6=0x%x\n",
2093 + ei_local->rx_ring2[rx_dma_owner_idx0].
2094 + rxd_info4.IP6);
2095 + printk("rx_info4.IP4=0x%x\n",
2096 + ei_local->rx_ring2[rx_dma_owner_idx0].
2097 + rxd_info4.IP4);
2098 + printk("rx_info4.IP4F=0x%x\n",
2099 + ei_local->rx_ring2[rx_dma_owner_idx0].
2100 + rxd_info4.IP4F);
2101 + printk("rx_info4.TACK=0x%x\n",
2102 + ei_local->rx_ring2[rx_dma_owner_idx0].
2103 + rxd_info4.TACK);
2104 + printk("rx_info4.L4VLD=0x%x\n",
2105 + ei_local->rx_ring2[rx_dma_owner_idx0].
2106 + rxd_info4.L4VLD);
2107 + printk("rx_info4.L4F=0x%x\n",
2108 + ei_local->rx_ring2[rx_dma_owner_idx0].
2109 + rxd_info4.L4F);
2110 + printk("rx_info4.SPORT=0x%x\n",
2111 + ei_local->rx_ring2[rx_dma_owner_idx0].
2112 + rxd_info4.SP);
2113 + printk("rx_info4.CRSN=0x%x\n",
2114 + ei_local->rx_ring2[rx_dma_owner_idx0].
2115 + rxd_info4.CRSN);
2116 + printk("rx_info4.FOE_Entry=0x%x\n",
2117 + ei_local->rx_ring2[rx_dma_owner_idx0].
2118 + rxd_info4.FOE_Entry);
2119 + printk("-------------------------------\n");
2120 + } else if (rx_ring_no == 3) {
2121 + printk("------- rt2880_eth_recv (ring3) --------\n");
2122 + printk("rx_info1.PDP0=0x%x\n",
2123 + ei_local->rx_ring3[rx_dma_owner_idx0].
2124 + rxd_info1.PDP0);
2125 + printk("rx_info2.DDONE_bit=0x%x\n",
2126 + ei_local->rx_ring3[rx_dma_owner_idx0].
2127 + rxd_info2.DDONE_bit);
2128 + printk("rx_info2.LS0=0x%x\n",
2129 + ei_local->rx_ring3[rx_dma_owner_idx0].
2130 + rxd_info2.LS0);
2131 + printk("rx_info2.PLEN0=0x%x\n",
2132 + ei_local->rx_ring3[rx_dma_owner_idx0].
2133 + rxd_info2.PLEN0);
2134 + printk("rx_info2.TAG=0x%x\n",
2135 + ei_local->rx_ring3[rx_dma_owner_idx0].
2136 + rxd_info2.TAG);
2137 +#if defined(CONFIG_ARCH_MT7623)
2138 + printk("rx_info2.LRO_AGG_CNT=0x%x\n",
2139 + ei_local->rx_ring3[rx_dma_owner_idx0].
2140 + rxd_info2.LRO_AGG_CNT);
2141 + printk("rx_info2.REV=0x%x\n",
2142 + ei_local->rx_ring3[rx_dma_owner_idx0].
2143 + rxd_info2.REV);
2144 +#else
2145 + printk("rx_info2.LS1=0x%x\n",
2146 + ei_local->rx_ring3[rx_dma_owner_idx0].
2147 + rxd_info2.LS1);
2148 +#endif /* CONFIG_RAETH_HW_LRO */
2149 + printk("rx_info2.PLEN1=0x%x\n",
2150 + ei_local->rx_ring3[rx_dma_owner_idx0].
2151 + rxd_info2.PLEN1);
2152 + printk("rx_info3.TPID=0x%x\n",
2153 + ei_local->rx_ring3[rx_dma_owner_idx0].
2154 + rxd_info3.TPID);
2155 + printk("rx_info3.VID=0x%x\n",
2156 + ei_local->rx_ring3[rx_dma_owner_idx0].
2157 + rxd_info3.VID);
2158 + printk("rx_info4.IP6=0x%x\n",
2159 + ei_local->rx_ring3[rx_dma_owner_idx0].
2160 + rxd_info4.IP6);
2161 + printk("rx_info4.IP4=0x%x\n",
2162 + ei_local->rx_ring3[rx_dma_owner_idx0].
2163 + rxd_info4.IP4);
2164 + printk("rx_info4.IP4F=0x%x\n",
2165 + ei_local->rx_ring3[rx_dma_owner_idx0].
2166 + rxd_info4.IP4F);
2167 + printk("rx_info4.TACK=0x%x\n",
2168 + ei_local->rx_ring3[rx_dma_owner_idx0].
2169 + rxd_info4.TACK);
2170 + printk("rx_info4.L4VLD=0x%x\n",
2171 + ei_local->rx_ring3[rx_dma_owner_idx0].
2172 + rxd_info4.L4VLD);
2173 + printk("rx_info4.L4F=0x%x\n",
2174 + ei_local->rx_ring3[rx_dma_owner_idx0].
2175 + rxd_info4.L4F);
2176 + printk("rx_info4.SPORT=0x%x\n",
2177 + ei_local->rx_ring3[rx_dma_owner_idx0].
2178 + rxd_info4.SP);
2179 + printk("rx_info4.CRSN=0x%x\n",
2180 + ei_local->rx_ring3[rx_dma_owner_idx0].
2181 + rxd_info4.CRSN);
2182 + printk("rx_info4.FOE_Entry=0x%x\n",
2183 + ei_local->rx_ring3[rx_dma_owner_idx0].
2184 + rxd_info4.FOE_Entry);
2185 + printk("-------------------------------\n");
2186 + }
2187 +#if 0
2188 + else {
2189 + printk("------- rt2880_eth_recv (ring0) --------\n");
2190 + printk("rx_info1.PDP0=0x%x\n",
2191 + ei_local->rx_ring0[rx_dma_owner_idx0].
2192 + rxd_info1.PDP0);
2193 + printk("rx_info2.DDONE_bit=0x%x\n",
2194 + ei_local->rx_ring0[rx_dma_owner_idx0].
2195 + rxd_info2.DDONE_bit);
2196 + printk("rx_info2.LS0=0x%x\n",
2197 + ei_local->rx_ring0[rx_dma_owner_idx0].
2198 + rxd_info2.LS0);
2199 + printk("rx_info2.PLEN0=0x%x\n",
2200 + ei_local->rx_ring0[rx_dma_owner_idx0].
2201 + rxd_info2.PLEN0);
2202 + printk("rx_info2.TAG=0x%x\n",
2203 + ei_local->rx_ring0[rx_dma_owner_idx0].
2204 + rxd_info2.TAG);
2205 + printk("rx_info2.LS1=0x%x\n",
2206 + ei_local->rx_ring0[rx_dma_owner_idx0].
2207 + rxd_info2.LS1);
2208 + printk("rx_info2.PLEN1=0x%x\n",
2209 + ei_local->rx_ring0[rx_dma_owner_idx0].
2210 + rxd_info2.PLEN1);
2211 + printk("rx_info3.TPID=0x%x\n",
2212 + ei_local->rx_ring0[rx_dma_owner_idx0].
2213 + rxd_info3.TPID);
2214 + printk("rx_info3.VID=0x%x\n",
2215 + ei_local->rx_ring0[rx_dma_owner_idx0].
2216 + rxd_info3.VID);
2217 + printk("rx_info4.IP6=0x%x\n",
2218 + ei_local->rx_ring0[rx_dma_owner_idx0].
2219 + rxd_info4.IP6);
2220 + printk("rx_info4.IP4=0x%x\n",
2221 + ei_local->rx_ring0[rx_dma_owner_idx0].
2222 + rxd_info4.IP4);
2223 + printk("rx_info4.IP4F=0x%x\n",
2224 + ei_local->rx_ring0[rx_dma_owner_idx0].
2225 + rxd_info4.IP4F);
2226 + printk("rx_info4.TACK=0x%x\n",
2227 + ei_local->rx_ring0[rx_dma_owner_idx0].
2228 + rxd_info4.TACK);
2229 + printk("rx_info4.L4VLD=0x%x\n",
2230 + ei_local->rx_ring0[rx_dma_owner_idx0].
2231 + rxd_info4.L4VLD);
2232 + printk("rx_info4.L4F=0x%x\n",
2233 + ei_local->rx_ring0[rx_dma_owner_idx0].
2234 + rxd_info4.L4F);
2235 + printk("rx_info4.SPORT=0x%x\n",
2236 + ei_local->rx_ring0[rx_dma_owner_idx0].
2237 + rxd_info4.SP);
2238 + printk("rx_info4.CRSN=0x%x\n",
2239 + ei_local->rx_ring0[rx_dma_owner_idx0].
2240 + rxd_info4.CRSN);
2241 + printk("rx_info4.FOE_Entry=0x%x\n",
2242 + ei_local->rx_ring0[rx_dma_owner_idx0].
2243 + rxd_info4.FOE_Entry);
2244 + printk("-------------------------------\n");
2245 + }
2246 +#endif
2247 + }
2248 + if (pdma_dvt_get_lro_test_config() == PDMA_TEST_LRO_FORCE_AGGREGATE) {
2249 + if (rx_ring_no == 1) {
2250 + printk("PASS!!! => RING1: rxd_info1.PDP0=0x%x\n",
2251 + ei_local->rx_ring1[rx_dma_owner_idx0].
2252 + rxd_info1.PDP0);
2253 + skb_dump(ei_local->netrx1_skbuf[rx_dma_owner_idx0]);
2254 + pdma_dvt_reset_config();
2255 + }
2256 + }
2257 +}
2258 +#endif
2259 +
2260 +int pdma_dvt_show_ctrl(int par1, int par2)
2261 +{
2262 + if (par2 == 0)
2263 + g_pdma_dvt_show_config = 0;
2264 + else
2265 + g_pdma_dvt_show_config |= (1 << par2);
2266 +
2267 + return 0;
2268 +}
2269 +
2270 +int pdma_dvt_test_rx_ctrl(int par1, int par2)
2271 +{
2272 + if (par2 == 0)
2273 + g_pdma_dvt_rx_test_config = 0;
2274 + else
2275 + g_pdma_dvt_rx_test_config |= (1 << par2);
2276 +
2277 + return 0;
2278 +}
2279 +
2280 +int pdma_dvt_test_tx_ctrl(int par1, int par2)
2281 +{
2282 + if (par2 == 0)
2283 + g_pdma_dvt_tx_test_config = 0;
2284 + else
2285 + g_pdma_dvt_tx_test_config |= (1 << par2);
2286 +
2287 + return 0;
2288 +}
2289 +
2290 +int pdma_dvt_test_debug_ctrl(int par1, int par2)
2291 +{
2292 + if (par2 == 0)
2293 + g_pdma_dvt_debug_test_config = 0;
2294 + else
2295 + g_pdma_dvt_debug_test_config |= (1 << par2);
2296 +
2297 + return 0;
2298 +}
2299 +
2300 +int pdma_dvt_test_lro_ctrl(int par1, int par2)
2301 +{
2302 + g_pdma_dvt_lro_test_config = par2;
2303 +
2304 +#if defined(CONFIG_RAETH_HW_LRO) || defined(CONFIG_RAETH_MULTIPLE_RX_RING)
2305 + if (pdma_dvt_lro_func[par2])
2306 + (*pdma_dvt_lro_func[par2]) ();
2307 +#endif /* #if defined (CONFIG_RAETH_HW_LRO) */
2308 +
2309 + return 0;
2310 +}
2311 +
2312 +unsigned int pdma_dvt_get_show_config()
2313 +{
2314 + return g_pdma_dvt_show_config;
2315 +}
2316 +
2317 +unsigned int pdma_dvt_get_rx_test_config()
2318 +{
2319 + return g_pdma_dvt_rx_test_config;
2320 +}
2321 +
2322 +unsigned int pdma_dvt_get_tx_test_config()
2323 +{
2324 + return g_pdma_dvt_tx_test_config;
2325 +}
2326 +
2327 +unsigned int pdma_dvt_get_debug_test_config()
2328 +{
2329 + return g_pdma_dvt_debug_test_config;
2330 +}
2331 +
2332 +unsigned int pdma_dvt_get_lro_test_config()
2333 +{
2334 + return g_pdma_dvt_lro_test_config;
2335 +}
2336 +
2337 +void pdma_dvt_reset_config()
2338 +{
2339 + g_pdma_dvt_show_config = 0;
2340 + g_pdma_dvt_rx_test_config = 0;
2341 + g_pdma_dvt_tx_test_config = 0;
2342 + g_pdma_dvt_lro_test_config = 0;
2343 +}
2344 +
2345 +void raeth_pdma_rx_desc_dvt(END_DEVICE *ei_local, int rx_dma_owner_idx0)
2346 +{
2347 +#if 0
2348 + unsigned int udf = 0;
2349 +#endif
2350 +
2351 + if (pdma_dvt_get_show_config() & PDMA_SHOW_RX_DESC) {
2352 + printk("------- rt2880_eth_recv --------\n");
2353 + printk("rx_info1=0x%x\n",
2354 + *(unsigned int *)&ei_local->
2355 + rx_ring0[rx_dma_owner_idx0].rxd_info1);
2356 + printk("rx_info2=0x%x\n",
2357 + *(unsigned int *)&ei_local->
2358 + rx_ring0[rx_dma_owner_idx0].rxd_info2);
2359 + printk("rx_info3=0x%x\n",
2360 + *(unsigned int *)&ei_local->
2361 + rx_ring0[rx_dma_owner_idx0].rxd_info3);
2362 + printk("rx_info4=0x%x\n",
2363 + *(unsigned int *)&ei_local->
2364 + rx_ring0[rx_dma_owner_idx0].rxd_info4);
2365 + printk("-------------------------------\n");
2366 + }
2367 + if ((pdma_dvt_get_show_config() & PDMA_SHOW_DETAIL_RX_DESC) ||
2368 + pdma_dvt_get_rx_test_config()) {
2369 +#if 0
2370 + udf = ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.IP6 << 5 |
2371 + ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.IP4 << 4 |
2372 + ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.IP4F << 3 |
2373 + ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.TACK << 2 |
2374 + ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.L4VLD << 1 |
2375 + ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.L4F;
2376 +#endif
2377 + printk("------- rt2880_eth_recv --------\n");
2378 + printk("rx_info1.PDP0=0x%x\n",
2379 + ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info1.PDP0);
2380 + printk("rx_info2.DDONE_bit=0x%x\n",
2381 + ei_local->rx_ring0[rx_dma_owner_idx0].
2382 + rxd_info2.DDONE_bit);
2383 + printk("rx_info2.LS0=0x%x\n",
2384 + ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info2.LS0);
2385 + printk("rx_info2.PLEN0=0x%x\n",
2386 + ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info2.PLEN0);
2387 + printk("rx_info2.TAG=0x%x\n",
2388 + ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info2.TAG);
2389 +#if defined(CONFIG_ARCH_MT7623)
2390 + printk("rx_info2.LRO_AGG_CNT=0x%x\n",
2391 + ei_local->rx_ring0[rx_dma_owner_idx0].
2392 + rxd_info2.LRO_AGG_CNT);
2393 +#else
2394 + printk("rx_info2.LS1=0x%x\n",
2395 + ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info2.LS1);
2396 +#endif /* CONFIG_RAETH_HW_LRO */
2397 + printk("rx_info2.PLEN1=0x%x\n",
2398 + ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info2.PLEN1);
2399 + printk("rx_info3.TPID=0x%x\n",
2400 + ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info3.TPID);
2401 + printk("rx_info3.VID=0x%x\n",
2402 + ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info3.VID);
2403 +#if 0
2404 + printk("rx_info4.UDF=0x%x\n", udf);
2405 +#endif
2406 + printk("rx_info4.IP6=0x%x\n",
2407 + ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.IP6);
2408 + printk("rx_info4.IP4=0x%x\n",
2409 + ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.IP4);
2410 + printk("rx_info4.IP4F=0x%x\n",
2411 + ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.IP4F);
2412 + printk("rx_info4.TACK=0x%x\n",
2413 + ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.TACK);
2414 + printk("rx_info4.L4VLD=0x%x\n",
2415 + ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.L4VLD);
2416 + printk("rx_info4.L4F=0x%x\n",
2417 + ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.L4F);
2418 + printk("rx_info4.SPORT=0x%x\n",
2419 + ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.SP);
2420 + printk("rx_info4.CRSN=0x%x\n",
2421 + ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.CRSN);
2422 + printk("rx_info4.FOE_Entry=0x%x\n",
2423 + ei_local->rx_ring0[rx_dma_owner_idx0].
2424 + rxd_info4.FOE_Entry);
2425 + printk("-------------------------------\n");
2426 + }
2427 + if ((pdma_dvt_get_rx_test_config() & PDMA_TEST_RX_IPV6)) {
2428 + if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.IP6) {
2429 + printk("PASS!!! => rx_info4.IP6=0x%x\n",
2430 + ei_local->rx_ring0[rx_dma_owner_idx0].
2431 + rxd_info4.IP6);
2432 + pdma_dvt_reset_config();
2433 + }
2434 + } else if ((pdma_dvt_get_rx_test_config() & PDMA_TEST_RX_IPV4)) {
2435 + if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.IP4) {
2436 + printk("PASS!!! => rx_info4.IP4=0x%x\n",
2437 + ei_local->rx_ring0[rx_dma_owner_idx0].
2438 + rxd_info4.IP4);
2439 + pdma_dvt_reset_config();
2440 + }
2441 + } else if ((pdma_dvt_get_rx_test_config() & PDMA_TEST_RX_IPV4F)) {
2442 + if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.IP4F) {
2443 + printk("PASS!!! => rx_info4.IP4F=0x%x\n",
2444 + ei_local->rx_ring0[rx_dma_owner_idx0].
2445 + rxd_info4.IP4F);
2446 + pdma_dvt_reset_config();
2447 + }
2448 + } else if ((pdma_dvt_get_rx_test_config() & PDMA_TEST_RX_L4VLD)) {
2449 + if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.L4VLD) {
2450 + printk("PASS!!! => rx_info4.L4VLD=0x%x\n",
2451 + ei_local->rx_ring0[rx_dma_owner_idx0].
2452 + rxd_info4.L4VLD);
2453 + pdma_dvt_reset_config();
2454 + }
2455 + } else if ((pdma_dvt_get_rx_test_config() & PDMA_TEST_RX_L4F)) {
2456 + if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.L4F) {
2457 + printk("PASS!!! => rx_info4.L4F=0x%x\n",
2458 + ei_local->rx_ring0[rx_dma_owner_idx0].
2459 + rxd_info4.L4F);
2460 + pdma_dvt_reset_config();
2461 + }
2462 + } else if ((pdma_dvt_get_rx_test_config() & PDMA_TEST_RX_SPORT)) {
2463 + if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.SP == 1) {
2464 + g_pdma_dev_lanport++;
2465 + } else if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.SP ==
2466 + 2) {
2467 + g_pdma_dev_wanport++;
2468 + }
2469 + if (g_pdma_dev_lanport && g_pdma_dev_wanport) {
2470 + printk
2471 + ("PASS!!! => g_pdma_dev_lanport=0x%x, g_pdma_dev_wanport=0x%x",
2472 + g_pdma_dev_lanport, g_pdma_dev_wanport);
2473 +
2474 + g_pdma_dev_lanport = 0;
2475 + g_pdma_dev_wanport = 0;
2476 + pdma_dvt_reset_config();
2477 + }
2478 + } else if ((pdma_dvt_get_rx_test_config() & PDMA_TEST_RX_VID_OFF)) {
2479 + if (!ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info3.VID) {
2480 + printk("PASS!!! => rxd_info3.VID=0x%x\n",
2481 + ei_local->rx_ring0[rx_dma_owner_idx0].
2482 + rxd_info3.VID);
2483 + pdma_dvt_reset_config();
2484 + }
2485 + } else if ((pdma_dvt_get_rx_test_config() & PDMA_TEST_RX_VID_ON)) {
2486 + printk("RX data: (PDP0=%x)\n",
2487 + (unsigned int)ei_local->
2488 + netrx0_skbuf[rx_dma_owner_idx0]->data);
2489 +
2490 + skb_dump(ei_local->netrx0_skbuf[rx_dma_owner_idx0]);
2491 +
2492 + if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info3.VID &&
2493 + ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info2.TAG) {
2494 + printk("PASS!!! => rxd_info2.TAG=0x%x\n",
2495 + ei_local->rx_ring0[rx_dma_owner_idx0].
2496 + rxd_info2.TAG);
2497 + printk("PASS!!! => rxd_info3.VID=0x%x\n",
2498 + ei_local->rx_ring0[rx_dma_owner_idx0].
2499 + rxd_info3.VID);
2500 + pdma_dvt_reset_config();
2501 + }
2502 + }
2503 +}
2504 +
2505 +void raeth_pdma_tx_vlan_dvt(END_DEVICE *ei_local,
2506 + unsigned long tx_cpu_owner_idx0)
2507 +{
2508 + if ((pdma_dvt_get_tx_test_config() & PDMA_TEST_TX_VLAN_ON)) {
2509 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.VLAN_TAG = 0x10000 | 0xE007; /* VLAN_TAG = 0x1E007 */
2510 + } else if ((pdma_dvt_get_tx_test_config() & PDMA_TEST_TX_VLAN_ZERO)) {
2511 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.VLAN_TAG = 0x10000 | 0x0000; /* VLAN_TAG = 0x10000 */
2512 + } else if ((pdma_dvt_get_tx_test_config() & PDMA_TEST_TX_VLAN_MAX)) {
2513 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.VLAN_TAG = 0x10000 | 0xFFFF; /* VLAN_TAG = 0x1FFFF */
2514 + }
2515 +}
2516 +
2517 +void raeth_pdma_tx_desc_dvt(END_DEVICE *ei_local,
2518 + unsigned long tx_cpu_owner_idx0)
2519 +{
2520 + if (PDMA_TEST_RX_UDF == pdma_dvt_get_rx_test_config()) {
2521 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FPORT = 4; /* PPE */
2522 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.UDF = 0x2F;
2523 + }
2524 + if (pdma_dvt_get_show_config() & PDMA_SHOW_TX_DESC) {
2525 + printk("------- rt2880_eth_send --------\n");
2526 + printk("tx_info1=%x\n",
2527 + *(unsigned int *)&ei_local->
2528 + tx_ring0[tx_cpu_owner_idx0].txd_info1);
2529 + printk("tx_info2=%x\n",
2530 + *(unsigned int *)&ei_local->
2531 + tx_ring0[tx_cpu_owner_idx0].txd_info2);
2532 + printk("tx_info3=%x\n",
2533 + *(unsigned int *)&ei_local->
2534 + tx_ring0[tx_cpu_owner_idx0].txd_info3);
2535 + printk("tx_info4=%x\n",
2536 + *(unsigned int *)&ei_local->
2537 + tx_ring0[tx_cpu_owner_idx0].txd_info4);
2538 + printk("--------------------------------\n");
2539 + }
2540 + if ((pdma_dvt_get_show_config() & PDMA_SHOW_DETAIL_TX_DESC) ||
2541 + pdma_dvt_get_tx_test_config()) {
2542 + printk("------- rt2880_eth_send --------\n");
2543 + printk("tx_info1.SDP0=%x\n",
2544 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info1.SDP0);
2545 + printk("tx_info2.DDONE_bit=%x\n",
2546 + ei_local->tx_ring0[tx_cpu_owner_idx0].
2547 + txd_info2.DDONE_bit);
2548 + printk("tx_info2.LS0_bit=%x\n",
2549 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.LS0_bit);
2550 + printk("tx_info2.SDL0=%x\n",
2551 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.SDL0);
2552 + printk("tx_info2.BURST_bit=%x\n",
2553 + ei_local->tx_ring0[tx_cpu_owner_idx0].
2554 + txd_info2.BURST_bit);
2555 + printk("tx_info2.LS1_bit=%x\n",
2556 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.LS1_bit);
2557 + printk("tx_info2.SDL1=%x\n",
2558 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.SDL1);
2559 + printk("tx_info3.SDP1=%x\n",
2560 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info3.SDP1);
2561 + printk("tx_info4.TUI_CO=%x\n",
2562 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.TUI_CO);
2563 + printk("tx_info4.TSO=%x\n",
2564 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.TSO);
2565 + printk("tx_info4.FPORT=%x\n",
2566 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FPORT);
2567 + printk("tx_info4.UDF=%x\n",
2568 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.UDF);
2569 + printk("tx_info4.RESV=%x\n",
2570 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.RESV);
2571 + printk("tx_info4.VLAN_TAG=%x\n",
2572 + ei_local->tx_ring0[tx_cpu_owner_idx0].
2573 + txd_info4.VLAN_TAG);
2574 + printk("--------------------------------\n");
2575 + }
2576 + if ((pdma_dvt_get_tx_test_config() & PDMA_TEST_TX_LAN_SPORT)) {
2577 + if (ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FPORT == 1) {
2578 + printk("PASS!!! => txd_info4.FPORT=0x%x\n",
2579 + ei_local->tx_ring0[tx_cpu_owner_idx0].
2580 + txd_info4.FPORT);
2581 + pdma_dvt_reset_config();
2582 + }
2583 + } else if ((pdma_dvt_get_tx_test_config() & PDMA_TEST_TX_WAN_SPORT)) {
2584 + if (ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FPORT == 2) {
2585 + printk("PASS!!! => txd_info4.FPORT=0x%x\n",
2586 + ei_local->tx_ring0[tx_cpu_owner_idx0].
2587 + txd_info4.FPORT);
2588 + pdma_dvt_reset_config();
2589 + }
2590 + } else if ((pdma_dvt_get_tx_test_config() & PDMA_TEST_TX_VLAN_ON)) {
2591 + if (ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.VLAN_TAG) {
2592 + printk("PASS!!! => txd_info4.VLAN_TAG=0x%x\n",
2593 + ei_local->tx_ring0[tx_cpu_owner_idx0].
2594 + txd_info4.VLAN_TAG);
2595 + /* pdma_dvt_reset_config(); */
2596 + }
2597 + } else if ((pdma_dvt_get_tx_test_config() & PDMA_TEST_TX_VLAN_OFF)) {
2598 + if (!ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.VLAN_TAG) {
2599 + printk("PASS!!! => txd_info4.VLAN_TAG=0x%x\n",
2600 + ei_local->tx_ring0[tx_cpu_owner_idx0].
2601 + txd_info4.VLAN_TAG);
2602 + pdma_dvt_reset_config();
2603 + }
2604 + } else if ((pdma_dvt_get_tx_test_config() & PDMA_TEST_TX_VLAN_ZERO)) {
2605 + if (ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.VLAN_TAG) {
2606 + printk("PASS!!! => txd_info4.VLAN_TAG=0x%x\n",
2607 + ei_local->tx_ring0[tx_cpu_owner_idx0].
2608 + txd_info4.VLAN_TAG);
2609 + /* pdma_dvt_reset_config(); */
2610 + }
2611 + } else if ((pdma_dvt_get_tx_test_config() & PDMA_TEST_TX_VLAN_MAX)) {
2612 + if (ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.VLAN_TAG) {
2613 + printk("PASS!!! => txd_info4.VLAN_TAG=0x%x\n",
2614 + ei_local->tx_ring0[tx_cpu_owner_idx0].
2615 + txd_info4.VLAN_TAG);
2616 + /* pdma_dvt_reset_config(); */
2617 + }
2618 + }
2619 +}
2620 +
2621 +void raeth_pdma_lro_dly_int_dvt(void)
2622 +{
2623 + unsigned int reg_int_val;
2624 +
2625 + reg_int_val = sysRegRead(RAETH_FE_INT_STATUS);
2626 +
2627 + if (pdma_dvt_get_lro_test_config() == PDMA_TEST_LRO_DLY_INT0) {
2628 + if ((reg_int_val & RX_DLY_INT)) {
2629 + printk("PASS!!! => reg_int_val=0x%x\n", reg_int_val);
2630 + pdma_dvt_reset_config();
2631 + }
2632 + } else if (pdma_dvt_get_lro_test_config() == PDMA_TEST_LRO_DLY_INT1) {
2633 + if ((reg_int_val & RING1_RX_DLY_INT)) {
2634 + printk("PASS!!! => reg_int_val=0x%x\n", reg_int_val);
2635 + pdma_dvt_reset_config();
2636 + }
2637 + } else if (pdma_dvt_get_lro_test_config() == PDMA_TEST_LRO_DLY_INT2) {
2638 + if ((reg_int_val & RING2_RX_DLY_INT)) {
2639 + printk("PASS!!! => reg_int_val=0x%x\n", reg_int_val);
2640 + pdma_dvt_reset_config();
2641 + }
2642 + } else if (pdma_dvt_get_lro_test_config() == PDMA_TEST_LRO_DLY_INT3) {
2643 + if ((reg_int_val & RING3_RX_DLY_INT)) {
2644 + printk("PASS!!! => reg_int_val=0x%x\n", reg_int_val);
2645 + pdma_dvt_reset_config();
2646 + }
2647 + }
2648 +}
2649 +
2650 +void pdma_dvt_set_dma_mode(void)
2651 +{
2652 +#if defined(CONFIG_RAETH_PDMA_LEGACY_MODE)
2653 + unsigned int regVal;
2654 + regVal = sysRegRead(ADMA_LRO_CTRL_DW3);
2655 + regVal &= ~(BIT(15));
2656 + sysRegWrite(ADMA_LRO_CTRL_DW3, regVal);
2657 +#endif /* CONFIG_RAETH_PDMA_DVT */
2658 +}
2659 +
2660 diff --git a/drivers/net/ethernet/raeth/dvt/raether_pdma_dvt.h b/drivers/net/ethernet/raeth/dvt/raether_pdma_dvt.h
2661 new file mode 100755
2662 index 0000000..600aab7
2663 --- /dev/null
2664 +++ b/drivers/net/ethernet/raeth/dvt/raether_pdma_dvt.h
2665 @@ -0,0 +1,75 @@
2666 +/* Show controls */
2667 +#define PDMA_SHOW_RX_DESC (1 << 1)
2668 +#define PDMA_SHOW_TX_DESC (1 << 2)
2669 +#define PDMA_SHOW_DETAIL_RX_DESC (1 << 3)
2670 +#define PDMA_SHOW_DETAIL_TX_DESC (1 << 4)
2671 +
2672 +/* Rx test controls */
2673 +#define PDMA_TEST_RX_UDF (1 << 1)
2674 +#define PDMA_TEST_RX_IPV6 (1 << 2)
2675 +#define PDMA_TEST_RX_IPV4 (1 << 3)
2676 +#define PDMA_TEST_RX_IPV4F (1 << 4)
2677 +#define PDMA_TEST_RX_L4VLD (1 << 5)
2678 +#define PDMA_TEST_RX_L4F (1 << 6)
2679 +#define PDMA_TEST_RX_SPORT (1 << 7)
2680 +#define PDMA_TEST_RX_VID_ON (1 << 8)
2681 +#define PDMA_TEST_RX_VID_OFF (1 << 9)
2682 +
2683 +/* Tx test controls */
2684 +#define PDMA_TEST_TX_LAN_SPORT (1 << 1)
2685 +#define PDMA_TEST_TX_WAN_SPORT (1 << 2)
2686 +#define PDMA_TEST_TX_VLAN_ON (1 << 3)
2687 +#define PDMA_TEST_TX_VLAN_OFF (1 << 4)
2688 +#define PDMA_TEST_TX_VLAN_ZERO (1 << 5)
2689 +#define PDMA_TEST_TX_VLAN_MAX (1 << 6)
2690 +#define PDMA_TEST_TX_PDMA_LPK (1 << 31)
2691 +
2692 +/* Debug controls */
2693 +#define PDMA_TEST_TSO_DEBUG (1 << 1)
2694 +
2695 +/* LRO test controls */
2696 +typedef int (*PDMA_LRO_DVT_FUNC) (void);
2697 +
2698 +#define PDMA_TEST_LRO_DISABLE (0)
2699 +#define PDMA_TEST_LRO_FORCE_PORT (1)
2700 +#define PDMA_TEST_LRO_AUTO_LEARN (2)
2701 +#define PDMA_TEST_LRO_AUTO_IPV6 (3)
2702 +#define PDMA_TEST_LRO_AUTO_MYIP (4)
2703 +#define PDMA_TEST_LRO_FORCE_AGGREGATE (5)
2704 +#define PDMA_TEST_NON_LRO_PORT_ID (6)
2705 +#define PDMA_TEST_NON_LRO_STAG (7)
2706 +#define PDMA_TEST_NON_LRO_VLAN (8)
2707 +#define PDMA_TEST_NON_LRO_TCP_ACK (9)
2708 +#define PDMA_TEST_NON_LRO_PRI1 (10)
2709 +#define PDMA_TEST_NON_LRO_PRI2 (11)
2710 +#define PDMA_TEST_LRO_DLY_INT0 (12)
2711 +#define PDMA_TEST_LRO_DLY_INT1 (13)
2712 +#define PDMA_TEST_LRO_DLY_INT2 (14)
2713 +#define PDMA_TEST_LRO_DLY_INT3 (15)
2714 +
2715 +void skb_dump(struct sk_buff *sk);
2716 +
2717 +int pdma_dvt_show_ctrl(int par1, int par2);
2718 +int pdma_dvt_test_rx_ctrl(int par1, int par2);
2719 +int pdma_dvt_test_tx_ctrl(int par1, int par2);
2720 +int pdma_dvt_test_debug_ctrl(int par1, int par2);
2721 +int pdma_dvt_test_lro_ctrl(int par1, int par2);
2722 +
2723 +unsigned int pdma_dvt_get_show_config(void);
2724 +unsigned int pdma_dvt_get_rx_test_config(void);
2725 +unsigned int pdma_dvt_get_tx_test_config(void);
2726 +unsigned int pdma_dvt_get_debug_test_config(void);
2727 +unsigned int pdma_dvt_get_lro_test_config(void);
2728 +void pdma_dvt_reset_config(void);
2729 +
2730 +void raeth_pdma_rx_desc_dvt(END_DEVICE *ei_local, int rx_dma_owner_idx0);
2731 +void raeth_pdma_tx_vlan_dvt(END_DEVICE *ei_local,
2732 + unsigned long tx_cpu_owner_idx0);
2733 +void raeth_pdma_tx_desc_dvt(END_DEVICE *ei_local,
2734 + unsigned long tx_cpu_owner_idx0);
2735 +
2736 +void raeth_pdma_lro_dvt(int rx_ring_no, END_DEVICE *ei_local,
2737 + int rx_dma_owner_idx0);
2738 +void raeth_pdma_lro_dly_int_dvt(void);
2739 +void pdma_dvt_set_dma_mode(void);
2740 +
2741 diff --git a/drivers/net/ethernet/raeth/ethtool_readme.txt b/drivers/net/ethernet/raeth/ethtool_readme.txt
2742 new file mode 100644
2743 index 0000000..10e918b
2744 --- /dev/null
2745 +++ b/drivers/net/ethernet/raeth/ethtool_readme.txt
2746 @@ -0,0 +1,44 @@
2747 +
2748 +Ethtool readme for selecting different PHY address.
2749 +
2750 +Before doing any ethtool command you should make sure the current PHY
2751 +address is expected. The default PHY address is 1(port 1).
2752 +
2753 +You can change current PHY address to X(0~4) by doing follow command:
2754 +# echo X > /proc/rt2880/gmac
2755 +
2756 +Ethtool command also would show the current PHY address as following.
2757 +
2758 +# ethtool eth2
2759 +Settings for eth2:
2760 + Supported ports: [ TP MII ]
2761 + Supported link modes: 10baseT/Half 10baseT/Full
2762 + 100baseT/Half 100baseT/Full
2763 + Supports auto-negotiation: Yes
2764 + Advertised link modes: 10baseT/Half 10baseT/Full
2765 + 100baseT/Half 100baseT/Full
2766 + Advertised auto-negotiation: No
2767 + Speed: 10Mb/s
2768 + Duplex: Full
2769 + Port: MII
2770 + PHYAD: 1
2771 + Transceiver: internal
2772 + Auto-negotiation: off
2773 + Current message level: 0x00000000 (0)
2774 + Link detected: no
2775 +
2776 +
2777 +The "PHYAD" field shows the current PHY address.
2778 +
2779 +
2780 +
2781 +Usage example
2782 +1) show port1 info
2783 +# echo 1 > /proc/rt2880/gmac # change phy address to 1
2784 +# ethtool eth2
2785 +
2786 +2) show port0 info
2787 +# echo 0 > /proc/rt2880/gmac # change phy address to 0
2788 +# ethtool eth2
2789 +
2790 +
2791 diff --git a/drivers/net/ethernet/raeth/mcast.c b/drivers/net/ethernet/raeth/mcast.c
2792 new file mode 100644
2793 index 0000000..d796b03
2794 --- /dev/null
2795 +++ b/drivers/net/ethernet/raeth/mcast.c
2796 @@ -0,0 +1,187 @@
2797 +#include <linux/config.h>
2798 +#include <linux/version.h>
2799 +#include <linux/module.h>
2800 +#include <linux/skbuff.h>
2801 +#include <linux/kernel.h>
2802 +#include <linux/init.h>
2803 +#include <linux/types.h>
2804 +#include <linux/netdevice.h>
2805 +#include <linux/if_vlan.h>
2806 +
2807 +
2808 +#define MAX_MCAST_ENTRY 16
2809 +#define AGEING_TIME 5 //Unit: Sec
2810 +#define MAC_ARG(x) ((u8*)(x))[0],((u8*)(x))[1],((u8*)(x))[2], \
2811 + ((u8*)(x))[3],((u8*)(x))[4],((u8*)(x))[5]
2812 +
2813 +//#define MCAST_DEBUG
2814 +#ifdef MCAST_DEBUG
2815 +#define MCAST_PRINT(fmt, args...) printk(KERN_INFO fmt, ## args)
2816 +#else
2817 +#define MCAST_PRINT(fmt, args...) { }
2818 +#endif
2819 +
2820 +typedef struct {
2821 + uint8_t src_mac[6];
2822 + uint8_t dst_mac[6];
2823 + uint16_t vlan_id;
2824 + uint32_t valid;
2825 + uint32_t use_count;
2826 + unsigned long ageout;
2827 +} mcast_entry;
2828 +
2829 +mcast_entry mcast_tbl[MAX_MCAST_ENTRY];
2830 +atomic_t mcast_entry_num=ATOMIC_INIT(0);
2831 +DECLARE_MUTEX(mtbl_lock);
2832 +
2833 +uint32_t inline is_multicast_pkt(uint8_t *mac)
2834 +{
2835 + if(mac[0]==0x01 && mac[1]==0x00 && mac[2]==0x5E) {
2836 + return 1;
2837 + }else{
2838 + return 0;
2839 + }
2840 +}
2841 +
2842 +int32_t inline mcast_entry_get(uint16_t vlan_id, uint8_t *src_mac, uint8_t *dst_mac)
2843 +{
2844 + int i=0;
2845 +
2846 + for(i=0;i<MAX_MCAST_ENTRY;i++) {
2847 + if( (mcast_tbl[i].vlan_id == vlan_id) &&
2848 + memcmp(mcast_tbl[i].src_mac,src_mac, 6)==0 &&
2849 + memcmp(mcast_tbl[i].dst_mac, dst_mac, 6)==0 &&
2850 + mcast_tbl[i].valid == 1) {
2851 + return i;
2852 + }
2853 + }
2854 + return -1;
2855 +}
2856 +
2857 +int inline __add_mcast_entry(uint16_t vlan_id, uint8_t *src_mac, uint8_t *dst_mac)
2858 +{
2859 + int i=0;
2860 +
2861 + // use empty or ageout entry
2862 + for(i=0;i<MAX_MCAST_ENTRY;i++) {
2863 + if( mcast_tbl[i].valid==0 ||
2864 + time_after(jiffies, mcast_tbl[i].ageout)) {
2865 +
2866 + if(mcast_tbl[i].valid==0) {
2867 + atomic_inc(&mcast_entry_num);
2868 + }
2869 + mcast_tbl[i].vlan_id = vlan_id;
2870 + memcpy(mcast_tbl[i].src_mac, src_mac, 6);
2871 + memcpy(mcast_tbl[i].dst_mac, dst_mac, 6);
2872 + mcast_tbl[i].valid=1;
2873 + mcast_tbl[i].use_count=1;
2874 + mcast_tbl[i].ageout=jiffies + AGEING_TIME * HZ;
2875 +
2876 + return 1;
2877 + }
2878 + }
2879 +
2880 + MCAST_PRINT("RAETH: Multicast Table is FULL!!\n");
2881 + return 0;
2882 +}
2883 +
2884 +int inline mcast_entry_ins(uint16_t vlan_id, uint8_t *src_mac, uint8_t *dst_mac)
2885 +{
2886 + int entry_num=0, ret=0;
2887 +
2888 + down(&mtbl_lock);
2889 + if((entry_num = mcast_entry_get(vlan_id, src_mac, dst_mac)) >=0) {
2890 + mcast_tbl[entry_num].use_count++;
2891 + mcast_tbl[entry_num].ageout=jiffies + AGEING_TIME * HZ;
2892 + MCAST_PRINT("%s: Update %0X:%0X:%0X:%0X:%0X:%0X's use_count=%d\n" \
2893 + ,__FUNCTION__, MAC_ARG(dst_mac), mcast_tbl[entry_num].use_count);
2894 + ret = 1;
2895 + }else { //if entry not found, create new entry.
2896 + MCAST_PRINT("%s: Create new entry %0X:%0X:%0X:%0X:%0X:%0X\n", \
2897 + __FUNCTION__, MAC_ARG(dst_mac));
2898 + ret = __add_mcast_entry(vlan_id, src_mac,dst_mac);
2899 + }
2900 +
2901 + up(&mtbl_lock);
2902 + return ret;
2903 +
2904 +}
2905 +
2906 +
2907 +/*
2908 + * Return:
2909 + * 0: entry found
2910 + * 1: entry not found
2911 + */
2912 +int inline mcast_entry_del(uint16_t vlan_id, uint8_t *src_mac, uint8_t *dst_mac)
2913 +{
2914 + int entry_num;
2915 +
2916 + down(&mtbl_lock);
2917 + if((entry_num = mcast_entry_get(vlan_id, src_mac, dst_mac)) >=0) {
2918 + if((--mcast_tbl[entry_num].use_count)==0) {
2919 + MCAST_PRINT("%s: %0X:%0X:%0X:%0X:%0X:%0X (entry_num=%d)\n", \
2920 + __FUNCTION__, MAC_ARG(dst_mac), entry_num);
2921 + mcast_tbl[entry_num].valid=0;
2922 + atomic_dec(&mcast_entry_num);
2923 + }
2924 + up(&mtbl_lock);
2925 + return 0;
2926 + }else {
2927 + /* this multicast packet was not sent by meself, just ignore it */
2928 + up(&mtbl_lock);
2929 + return 1;
2930 + }
2931 +}
2932 +
2933 +/*
2934 + * Return
2935 + * 0: drop packet
2936 + * 1: continue
2937 + */
2938 +int32_t mcast_rx(struct sk_buff * skb)
2939 +{
2940 + struct vlan_ethhdr *eth = (struct vlan_ethhdr *)(skb->data-ETH_HLEN);
2941 +
2942 + /* if we do not send multicast packet before,
2943 + * we don't need to check re-inject multicast packet.
2944 + */
2945 + if (atomic_read(&mcast_entry_num)==0) {
2946 + return 1;
2947 + }
2948 +
2949 +
2950 + if(is_multicast_pkt(eth->h_dest)) {
2951 + MCAST_PRINT("%s: %0X:%0X:%0X:%0X:%0X:%0X\n", __FUNCTION__, \
2952 + MAC_ARG(eth->h_dest));
2953 +
2954 + if(ntohs(eth->h_vlan_proto)==0x8100) {
2955 + return mcast_entry_del(eth->h_vlan_TCI, eth->h_source, eth->h_dest);
2956 + } else {
2957 + return mcast_entry_del(0, eth->h_source, eth->h_dest);
2958 + }
2959 + }
2960 +
2961 + return 1;
2962 +}
2963 +
2964 +
2965 +int32_t mcast_tx(struct sk_buff *skb)
2966 +{
2967 + struct vlan_ethhdr *eth = (struct vlan_ethhdr *)(skb->data);
2968 +
2969 +
2970 + if(is_multicast_pkt(eth->h_dest)) {
2971 + MCAST_PRINT("%s: %0X:%0X:%0X:%0X:%0X:%0X\n", __FUNCTION__,\
2972 + MAC_ARG(eth->h_dest));
2973 +
2974 + if(ntohs(eth->h_vlan_proto)==0x8100) {
2975 + mcast_entry_ins(eth->h_vlan_TCI, eth->h_source, eth->h_dest);
2976 + } else {
2977 + mcast_entry_ins(0, eth->h_source, eth->h_dest);
2978 + }
2979 + }
2980 +
2981 + return 1;
2982 +}
2983 +
2984 diff --git a/drivers/net/ethernet/raeth/mii_mgr.c b/drivers/net/ethernet/raeth/mii_mgr.c
2985 new file mode 100644
2986 index 0000000..77a47f1
2987 --- /dev/null
2988 +++ b/drivers/net/ethernet/raeth/mii_mgr.c
2989 @@ -0,0 +1,603 @@
2990 +#include <linux/module.h>
2991 +#include <linux/version.h>
2992 +#include <linux/netdevice.h>
2993 +
2994 +#include <linux/kernel.h>
2995 +#include <linux/sched.h>
2996 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)
2997 +#include <asm/rt2880/rt_mmap.h>
2998 +#endif
2999 +
3000 +#include "ra2882ethreg.h"
3001 +#include "raether.h"
3002 +
3003 +
3004 +#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
3005 +#define PHY_CONTROL_0 0xC0
3006 +#define PHY_CONTROL_1 0xC4
3007 +#define MDIO_PHY_CONTROL_0 (RALINK_ETH_SW_BASE + PHY_CONTROL_0)
3008 +#define MDIO_PHY_CONTROL_1 (RALINK_ETH_SW_BASE + PHY_CONTROL_1)
3009 +
3010 +#define GPIO_MDIO_BIT (1<<7)
3011 +#define GPIO_PURPOSE_SELECT 0x60
3012 +#define GPIO_PRUPOSE (RALINK_SYSCTL_BASE + GPIO_PURPOSE_SELECT)
3013 +
3014 +#elif defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A)
3015 +
3016 +#define PHY_CONTROL_0 0x7004
3017 +#define MDIO_PHY_CONTROL_0 (RALINK_ETH_SW_BASE + PHY_CONTROL_0)
3018 +#define enable_mdio(x)
3019 +
3020 +#elif defined (CONFIG_RALINK_MT7620)
3021 +
3022 +#define PHY_CONTROL_0 0x7004
3023 +#define MDIO_PHY_CONTROL_0 (RALINK_ETH_SW_BASE + PHY_CONTROL_0)
3024 +#define enable_mdio(x)
3025 +
3026 +#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623)
3027 +
3028 +#define PHY_CONTROL_0 0x0004
3029 +#define MDIO_PHY_CONTROL_0 (RALINK_ETH_SW_BASE + PHY_CONTROL_0)
3030 +#define enable_mdio(x)
3031 +
3032 +#else
3033 +#define PHY_CONTROL_0 0x00
3034 +#define PHY_CONTROL_1 0x04
3035 +#define MDIO_PHY_CONTROL_0 (RALINK_FRAME_ENGINE_BASE + PHY_CONTROL_0)
3036 +#define MDIO_PHY_CONTROL_1 (RALINK_FRAME_ENGINE_BASE + PHY_CONTROL_1)
3037 +#define enable_mdio(x)
3038 +#endif
3039 +
3040 +#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
3041 +void enable_mdio(int enable)
3042 +{
3043 +#if !defined (CONFIG_P5_MAC_TO_PHY_MODE) && !defined(CONFIG_GE1_RGMII_AN) && !defined(CONFIG_GE2_RGMII_AN) && \
3044 + !defined (CONFIG_GE1_MII_AN) && !defined (CONFIG_GE2_MII_AN) && !defined (CONFIG_RALINK_MT7628)
3045 + u32 data = sysRegRead(GPIO_PRUPOSE);
3046 + if (enable)
3047 + data &= ~GPIO_MDIO_BIT;
3048 + else
3049 + data |= GPIO_MDIO_BIT;
3050 + sysRegWrite(GPIO_PRUPOSE, data);
3051 +#endif
3052 +}
3053 +#endif
3054 +
3055 +#if defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A)
3056 +
3057 +u32 mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data)
3058 +{
3059 + u32 volatile status = 0;
3060 + u32 rc = 0;
3061 + unsigned long volatile t_start = jiffies;
3062 + u32 volatile data = 0;
3063 +
3064 + /* We enable mdio gpio purpose register, and disable it when exit. */
3065 + enable_mdio(1);
3066 +
3067 + // make sure previous read operation is complete
3068 + while (1) {
3069 + // 0 : Read/write operation complete
3070 + if(!( sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
3071 + {
3072 + break;
3073 + }
3074 + else if (time_after(jiffies, t_start + 5*HZ)) {
3075 + enable_mdio(0);
3076 + printk("\n MDIO Read operation is ongoing !!\n");
3077 + return rc;
3078 + }
3079 + }
3080 +
3081 + data = (0x01 << 16) | (0x02 << 18) | (phy_addr << 20) | (phy_register << 25);
3082 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
3083 + data |= (1<<31);
3084 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
3085 + //printk("\n Set Command [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0);
3086 +
3087 +
3088 + // make sure read operation is complete
3089 + t_start = jiffies;
3090 + while (1) {
3091 + if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) {
3092 + status = sysRegRead(MDIO_PHY_CONTROL_0);
3093 + *read_data = (u32)(status & 0x0000FFFF);
3094 +
3095 + enable_mdio(0);
3096 + return 1;
3097 + }
3098 + else if (time_after(jiffies, t_start+5*HZ)) {
3099 + enable_mdio(0);
3100 + printk("\n MDIO Read operation is ongoing and Time Out!!\n");
3101 + return 0;
3102 + }
3103 + }
3104 +}
3105 +
3106 +u32 mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data)
3107 +{
3108 + unsigned long volatile t_start=jiffies;
3109 + u32 volatile data;
3110 +
3111 + enable_mdio(1);
3112 +
3113 + // make sure previous write operation is complete
3114 + while(1) {
3115 + if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
3116 + {
3117 + break;
3118 + }
3119 + else if (time_after(jiffies, t_start + 5 * HZ)) {
3120 + enable_mdio(0);
3121 + printk("\n MDIO Write operation ongoing\n");
3122 + return 0;
3123 + }
3124 + }
3125 +
3126 + data = (0x01 << 16)| (1<<18) | (phy_addr << 20) | (phy_register << 25) | write_data;
3127 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
3128 + data |= (1<<31);
3129 + sysRegWrite(MDIO_PHY_CONTROL_0, data); //start operation
3130 + //printk("\n Set Command [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0);
3131 +
3132 + t_start = jiffies;
3133 +
3134 + // make sure write operation is complete
3135 + while (1) {
3136 + if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) //0 : Read/write operation complete
3137 + {
3138 + enable_mdio(0);
3139 + return 1;
3140 + }
3141 + else if (time_after(jiffies, t_start + 5 * HZ)) {
3142 + enable_mdio(0);
3143 + printk("\n MDIO Write operation Time Out\n");
3144 + return 0;
3145 + }
3146 + }
3147 +}
3148 +#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7620) || defined (CONFIG_ARCH_MT7623)
3149 +
3150 +u32 __mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data)
3151 +{
3152 + u32 volatile status = 0;
3153 + u32 rc = 0;
3154 + unsigned long volatile t_start = jiffies;
3155 + u32 volatile data = 0;
3156 +
3157 + /* We enable mdio gpio purpose register, and disable it when exit. */
3158 + enable_mdio(1);
3159 +
3160 + // make sure previous read operation is complete
3161 + while (1) {
3162 + // 0 : Read/write operation complete
3163 + if(!( sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
3164 + {
3165 + break;
3166 + }
3167 + else if (time_after(jiffies, t_start + 5*HZ)) {
3168 + enable_mdio(0);
3169 + printk("\n MDIO Read operation is ongoing !!\n");
3170 + return rc;
3171 + }
3172 + }
3173 +
3174 + data = (0x01 << 16) | (0x02 << 18) | (phy_addr << 20) | (phy_register << 25);
3175 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
3176 + data |= (1<<31);
3177 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
3178 + //printk("\n Set Command [0x%08X] = [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0, data);
3179 +
3180 +
3181 + // make sure read operation is complete
3182 + t_start = jiffies;
3183 + while (1) {
3184 + if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) {
3185 + status = sysRegRead(MDIO_PHY_CONTROL_0);
3186 + *read_data = (u32)(status & 0x0000FFFF);
3187 +
3188 + enable_mdio(0);
3189 + return 1;
3190 + }
3191 + else if (time_after(jiffies, t_start+5*HZ)) {
3192 + enable_mdio(0);
3193 + printk("\n MDIO Read operation is ongoing and Time Out!!\n");
3194 + return 0;
3195 + }
3196 + }
3197 +}
3198 +
3199 +u32 __mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data)
3200 +{
3201 + unsigned long volatile t_start=jiffies;
3202 + u32 volatile data;
3203 +
3204 + enable_mdio(1);
3205 +
3206 + // make sure previous write operation is complete
3207 + while(1) {
3208 + if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
3209 + {
3210 + break;
3211 + }
3212 + else if (time_after(jiffies, t_start + 5 * HZ)) {
3213 + enable_mdio(0);
3214 + printk("\n MDIO Write operation ongoing\n");
3215 + return 0;
3216 + }
3217 + }
3218 +
3219 + data = (0x01 << 16)| (1<<18) | (phy_addr << 20) | (phy_register << 25) | write_data;
3220 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
3221 + data |= (1<<31);
3222 + sysRegWrite(MDIO_PHY_CONTROL_0, data); //start operation
3223 + //printk("\n Set Command [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0);
3224 +
3225 + t_start = jiffies;
3226 +
3227 + // make sure write operation is complete
3228 + while (1) {
3229 + if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) //0 : Read/write operation complete
3230 + {
3231 + enable_mdio(0);
3232 + return 1;
3233 + }
3234 + else if (time_after(jiffies, t_start + 5 * HZ)) {
3235 + enable_mdio(0);
3236 + printk("\n MDIO Write operation Time Out\n");
3237 + return 0;
3238 + }
3239 + }
3240 +}
3241 +
3242 +u32 mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data)
3243 +{
3244 +#if defined (CONFIG_GE1_RGMII_FORCE_1000) || defined (CONFIG_GE1_TRGMII_FORCE_1200) || defined (CONFIG_GE1_TRGMII_FORCE_2000) || defined (CONFIG_GE1_TRGMII_FORCE_2600) || defined (CONFIG_P5_RGMII_TO_MT7530_MODE)
3245 + u32 low_word;
3246 + u32 high_word;
3247 + u32 an_status = 0;
3248 +
3249 + if(phy_addr==31)
3250 + {
3251 + an_status = (*(unsigned long *)(ESW_PHY_POLLING) & (1<<31));
3252 + if(an_status){
3253 + *(unsigned long *)(ESW_PHY_POLLING) &= ~(1<<31);//(AN polling off)
3254 + }
3255 + //phase1: write page address phase
3256 + if(__mii_mgr_write(phy_addr, 0x1f, ((phy_register >> 6) & 0x3FF))) {
3257 + //phase2: write address & read low word phase
3258 + if(__mii_mgr_read(phy_addr, (phy_register >> 2) & 0xF, &low_word)) {
3259 + //phase3: write address & read high word phase
3260 + if(__mii_mgr_read(phy_addr, (0x1 << 4), &high_word)) {
3261 + *read_data = (high_word << 16) | (low_word & 0xFFFF);
3262 + if(an_status){
3263 + *(unsigned long *)(ESW_PHY_POLLING) |= (1<<31);//(AN polling on)
3264 + }
3265 + return 1;
3266 + }
3267 + }
3268 + }
3269 + if(an_status){
3270 + *(unsigned long *)(ESW_PHY_POLLING) |= (1<<31);//(AN polling on)
3271 + }
3272 + } else
3273 +#endif
3274 + {
3275 + if(__mii_mgr_read(phy_addr, phy_register, read_data)) {
3276 + return 1;
3277 + }
3278 + }
3279 +
3280 + return 0;
3281 +}
3282 +
3283 +u32 mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data)
3284 +{
3285 +#if defined (CONFIG_GE1_RGMII_FORCE_1000) || defined (CONFIG_GE1_TRGMII_FORCE_1200) || defined (CONFIG_GE1_TRGMII_FORCE_2000) || defined (CONFIG_GE1_TRGMII_FORCE_2600) || defined (CONFIG_P5_RGMII_TO_MT7530_MODE)
3286 + u32 an_status = 0;
3287 +
3288 + if(phy_addr == 31)
3289 + {
3290 + an_status = (*(unsigned long *)(ESW_PHY_POLLING) & (1<<31));
3291 + if(an_status){
3292 + *(unsigned long *)(ESW_PHY_POLLING) &= ~(1<<31);//(AN polling off)
3293 + }
3294 + //phase1: write page address phase
3295 + if(__mii_mgr_write(phy_addr, 0x1f, (phy_register >> 6) & 0x3FF)) {
3296 + //phase2: write address & read low word phase
3297 + if(__mii_mgr_write(phy_addr, ((phy_register >> 2) & 0xF), write_data & 0xFFFF)) {
3298 + //phase3: write address & read high word phase
3299 + if(__mii_mgr_write(phy_addr, (0x1 << 4), write_data >> 16)) {
3300 + if(an_status){
3301 + *(unsigned long *)(ESW_PHY_POLLING) |= (1<<31);//(AN polling on)
3302 + }
3303 + return 1;
3304 + }
3305 + }
3306 + }
3307 + if(an_status){
3308 + *(unsigned long *)(ESW_PHY_POLLING) |= (1<<31);//(AN polling on)
3309 + }
3310 + } else
3311 +#endif
3312 + {
3313 + if(__mii_mgr_write(phy_addr, phy_register, write_data)) {
3314 + return 1;
3315 + }
3316 + }
3317 +
3318 + return 0;
3319 +}
3320 +
3321 +u32 mii_mgr_cl45_set_address(u32 port_num, u32 dev_addr, u32 reg_addr)
3322 +{
3323 + u32 rc = 0;
3324 + unsigned long volatile t_start = jiffies;
3325 + u32 volatile data = 0;
3326 +
3327 + enable_mdio(1);
3328 +
3329 + while (1) {
3330 + if(!( sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
3331 + {
3332 + break;
3333 + }
3334 + else if (time_after(jiffies, t_start + 5*HZ)) {
3335 + enable_mdio(0);
3336 + printk("\n MDIO Read operation is ongoing !!\n");
3337 + return rc;
3338 + }
3339 + }
3340 + data = (dev_addr << 25) | (port_num << 20) | (0x00 << 18) | (0x00 << 16) | reg_addr;
3341 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
3342 + data |= (1<<31);
3343 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
3344 +
3345 + t_start = jiffies;
3346 + while (1) {
3347 + if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) //0 : Read/write operation complete
3348 + {
3349 + enable_mdio(0);
3350 + return 1;
3351 + }
3352 + else if (time_after(jiffies, t_start + 5 * HZ)) {
3353 + enable_mdio(0);
3354 + printk("\n MDIO Write operation Time Out\n");
3355 + return 0;
3356 + }
3357 + }
3358 +
3359 +}
3360 +
3361 +
3362 +u32 mii_mgr_read_cl45(u32 port_num, u32 dev_addr, u32 reg_addr, u32 *read_data)
3363 +{
3364 + u32 volatile status = 0;
3365 + u32 rc = 0;
3366 + unsigned long volatile t_start = jiffies;
3367 + u32 volatile data = 0;
3368 +
3369 + // set address first
3370 + mii_mgr_cl45_set_address(port_num, dev_addr, reg_addr);
3371 + //udelay(10);
3372 +
3373 + enable_mdio(1);
3374 +
3375 + while (1) {
3376 + if(!( sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
3377 + {
3378 + break;
3379 + }
3380 + else if (time_after(jiffies, t_start + 5*HZ)) {
3381 + enable_mdio(0);
3382 + printk("\n MDIO Read operation is ongoing !!\n");
3383 + return rc;
3384 + }
3385 + }
3386 + data = (dev_addr << 25) | (port_num << 20) | (0x03 << 18) | (0x00 << 16) | reg_addr;
3387 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
3388 + data |= (1<<31);
3389 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
3390 + t_start = jiffies;
3391 + while (1) {
3392 + if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) {
3393 + *read_data = (sysRegRead(MDIO_PHY_CONTROL_0) & 0x0000FFFF);
3394 + enable_mdio(0);
3395 + return 1;
3396 + }
3397 + else if (time_after(jiffies, t_start+5*HZ)) {
3398 + enable_mdio(0);
3399 + printk("\n Set Operation: MDIO Read operation is ongoing and Time Out!!\n");
3400 + return 0;
3401 + }
3402 + status = sysRegRead(MDIO_PHY_CONTROL_0);
3403 + }
3404 +
3405 +}
3406 +
3407 +u32 mii_mgr_write_cl45 (u32 port_num, u32 dev_addr, u32 reg_addr, u32 write_data)
3408 +{
3409 + u32 rc = 0;
3410 + unsigned long volatile t_start = jiffies;
3411 + u32 volatile data = 0;
3412 +
3413 + // set address first
3414 + mii_mgr_cl45_set_address(port_num, dev_addr, reg_addr);
3415 + //udelay(10);
3416 +
3417 + enable_mdio(1);
3418 + while (1) {
3419 + if(!( sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
3420 + {
3421 + break;
3422 + }
3423 + else if (time_after(jiffies, t_start + 5*HZ)) {
3424 + enable_mdio(0);
3425 + printk("\n MDIO Read operation is ongoing !!\n");
3426 + return rc;
3427 + }
3428 + }
3429 +
3430 + data = (dev_addr << 25) | (port_num << 20) | (0x01 << 18) | (0x00 << 16) | write_data;
3431 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
3432 + data |= (1<<31);
3433 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
3434 +
3435 + t_start = jiffies;
3436 +
3437 + while (1) {
3438 + if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
3439 + {
3440 + enable_mdio(0);
3441 + return 1;
3442 + }
3443 + else if (time_after(jiffies, t_start + 5 * HZ)) {
3444 + enable_mdio(0);
3445 + printk("\n MDIO Write operation Time Out\n");
3446 + return 0;
3447 + }
3448 +
3449 + }
3450 +}
3451 +
3452 +#else // not rt6855
3453 +
3454 +u32 mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data)
3455 +{
3456 + u32 volatile status = 0;
3457 + u32 rc = 0;
3458 + unsigned long volatile t_start = jiffies;
3459 +#if !defined (CONFIG_RALINK_RT3052) && !defined (CONFIG_RALINK_RT3352) && !defined (CONFIG_RALINK_RT5350) && !defined (CONFIG_RALINK_MT7628)
3460 + u32 volatile data = 0;
3461 +#endif
3462 +
3463 + /* We enable mdio gpio purpose register, and disable it when exit. */
3464 + enable_mdio(1);
3465 +
3466 + // make sure previous read operation is complete
3467 + while (1) {
3468 +#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
3469 + // rd_rdy: read operation is complete
3470 + if(!( sysRegRead(MDIO_PHY_CONTROL_1) & (0x1 << 1)))
3471 +#else
3472 + // 0 : Read/write operation complet
3473 + if(!( sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
3474 +#endif
3475 + {
3476 + break;
3477 + }
3478 + else if (time_after(jiffies, t_start + 5*HZ)) {
3479 + enable_mdio(0);
3480 + printk("\n MDIO Read operation is ongoing !!\n");
3481 + return rc;
3482 + }
3483 + }
3484 +
3485 +#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
3486 + sysRegWrite(MDIO_PHY_CONTROL_0 , (1<<14) | (phy_register << 8) | (phy_addr));
3487 +#else
3488 + data = (phy_addr << 24) | (phy_register << 16);
3489 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
3490 + data |= (1<<31);
3491 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
3492 +#endif
3493 + //printk("\n Set Command [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0);
3494 +
3495 +
3496 + // make sure read operation is complete
3497 + t_start = jiffies;
3498 + while (1) {
3499 +#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
3500 + if (sysRegRead(MDIO_PHY_CONTROL_1) & (0x1 << 1)) {
3501 + status = sysRegRead(MDIO_PHY_CONTROL_1);
3502 + *read_data = (u32)(status >>16);
3503 +
3504 + enable_mdio(0);
3505 + return 1;
3506 + }
3507 +#else
3508 + if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) {
3509 + status = sysRegRead(MDIO_PHY_CONTROL_0);
3510 + *read_data = (u32)(status & 0x0000FFFF);
3511 +
3512 + enable_mdio(0);
3513 + return 1;
3514 + }
3515 +#endif
3516 + else if (time_after(jiffies, t_start+5*HZ)) {
3517 + enable_mdio(0);
3518 + printk("\n MDIO Read operation is ongoing and Time Out!!\n");
3519 + return 0;
3520 + }
3521 + }
3522 +}
3523 +
3524 +
3525 +u32 mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data)
3526 +{
3527 + unsigned long volatile t_start=jiffies;
3528 + u32 volatile data;
3529 +
3530 + enable_mdio(1);
3531 +
3532 + // make sure previous write operation is complete
3533 + while(1) {
3534 +#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
3535 + if (!(sysRegRead(MDIO_PHY_CONTROL_1) & (0x1 << 0)))
3536 +#else
3537 + if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
3538 +#endif
3539 + {
3540 + break;
3541 + }
3542 + else if (time_after(jiffies, t_start + 5 * HZ)) {
3543 + enable_mdio(0);
3544 + printk("\n MDIO Write operation ongoing\n");
3545 + return 0;
3546 + }
3547 + }
3548 +
3549 +#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
3550 + data = ((write_data & 0xFFFF) << 16);
3551 + data |= (phy_register << 8) | (phy_addr);
3552 + data |= (1<<13);
3553 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
3554 +#else
3555 + data = (1<<30) | (phy_addr << 24) | (phy_register << 16) | write_data;
3556 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
3557 + data |= (1<<31);
3558 + sysRegWrite(MDIO_PHY_CONTROL_0, data); //start operation
3559 +#endif
3560 + //printk("\n Set Command [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0);
3561 +
3562 + t_start = jiffies;
3563 +
3564 + // make sure write operation is complete
3565 + while (1) {
3566 +#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
3567 + if (sysRegRead(MDIO_PHY_CONTROL_1) & (0x1 << 0)) //wt_done ?= 1
3568 +#else
3569 + if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) //0 : Read/write operation complete
3570 +#endif
3571 + {
3572 + enable_mdio(0);
3573 + return 1;
3574 + }
3575 + else if (time_after(jiffies, t_start + 5 * HZ)) {
3576 + enable_mdio(0);
3577 + printk("\n MDIO Write operation Time Out\n");
3578 + return 0;
3579 + }
3580 + }
3581 +}
3582 +
3583 +
3584 +
3585 +
3586 +#endif
3587 +
3588 +
3589 +
3590 +
3591 +EXPORT_SYMBOL(mii_mgr_write);
3592 +EXPORT_SYMBOL(mii_mgr_read);
3593 diff --git a/drivers/net/ethernet/raeth/ra2882ethreg.h b/drivers/net/ethernet/raeth/ra2882ethreg.h
3594 new file mode 100644
3595 index 0000000..c67a042
3596 --- /dev/null
3597 +++ b/drivers/net/ethernet/raeth/ra2882ethreg.h
3598 @@ -0,0 +1,1985 @@
3599 +#ifndef RA2882ETHREG_H
3600 +#define RA2882ETHREG_H
3601 +
3602 +#include <linux/mii.h> // for struct mii_if_info in ra2882ethreg.h
3603 +#include <linux/version.h> /* check linux version for 2.4 and 2.6 compatibility */
3604 +#include <linux/interrupt.h> /* for "struct tasklet_struct" in linux-3.10.14 */
3605 +#if defined (CONFIG_HW_SFQ)
3606 +#include <linux/ip.h>
3607 +#include <linux/ipv6.h>
3608 +#endif
3609 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
3610 +#include <asm/rt2880/rt_mmap.h>
3611 +#endif
3612 +#include "raether.h"
3613 +
3614 +#ifdef WORKQUEUE_BH
3615 +#include <linux/workqueue.h>
3616 +#endif // WORKQUEUE_BH //
3617 +#ifdef CONFIG_RAETH_LRO
3618 +#include <linux/inet_lro.h>
3619 +#endif
3620 +
3621 +#define MAX_PACKET_SIZE 1514
3622 +#define MIN_PACKET_SIZE 60
3623 +#define MAX_TXD_LEN 0x3fff
3624 +
3625 +#if defined (CONFIG_ARCH_MT7623)
3626 +#define phys_to_bus(a) (a)
3627 +#else
3628 +#define phys_to_bus(a) (a & 0x1FFFFFFF)
3629 +#endif
3630 +
3631 +
3632 +
3633 +
3634 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
3635 +#define BIT(x) ((1 << x))
3636 +#endif
3637 +/* bits range: for example BITS(16,23) = 0xFF0000
3638 + * ==> (BIT(m)-1) = 0x0000FFFF ~(BIT(m)-1) => 0xFFFF0000
3639 + * ==> (BIT(n+1)-1) = 0x00FFFFFF
3640 + */
3641 +#define BITS(m,n) (~(BIT(m)-1) & ((BIT(n) - 1) | BIT(n)))
3642 +
3643 +#define ETHER_ADDR_LEN 6
3644 +
3645 +/* Phy Vender ID list */
3646 +
3647 +#define EV_ICPLUS_PHY_ID0 0x0243
3648 +#define EV_ICPLUS_PHY_ID1 0x0D90
3649 +#define EV_MARVELL_PHY_ID0 0x0141
3650 +#define EV_MARVELL_PHY_ID1 0x0CC2
3651 +#define EV_VTSS_PHY_ID0 0x0007
3652 +#define EV_VTSS_PHY_ID1 0x0421
3653 +
3654 +/*
3655 + FE_INT_STATUS
3656 +*/
3657 +#if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
3658 + defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) || \
3659 + defined (CONFIG_ARCH_MT7623)
3660 +
3661 +#define RX_COHERENT BIT(31)
3662 +#define RX_DLY_INT BIT(30)
3663 +#define TX_COHERENT BIT(29)
3664 +#define TX_DLY_INT BIT(28)
3665 +#define RING3_RX_DLY_INT BIT(27)
3666 +#define RING2_RX_DLY_INT BIT(26)
3667 +#define RING1_RX_DLY_INT BIT(25)
3668 +
3669 +#define ALT_RPLC_INT3 BIT(23)
3670 +#define ALT_RPLC_INT2 BIT(22)
3671 +#define ALT_RPLC_INT1 BIT(21)
3672 +
3673 +#define RX_DONE_INT3 BIT(19)
3674 +#define RX_DONE_INT2 BIT(18)
3675 +#define RX_DONE_INT1 BIT(17)
3676 +#define RX_DONE_INT0 BIT(16)
3677 +
3678 +#define TX_DONE_INT3 BIT(3)
3679 +#define TX_DONE_INT2 BIT(2)
3680 +#define TX_DONE_INT1 BIT(1)
3681 +#define TX_DONE_INT0 BIT(0)
3682 +
3683 +#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623)
3684 +#define RLS_COHERENT BIT(29)
3685 +#define RLS_DLY_INT BIT(28)
3686 +#define RLS_DONE_INT BIT(0)
3687 +#endif
3688 +
3689 +#else
3690 +//#define CNT_PPE_AF BIT(31)
3691 +//#define CNT_GDM_AF BIT(29)
3692 +#define PSE_P2_FC BIT(26)
3693 +#define GDM_CRC_DROP BIT(25)
3694 +#define PSE_BUF_DROP BIT(24)
3695 +#define GDM_OTHER_DROP BIT(23)
3696 +#define PSE_P1_FC BIT(22)
3697 +#define PSE_P0_FC BIT(21)
3698 +#define PSE_FQ_EMPTY BIT(20)
3699 +#define GE1_STA_CHG BIT(18)
3700 +#define TX_COHERENT BIT(17)
3701 +#define RX_COHERENT BIT(16)
3702 +
3703 +#define TX_DONE_INT3 BIT(11)
3704 +#define TX_DONE_INT2 BIT(10)
3705 +#define TX_DONE_INT1 BIT(9)
3706 +#define TX_DONE_INT0 BIT(8)
3707 +#define RX_DONE_INT1 RX_DONE_INT0
3708 +#define RX_DONE_INT0 BIT(2)
3709 +#define TX_DLY_INT BIT(1)
3710 +#define RX_DLY_INT BIT(0)
3711 +#endif
3712 +
3713 +#define FE_INT_ALL (TX_DONE_INT3 | TX_DONE_INT2 | \
3714 + TX_DONE_INT1 | TX_DONE_INT0 | \
3715 + RX_DONE_INT0 | RX_DONE_INT1 | \
3716 + RX_DONE_INT2 | RX_DONE_INT3)
3717 +
3718 +#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623)
3719 +#define QFE_INT_ALL (RLS_DONE_INT | RX_DONE_INT0 | RX_DONE_INT1)
3720 +#define QFE_INT_DLY_INIT (RLS_DLY_INT | RX_DLY_INT)
3721 +
3722 +#define NUM_QDMA_PAGE 512
3723 +#define QDMA_PAGE_SIZE 2048
3724 +#endif
3725 +/*
3726 + * SW_INT_STATUS
3727 + */
3728 +#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
3729 +#define PORT0_QUEUE_FULL BIT(14) //port0 queue full
3730 +#define PORT1_QUEUE_FULL BIT(15) //port1 queue full
3731 +#define PORT2_QUEUE_FULL BIT(16) //port2 queue full
3732 +#define PORT3_QUEUE_FULL BIT(17) //port3 queue full
3733 +#define PORT4_QUEUE_FULL BIT(18) //port4 queue full
3734 +#define PORT5_QUEUE_FULL BIT(19) //port5 queue full
3735 +#define PORT6_QUEUE_FULL BIT(20) //port6 queue full
3736 +#define SHARED_QUEUE_FULL BIT(23) //shared queue full
3737 +#define QUEUE_EXHAUSTED BIT(24) //global queue is used up and all packets are dropped
3738 +#define BC_STROM BIT(25) //the device is undergoing broadcast storm
3739 +#define PORT_ST_CHG BIT(26) //Port status change
3740 +#define UNSECURED_ALERT BIT(27) //Intruder alert
3741 +#define ABNORMAL_ALERT BIT(28) //Abnormal
3742 +
3743 +#define ESW_ISR (RALINK_ETH_SW_BASE + 0x00)
3744 +#define ESW_IMR (RALINK_ETH_SW_BASE + 0x04)
3745 +#define ESW_INT_ALL (PORT_ST_CHG)
3746 +
3747 +#elif defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
3748 + defined (CONFIG_RALINK_MT7620)
3749 +#define MIB_INT BIT(25)
3750 +#define ACL_INT BIT(24)
3751 +#define P5_LINK_CH BIT(5)
3752 +#define P4_LINK_CH BIT(4)
3753 +#define P3_LINK_CH BIT(3)
3754 +#define P2_LINK_CH BIT(2)
3755 +#define P1_LINK_CH BIT(1)
3756 +#define P0_LINK_CH BIT(0)
3757 +
3758 +#define RX_GOCT_CNT BIT(4)
3759 +#define RX_GOOD_CNT BIT(6)
3760 +#define TX_GOCT_CNT BIT(17)
3761 +#define TX_GOOD_CNT BIT(19)
3762 +
3763 +#define MSK_RX_GOCT_CNT BIT(4)
3764 +#define MSK_RX_GOOD_CNT BIT(6)
3765 +#define MSK_TX_GOCT_CNT BIT(17)
3766 +#define MSK_TX_GOOD_CNT BIT(19)
3767 +#define MSK_CNT_INT_ALL (MSK_RX_GOCT_CNT | MSK_RX_GOOD_CNT | MSK_TX_GOCT_CNT | MSK_TX_GOOD_CNT)
3768 +//#define MSK_CNT_INT_ALL (MSK_RX_GOOD_CNT | MSK_TX_GOOD_CNT)
3769 +
3770 +
3771 +#define ESW_IMR (RALINK_ETH_SW_BASE + 0x7000 + 0x8)
3772 +#define ESW_ISR (RALINK_ETH_SW_BASE + 0x7000 + 0xC)
3773 +#define ESW_INT_ALL (P0_LINK_CH | P1_LINK_CH | P2_LINK_CH | P3_LINK_CH | P4_LINK_CH | P5_LINK_CH | ACL_INT | MIB_INT)
3774 +#define ESW_AISR (RALINK_ETH_SW_BASE + 0x8)
3775 +#define ESW_P0_IntSn (RALINK_ETH_SW_BASE + 0x4004)
3776 +#define ESW_P1_IntSn (RALINK_ETH_SW_BASE + 0x4104)
3777 +#define ESW_P2_IntSn (RALINK_ETH_SW_BASE + 0x4204)
3778 +#define ESW_P3_IntSn (RALINK_ETH_SW_BASE + 0x4304)
3779 +#define ESW_P4_IntSn (RALINK_ETH_SW_BASE + 0x4404)
3780 +#define ESW_P5_IntSn (RALINK_ETH_SW_BASE + 0x4504)
3781 +#define ESW_P6_IntSn (RALINK_ETH_SW_BASE + 0x4604)
3782 +#define ESW_P0_IntMn (RALINK_ETH_SW_BASE + 0x4008)
3783 +#define ESW_P1_IntMn (RALINK_ETH_SW_BASE + 0x4108)
3784 +#define ESW_P2_IntMn (RALINK_ETH_SW_BASE + 0x4208)
3785 +#define ESW_P3_IntMn (RALINK_ETH_SW_BASE + 0x4308)
3786 +#define ESW_P4_IntMn (RALINK_ETH_SW_BASE + 0x4408)
3787 +#define ESW_P5_IntMn (RALINK_ETH_SW_BASE + 0x4508)
3788 +#define ESW_P6_IntMn (RALINK_ETH_SW_BASE + 0x4608)
3789 +
3790 +#if defined (CONFIG_RALINK_MT7620)
3791 +#define ESW_P7_IntSn (RALINK_ETH_SW_BASE + 0x4704)
3792 +#define ESW_P7_IntMn (RALINK_ETH_SW_BASE + 0x4708)
3793 +#endif
3794 +
3795 +
3796 +#define ESW_PHY_POLLING (RALINK_ETH_SW_BASE + 0x7000)
3797 +
3798 +#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623)
3799 +
3800 +#define ESW_PHY_POLLING (RALINK_ETH_SW_BASE + 0x0000)
3801 +
3802 +#define P5_LINK_CH BIT(5)
3803 +#define P4_LINK_CH BIT(4)
3804 +#define P3_LINK_CH BIT(3)
3805 +#define P2_LINK_CH BIT(2)
3806 +#define P1_LINK_CH BIT(1)
3807 +#define P0_LINK_CH BIT(0)
3808 +
3809 +
3810 +#endif // CONFIG_RALINK_RT3052 || CONFIG_RALINK_RT3352 || CONFIG_RALINK_RT5350 || defined (CONFIG_RALINK_MT7628)//
3811 +
3812 +#define RX_BUF_ALLOC_SIZE 2000
3813 +#define FASTPATH_HEADROOM 64
3814 +
3815 +#define ETHER_BUFFER_ALIGN 32 ///// Align on a cache line
3816 +
3817 +#define ETHER_ALIGNED_RX_SKB_ADDR(addr) \
3818 + ((((unsigned long)(addr) + ETHER_BUFFER_ALIGN - 1) & \
3819 + ~(ETHER_BUFFER_ALIGN - 1)) - (unsigned long)(addr))
3820 +
3821 +#ifdef CONFIG_PSEUDO_SUPPORT
3822 +typedef struct _PSEUDO_ADAPTER {
3823 + struct net_device *RaethDev;
3824 + struct net_device *PseudoDev;
3825 + struct net_device_stats stat;
3826 +#if defined (CONFIG_ETHTOOL) /*&& defined (CONFIG_RAETH_ROUTER)*/
3827 + struct mii_if_info mii_info;
3828 +#endif
3829 +
3830 +} PSEUDO_ADAPTER, PPSEUDO_ADAPTER;
3831 +
3832 +#define MAX_PSEUDO_ENTRY 1
3833 +#endif
3834 +
3835 +
3836 +
3837 +/* Register Categories Definition */
3838 +#define RAFRAMEENGINE_OFFSET 0x0000
3839 +#define RAGDMA_OFFSET 0x0020
3840 +#define RAPSE_OFFSET 0x0040
3841 +#define RAGDMA2_OFFSET 0x0060
3842 +#define RACDMA_OFFSET 0x0080
3843 +#if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
3844 + defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) || \
3845 + defined (CONFIG_ARCH_MT7623)
3846 +
3847 +#define RAPDMA_OFFSET 0x0800
3848 +#define SDM_OFFSET 0x0C00
3849 +#else
3850 +#define RAPDMA_OFFSET 0x0100
3851 +#endif
3852 +#define RAPPE_OFFSET 0x0200
3853 +#define RACMTABLE_OFFSET 0x0400
3854 +#define RAPOLICYTABLE_OFFSET 0x1000
3855 +
3856 +
3857 +/* Register Map Detail */
3858 +/* RT3883 */
3859 +#define SYSCFG1 (RALINK_SYSCTL_BASE + 0x14)
3860 +
3861 +#if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
3862 +
3863 +/* 1. PDMA */
3864 +#define TX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x000)
3865 +#define TX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x004)
3866 +#define TX_CTX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x008)
3867 +#define TX_DTX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x00C)
3868 +
3869 +#define TX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x010)
3870 +#define TX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x014)
3871 +#define TX_CTX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x018)
3872 +#define TX_DTX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x01C)
3873 +
3874 +#define TX_BASE_PTR2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x020)
3875 +#define TX_MAX_CNT2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x024)
3876 +#define TX_CTX_IDX2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x028)
3877 +#define TX_DTX_IDX2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x02C)
3878 +
3879 +#define TX_BASE_PTR3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x030)
3880 +#define TX_MAX_CNT3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x034)
3881 +#define TX_CTX_IDX3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x038)
3882 +#define TX_DTX_IDX3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x03C)
3883 +
3884 +#define RX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x100)
3885 +#define RX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x104)
3886 +#define RX_CALC_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x108)
3887 +#define RX_DRX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x10C)
3888 +
3889 +#define RX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x110)
3890 +#define RX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x114)
3891 +#define RX_CALC_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x118)
3892 +#define RX_DRX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x11C)
3893 +
3894 +#define PDMA_INFO (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x200)
3895 +#define PDMA_GLO_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x204)
3896 +#define PDMA_RST_IDX (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x208)
3897 +#define PDMA_RST_CFG (PDMA_RST_IDX)
3898 +#define DLY_INT_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x20C)
3899 +#define FREEQ_THRES (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x210)
3900 +#define INT_STATUS (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x220)
3901 +#define FE_INT_STATUS (INT_STATUS)
3902 +#define INT_MASK (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x228)
3903 +#define FE_INT_ENABLE (INT_MASK)
3904 +#define PDMA_WRR (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x280)
3905 +#define PDMA_SCH_CFG (PDMA_WRR)
3906 +
3907 +#define SDM_CON (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x00) //Switch DMA configuration
3908 +#define SDM_RRING (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x04) //Switch DMA Rx Ring
3909 +#define SDM_TRING (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x08) //Switch DMA Tx Ring
3910 +#define SDM_MAC_ADRL (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x0C) //Switch MAC address LSB
3911 +#define SDM_MAC_ADRH (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x10) //Switch MAC Address MSB
3912 +#define SDM_TPCNT (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x100) //Switch DMA Tx packet count
3913 +#define SDM_TBCNT (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x104) //Switch DMA Tx byte count
3914 +#define SDM_RPCNT (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x108) //Switch DMA rx packet count
3915 +#define SDM_RBCNT (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x10C) //Switch DMA rx byte count
3916 +#define SDM_CS_ERR (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x110) //Switch DMA rx checksum error count
3917 +
3918 +#elif defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
3919 + defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621) || \
3920 + defined (CONFIG_ARCH_MT7623)
3921 +
3922 +/* Old FE with New PDMA */
3923 +#define PDMA_RELATED 0x0800
3924 +/* 1. PDMA */
3925 +#define TX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x000)
3926 +#define TX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x004)
3927 +#define TX_CTX_IDX0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x008)
3928 +#define TX_DTX_IDX0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x00C)
3929 +
3930 +#define TX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x010)
3931 +#define TX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x014)
3932 +#define TX_CTX_IDX1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x018)
3933 +#define TX_DTX_IDX1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x01C)
3934 +
3935 +#define TX_BASE_PTR2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x020)
3936 +#define TX_MAX_CNT2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x024)
3937 +#define TX_CTX_IDX2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x028)
3938 +#define TX_DTX_IDX2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x02C)
3939 +
3940 +#define TX_BASE_PTR3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x030)
3941 +#define TX_MAX_CNT3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x034)
3942 +#define TX_CTX_IDX3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x038)
3943 +#define TX_DTX_IDX3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x03C)
3944 +
3945 +#define RX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x100)
3946 +#define RX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x104)
3947 +#define RX_CALC_IDX0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x108)
3948 +#define RX_DRX_IDX0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x10C)
3949 +
3950 +#define RX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x110)
3951 +#define RX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x114)
3952 +#define RX_CALC_IDX1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x118)
3953 +#define RX_DRX_IDX1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x11C)
3954 +
3955 +#define RX_BASE_PTR2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x120)
3956 +#define RX_MAX_CNT2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x124)
3957 +#define RX_CALC_IDX2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x128)
3958 +#define RX_DRX_IDX12 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x12C)
3959 +
3960 +#define RX_BASE_PTR3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x130)
3961 +#define RX_MAX_CNT3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x134)
3962 +#define RX_CALC_IDX3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x138)
3963 +#define RX_DRX_IDX3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x13C)
3964 +
3965 +#define PDMA_INFO (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x200)
3966 +#define PDMA_GLO_CFG (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x204)
3967 +#define PDMA_RST_IDX (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x208)
3968 +#define PDMA_RST_CFG (PDMA_RST_IDX)
3969 +#define DLY_INT_CFG (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x20C)
3970 +#define FREEQ_THRES (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x210)
3971 +#define INT_STATUS (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x220)
3972 +#define FE_INT_STATUS (INT_STATUS)
3973 +#define INT_MASK (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x228)
3974 +#define FE_INT_ENABLE (INT_MASK)
3975 +#define SCH_Q01_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x280)
3976 +#define SCH_Q23_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x284)
3977 +
3978 +#define FE_GLO_CFG RALINK_FRAME_ENGINE_BASE + 0x00
3979 +#define FE_RST_GL RALINK_FRAME_ENGINE_BASE + 0x04
3980 +#define FE_INT_STATUS2 RALINK_FRAME_ENGINE_BASE + 0x08
3981 +#define FE_INT_ENABLE2 RALINK_FRAME_ENGINE_BASE + 0x0c
3982 +//#define FC_DROP_STA RALINK_FRAME_ENGINE_BASE + 0x18
3983 +#define FOE_TS_T RALINK_FRAME_ENGINE_BASE + 0x10
3984 +
3985 +#if defined (CONFIG_RALINK_MT7620)
3986 +#define GDMA1_RELATED 0x0600
3987 +#define GDMA1_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x00)
3988 +#define GDMA1_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x04)
3989 +#define GDMA1_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x08)
3990 +#define GDMA1_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x0C)
3991 +#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623)
3992 +#define GDMA1_RELATED 0x0500
3993 +#define GDMA1_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x00)
3994 +#define GDMA1_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x04)
3995 +#define GDMA1_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x08)
3996 +#define GDMA1_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x0C)
3997 +
3998 +#define GDMA2_RELATED 0x1500
3999 +#define GDMA2_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x00)
4000 +#define GDMA2_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x04)
4001 +#define GDMA2_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x08)
4002 +#define GDMA2_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x0C)
4003 +#else
4004 +#define GDMA1_RELATED 0x0020
4005 +#define GDMA1_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x00)
4006 +#define GDMA1_SCH_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x04)
4007 +#define GDMA1_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x08)
4008 +#define GDMA1_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x0C)
4009 +#define GDMA1_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x10)
4010 +
4011 +#define GDMA2_RELATED 0x0060
4012 +#define GDMA2_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x00)
4013 +#define GDMA2_SCH_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x04)
4014 +#define GDMA2_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x08)
4015 +#define GDMA2_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x0C)
4016 +#define GDMA2_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x10)
4017 +#endif
4018 +
4019 +#if defined (CONFIG_RALINK_MT7620)
4020 +#define PSE_RELATED 0x0500
4021 +#define PSE_FQFC_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x00)
4022 +#define PSE_IQ_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x04)
4023 +#define PSE_QUE_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x08)
4024 +#else
4025 +#define PSE_RELATED 0x0040
4026 +#define PSE_FQ_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x00)
4027 +#define CDMA_FC_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x04)
4028 +#define GDMA1_FC_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x08)
4029 +#define GDMA2_FC_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x0C)
4030 +#define CDMA_OQ_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x10)
4031 +#define GDMA1_OQ_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x14)
4032 +#define GDMA2_OQ_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x18)
4033 +#define PSE_IQ_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x1C)
4034 +#endif
4035 +
4036 +
4037 +#if defined (CONFIG_RALINK_MT7620)
4038 +#define CDMA_RELATED 0x0400
4039 +#define CDMA_CSG_CFG (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x00)
4040 +#define SMACCR0 (RALINK_ETH_SW_BASE + 0x3FE4)
4041 +#define SMACCR1 (RALINK_ETH_SW_BASE + 0x3FE8)
4042 +#define CKGCR (RALINK_ETH_SW_BASE + 0x3FF0)
4043 +#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623)