kernel: update 4.1 to 4.1.13
[openwrt/openwrt.git] / target / linux / mediatek / patches / 0063-arm-mediatek-add-SDK-ethernet.patch
1 From e3aece79d5003b6879298b05551e113117d5cdd8 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sat, 27 Jun 2015 13:13:36 +0200
4 Subject: [PATCH 63/76] arm: mediatek: add SDK ethernet
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 drivers/net/ethernet/Kconfig | 1 +
9 drivers/net/ethernet/Makefile | 1 +
10 drivers/net/ethernet/raeth/Kconfig | 415 ++
11 drivers/net/ethernet/raeth/Makefile | 67 +
12 drivers/net/ethernet/raeth/Makefile.release | 60 +
13 drivers/net/ethernet/raeth/csr_netlink.h | 27 +
14 drivers/net/ethernet/raeth/dvt/pkt_gen.c | 88 +
15 drivers/net/ethernet/raeth/dvt/pkt_gen_tcp_frag.c | 138 +
16 drivers/net/ethernet/raeth/dvt/pkt_gen_udp_frag.c | 191 +
17 drivers/net/ethernet/raeth/dvt/raether_pdma_dvt.c | 1527 +++++
18 drivers/net/ethernet/raeth/dvt/raether_pdma_dvt.h | 75 +
19 drivers/net/ethernet/raeth/ethtool_readme.txt | 44 +
20 drivers/net/ethernet/raeth/mcast.c | 187 +
21 drivers/net/ethernet/raeth/mii_mgr.c | 603 ++
22 drivers/net/ethernet/raeth/ra2882ethreg.h | 1985 +++++++
23 drivers/net/ethernet/raeth/ra_ethtool.c | 515 ++
24 drivers/net/ethernet/raeth/ra_ethtool.h | 13 +
25 drivers/net/ethernet/raeth/ra_ioctl.h | 102 +
26 drivers/net/ethernet/raeth/ra_mac.c | 2645 +++++++++
27 drivers/net/ethernet/raeth/ra_mac.h | 57 +
28 drivers/net/ethernet/raeth/ra_netlink.c | 142 +
29 drivers/net/ethernet/raeth/ra_netlink.h | 10 +
30 drivers/net/ethernet/raeth/ra_qos.c | 655 +++
31 drivers/net/ethernet/raeth/ra_qos.h | 18 +
32 drivers/net/ethernet/raeth/ra_rfrw.c | 66 +
33 drivers/net/ethernet/raeth/ra_rfrw.h | 6 +
34 drivers/net/ethernet/raeth/raether.c | 6401 +++++++++++++++++++++
35 drivers/net/ethernet/raeth/raether.h | 126 +
36 drivers/net/ethernet/raeth/raether_hwlro.c | 347 ++
37 drivers/net/ethernet/raeth/raether_pdma.c | 1121 ++++
38 drivers/net/ethernet/raeth/raether_qdma.c | 1407 +++++
39 drivers/net/ethernet/raeth/raether_qdma_mt7623.c | 1020 ++++
40 drivers/net/ethernet/raeth/smb_hook.c | 17 +
41 drivers/net/ethernet/raeth/smb_nf.c | 177 +
42 drivers/net/ethernet/raeth/sync_write.h | 103 +
43 35 files changed, 20357 insertions(+)
44 create mode 100644 drivers/net/ethernet/raeth/Kconfig
45 create mode 100644 drivers/net/ethernet/raeth/Makefile
46 create mode 100644 drivers/net/ethernet/raeth/Makefile.release
47 create mode 100644 drivers/net/ethernet/raeth/csr_netlink.h
48 create mode 100755 drivers/net/ethernet/raeth/dvt/pkt_gen.c
49 create mode 100755 drivers/net/ethernet/raeth/dvt/pkt_gen_tcp_frag.c
50 create mode 100755 drivers/net/ethernet/raeth/dvt/pkt_gen_udp_frag.c
51 create mode 100755 drivers/net/ethernet/raeth/dvt/raether_pdma_dvt.c
52 create mode 100755 drivers/net/ethernet/raeth/dvt/raether_pdma_dvt.h
53 create mode 100644 drivers/net/ethernet/raeth/ethtool_readme.txt
54 create mode 100644 drivers/net/ethernet/raeth/mcast.c
55 create mode 100644 drivers/net/ethernet/raeth/mii_mgr.c
56 create mode 100644 drivers/net/ethernet/raeth/ra2882ethreg.h
57 create mode 100644 drivers/net/ethernet/raeth/ra_ethtool.c
58 create mode 100644 drivers/net/ethernet/raeth/ra_ethtool.h
59 create mode 100644 drivers/net/ethernet/raeth/ra_ioctl.h
60 create mode 100644 drivers/net/ethernet/raeth/ra_mac.c
61 create mode 100644 drivers/net/ethernet/raeth/ra_mac.h
62 create mode 100644 drivers/net/ethernet/raeth/ra_netlink.c
63 create mode 100644 drivers/net/ethernet/raeth/ra_netlink.h
64 create mode 100644 drivers/net/ethernet/raeth/ra_qos.c
65 create mode 100644 drivers/net/ethernet/raeth/ra_qos.h
66 create mode 100644 drivers/net/ethernet/raeth/ra_rfrw.c
67 create mode 100644 drivers/net/ethernet/raeth/ra_rfrw.h
68 create mode 100644 drivers/net/ethernet/raeth/raether.c
69 create mode 100644 drivers/net/ethernet/raeth/raether.h
70 create mode 100755 drivers/net/ethernet/raeth/raether_hwlro.c
71 create mode 100755 drivers/net/ethernet/raeth/raether_pdma.c
72 create mode 100644 drivers/net/ethernet/raeth/raether_qdma.c
73 create mode 100644 drivers/net/ethernet/raeth/raether_qdma_mt7623.c
74 create mode 100644 drivers/net/ethernet/raeth/smb_hook.c
75 create mode 100644 drivers/net/ethernet/raeth/smb_nf.c
76 create mode 100644 drivers/net/ethernet/raeth/sync_write.h
77
78 --- a/drivers/net/ethernet/Kconfig
79 +++ b/drivers/net/ethernet/Kconfig
80 @@ -17,6 +17,7 @@ config MDIO
81 config SUNGEM_PHY
82 tristate
83
84 +source "drivers/net/ethernet/raeth/Kconfig"
85 source "drivers/net/ethernet/3com/Kconfig"
86 source "drivers/net/ethernet/adaptec/Kconfig"
87 source "drivers/net/ethernet/aeroflex/Kconfig"
88 --- a/drivers/net/ethernet/Makefile
89 +++ b/drivers/net/ethernet/Makefile
90 @@ -84,3 +84,4 @@ obj-$(CONFIG_NET_VENDOR_VIA) += via/
91 obj-$(CONFIG_NET_VENDOR_WIZNET) += wiznet/
92 obj-$(CONFIG_NET_VENDOR_XILINX) += xilinx/
93 obj-$(CONFIG_NET_VENDOR_XIRCOM) += xircom/
94 +obj-$(CONFIG_RAETH) += raeth/
95 --- /dev/null
96 +++ b/drivers/net/ethernet/raeth/Kconfig
97 @@ -0,0 +1,415 @@
98 +config ARCH_MT7623
99 + bool
100 + default y
101 +
102 +config RA_NAT_NONE
103 + bool
104 + default y
105 +
106 +config RAETH
107 + tristate "Ralink GMAC"
108 + ---help---
109 + This driver supports Ralink gigabit ethernet family of
110 + adapters.
111 +
112 +config PDMA_NEW
113 + bool
114 + default y if (RALINK_MT7620 || RALINK_MT7621 || ARCH_MT7623)
115 + depends on RAETH
116 +
117 +config RAETH_SCATTER_GATHER_RX_DMA
118 + bool
119 + default y if (RALINK_MT7620 || RALINK_MT7621 || ARCH_MT7623)
120 + depends on RAETH
121 +
122 +
123 +choice
124 + prompt "Network BottomHalves"
125 + depends on RAETH
126 + default RA_NETWORK_WORKQUEUE_BH
127 +
128 + config RA_NETWORK_TASKLET_BH
129 + bool "Tasklet"
130 +
131 + config RA_NETWORK_WORKQUEUE_BH
132 + bool "Work Queue"
133 +
134 + config RAETH_NAPI
135 + bool "NAPI"
136 +
137 +endchoice
138 +
139 +#config TASKLET_WORKQUEUE_SW
140 +# bool "Tasklet and Workqueue switch"
141 +# depends on RA_NETWORK_TASKLET_BH
142 +
143 +config RAETH_SKB_RECYCLE_2K
144 + bool "SKB Recycling"
145 + depends on RAETH
146 +
147 +config RAETH_SPECIAL_TAG
148 + bool "Ralink Special Tag (0x810x)"
149 + depends on RAETH && RT_3052_ESW
150 +
151 +#config RAETH_JUMBOFRAME
152 +# bool "Jumbo Frame up to 4K bytes"
153 +# depends on RAETH && !(RALINK_RT3052 || RALINK_RT3352 || RALINK_RT5350 || RALINK_MT7628)
154 +
155 +config RAETH_CHECKSUM_OFFLOAD
156 + bool "TCP/UDP/IP checksum offload"
157 + default y
158 + depends on RAETH && !RALINK_RT2880
159 +
160 +#config RAETH_SW_FC
161 +# bool "When TX ring is full, inform kernel stop transmit and stop RX handler"
162 +# default n
163 +# depends on RAETH
164 +
165 +#config RAETH_8023AZ_EEE
166 +# bool "Enable Embeded Switch EEE"
167 +# default n
168 +# depends on RAETH && (RALINK_MT7620 || RALINK_MT7621 || RALINK_MT7628)
169 +
170 +
171 +
172 +config 32B_DESC
173 + bool "32bytes TX/RX description"
174 + default n
175 + depends on RAETH && (RALINK_MT7620 || RALINK_MT7621)
176 + ---help---
177 + At this moment, you cannot enable 32B description with Multiple RX ring at the same time.
178 +
179 +config RAETH_LRO
180 + bool "LRO (Large Receive Offload )"
181 + select INET_LRO
182 + depends on RAETH && (RALINK_RT6855A || RALINK_MT7620 || RALINK_MT7621 || ARCH_MT7623)
183 +
184 +config RAETH_HW_LRO
185 + bool "HW LRO (Large Receive Offload)"
186 + default n
187 + depends on RAETH
188 +
189 +config RAETH_HW_LRO_DBG
190 + bool "HW LRO Debug"
191 + default n
192 + depends on RAETH_HW_LRO
193 +
194 +config RAETH_HW_LRO_AUTO_ADJ_DBG
195 + bool "HW LRO Auto Adjustment Debug"
196 + default y
197 + depends on RAETH_HW_LRO
198 +
199 +config RAETH_HW_LRO_REASON_DBG
200 + bool "HW LRO Flush Reason Debug"
201 + default n
202 + depends on RAETH_HW_LRO
203 +
204 +config RAETH_HW_VLAN_TX
205 + bool "Transmit VLAN HW (DoubleVLAN is not supported)"
206 + depends on RAETH && !(RALINK_RT5350 || RALINK_MT7628)
207 + ---help---
208 + Please disable HW_VLAN_TX if you need double vlan
209 +
210 +config RAETH_HW_VLAN_RX
211 + bool "Receive VLAN HW (DoubleVLAN is not supported)"
212 + depends on RAETH && RALINK_MT7621
213 + ---help---
214 + Please disable HW_VLAN_RX if you need double vlan
215 +
216 +config RAETH_TSO
217 + bool "TSOV4 (Tcp Segmentaton Offload)"
218 + depends on (RAETH_HW_VLAN_TX && (RALINK_RT6855 || RALINK_RT6855A || RALINK_MT7620))||((RALINK_MT7621 || ARCH_MT7623) &&(RAETH_HW_VLAN_TX || RAETH_GMAC2 ))
219 +
220 +config RAETH_TSOV6
221 + bool "TSOV6 (Tcp Segmentaton Offload)"
222 + depends on RAETH_TSO
223 +
224 +config RAETH_RW_PDMAPTR_FROM_VAR
225 + bool
226 + default y if RALINK_RT6855A || RALINK_MT7620
227 + depends on RAETH
228 +
229 +config MTK_SMB_HOOK
230 + bool "Samba Speedup Module"
231 + depends on RAETH
232 +
233 +config SPLICE_NET_SUPPORT
234 + default y if MTK_SMB_HOOK
235 + depends on MTK_SMB_HOOK
236 + bool
237 +
238 +
239 +config RAETH_DVT
240 + bool "RAETH DVT"
241 + depends on RAETH && (RALINK_MT7621 || ARCH_MT7623)
242 +
243 +config RAETH_PDMA_DVT
244 + bool "PDMA DVT"
245 + depends on RAETH_DVT
246 +
247 +config RAETH_PDMA_LEGACY_MODE
248 + bool "PDMA legacy mode"
249 + depends on RAETH_PDMA_DVT
250 +
251 +#config RAETH_QOS
252 +# bool "QoS Feature"
253 +# depends on RAETH && !RALINK_RT2880 && !RALINK_MT7620 && !RALINK_MT7621 && !RAETH_TSO
254 +
255 +choice
256 + prompt "QoS Type"
257 + depends on RAETH_QOS
258 + default DSCP_QOS_DSCP
259 +
260 +config RAETH_QOS_DSCP_BASED
261 + bool "DSCP-based"
262 + depends on RAETH_QOS
263 +
264 +config RAETH_QOS_VPRI_BASED
265 + bool "VPRI-based"
266 + depends on RAETH_QOS
267 +
268 +endchoice
269 +
270 +config RAETH_QDMA
271 + bool "Choose QDMA instead PDMA"
272 + default n
273 + depends on RAETH && (RALINK_MT7621 || ARCH_MT7623)
274 +
275 +config RAETH_QDMATX_QDMARX
276 + bool "Choose QDMA RX instead PDMA RX"
277 + default n
278 + depends on RAETH_QDMA && !RALINK_MT7621
279 +
280 +
281 +
282 +choice
283 + prompt "GMAC is connected to"
284 + depends on RAETH
285 + default GE1_RGMII_FORCE_1000
286 +
287 +config GE1_MII_FORCE_100
288 + bool "MII_FORCE_100 (10/100M Switch)"
289 + depends on (RALINK_RT2880 || RALINK_RT3883 || RALINK_MT7621)
290 +
291 +config GE1_MII_AN
292 + bool "MII_AN (100Phy)"
293 + depends on (RALINK_RT2880 || RALINK_RT3883 || RALINK_MT7621)
294 +
295 +config GE1_RVMII_FORCE_100
296 + bool "RvMII_FORCE_100 (CPU)"
297 + depends on (RALINK_RT2880 || RALINK_RT3883 || RALINK_MT7621)
298 +
299 +config GE1_RGMII_FORCE_1000
300 + bool "RGMII_FORCE_1000 (GigaSW, CPU)"
301 + depends on (RALINK_RT2880 || RALINK_RT3883)
302 + select RALINK_SPI
303 +
304 +config GE1_RGMII_FORCE_1000
305 + bool "RGMII_FORCE_1000 (GigaSW, CPU)"
306 + depends on (RALINK_MT7621 || ARCH_MT7623)
307 + select RT_3052_ESW
308 +
309 +config GE1_TRGMII_FORCE_1200
310 + bool "TRGMII_FORCE_1200 (GigaSW, CPU)"
311 + depends on (RALINK_MT7621)
312 + select RT_3052_ESW
313 +
314 +config GE1_TRGMII_FORCE_2000
315 + bool "TRGMII_FORCE_2000 (GigaSW, CPU, for MT7623 and MT7683)"
316 + depends on (ARCH_MT7623)
317 + select RT_3052_ESW
318 +
319 +config GE1_TRGMII_FORCE_2600
320 + bool "TRGMII_FORCE_2600 (GigaSW, CPU, MT7623 only)"
321 + depends on (ARCH_MT7623)
322 + select RT_3052_ESW
323 +
324 +config GE1_RGMII_AN
325 + bool "RGMII_AN (GigaPhy)"
326 + depends on (RALINK_RT2880 || RALINK_RT3883 || RALINK_MT7621 || ARCH_MT7623)
327 +
328 +config GE1_RGMII_NONE
329 + bool "NONE (NO CONNECT)"
330 + depends on (RALINK_MT7621 || ARCH_MT7623)
331 +
332 +endchoice
333 +
334 +config HW_SFQ
335 + bool "HW_SFQ"
336 + default n
337 + depends on RAETH_QDMA && (ARCH_MT7623)
338 +
339 +
340 +config RT_3052_ESW
341 + bool "Ralink Embedded Switch"
342 + default y
343 + depends on RAETH && (RALINK_RT3052 || RALINK_RT3352 || RALINK_RT5350 || RALINK_RT6855 || RALINK_RT6855A || RALINK_MT7620 || RALINK_MT7621 || RALINK_MT7628 || ARCH_MT7623)
344 +
345 +config LAN_WAN_SUPPORT
346 + bool "LAN/WAN Partition"
347 + depends on RAETH && (RAETH_ROUTER || RT_3052_ESW)
348 +
349 +config ETH_MEMORY_OPTIMIZATION
350 + bool "Ethernet memory optimization"
351 + depends on RALINK_MT7628
352 +
353 +config ETH_ONE_PORT_ONLY
354 + bool "One Port Only"
355 + depends on RALINK_MT7628
356 +
357 +choice
358 + prompt "Switch Board Layout Type"
359 + depends on LAN_WAN_SUPPORT || P5_RGMII_TO_MAC_MODE || GE1_RGMII_FORCE_1000 || GE1_TRGMII_FORCE_1200 || GE2_RGMII_FORCE_1000
360 + default WAN_AT_P0
361 +
362 + config WAN_AT_P4
363 + bool "LLLL/W"
364 +
365 + config WAN_AT_P0
366 + bool "W/LLLL"
367 +endchoice
368 +
369 +config RALINK_VISTA_BASIC
370 + bool 'Vista Basic Logo for IC+ 175C'
371 + depends on LAN_WAN_SUPPORT && (RALINK_RT2880 || RALINK_RT3883)
372 +
373 +config ESW_DOUBLE_VLAN_TAG
374 + bool
375 + default y if RT_3052_ESW
376 +
377 +config RAETH_HAS_PORT4
378 + bool "Port 4 Support"
379 + depends on RAETH && RALINK_MT7620
380 +choice
381 + prompt "Target Mode"
382 + depends on RAETH_HAS_PORT4
383 + default P4_RGMII_TO_MAC_MODE
384 +
385 + config P4_MAC_TO_PHY_MODE
386 + bool "Giga_Phy (RGMII)"
387 + config GE_RGMII_MT7530_P0_AN
388 + bool "GE_RGMII_MT7530_P0_AN (MT7530 Internal GigaPhy)"
389 + config GE_RGMII_MT7530_P4_AN
390 + bool "GE_RGMII_MT7530_P4_AN (MT7530 Internal GigaPhy)"
391 + config P4_RGMII_TO_MAC_MODE
392 + bool "Giga_SW/iNIC (RGMII)"
393 + config P4_MII_TO_MAC_MODE
394 + bool "External_CPU (MII_RvMII)"
395 + config P4_RMII_TO_MAC_MODE
396 + bool "External_CPU (RvMII_MII)"
397 +endchoice
398 +
399 +config MAC_TO_GIGAPHY_MODE_ADDR2
400 + hex "Port4 Phy Address"
401 + default 0x4
402 + depends on P4_MAC_TO_PHY_MODE
403 +
404 +config RAETH_HAS_PORT5
405 + bool "Port 5 Support"
406 + depends on RAETH && (RALINK_RT3052 || RALINK_RT3352 || RALINK_RT6855 || RALINK_RT6855A || RALINK_MT7620)
407 +choice
408 + prompt "Target Mode"
409 + depends on RAETH_HAS_PORT5
410 + default P5_RGMII_TO_MAC_MODE
411 +
412 + config P5_MAC_TO_PHY_MODE
413 + bool "Giga_Phy (RGMII)"
414 + config P5_RGMII_TO_MAC_MODE
415 + bool "Giga_SW/iNIC (RGMII)"
416 + config P5_RGMII_TO_MT7530_MODE
417 + bool "MT7530 Giga_SW (RGMII)"
418 + depends on RALINK_MT7620
419 + config P5_MII_TO_MAC_MODE
420 + bool "External_CPU (MII_RvMII)"
421 + config P5_RMII_TO_MAC_MODE
422 + bool "External_CPU (RvMII_MII)"
423 +endchoice
424 +
425 +config MAC_TO_GIGAPHY_MODE_ADDR
426 + hex "GE1 Phy Address"
427 + default 0x1F
428 + depends on GE1_MII_AN || GE1_RGMII_AN
429 +
430 +config MAC_TO_GIGAPHY_MODE_ADDR
431 + hex "Port5 Phy Address"
432 + default 0x5
433 + depends on P5_MAC_TO_PHY_MODE
434 +
435 +config RAETH_GMAC2
436 + bool "GMAC2 Support"
437 + depends on RAETH && (RALINK_RT3883 || RALINK_MT7621 || ARCH_MT7623)
438 +
439 +choice
440 + prompt "GMAC2 is connected to"
441 + depends on RAETH_GMAC2
442 + default GE2_RGMII_AN
443 +
444 +config GE2_MII_FORCE_100
445 + bool "MII_FORCE_100 (10/100M Switch)"
446 + depends on RAETH_GMAC2
447 +
448 +config GE2_MII_AN
449 + bool "MII_AN (100Phy)"
450 + depends on RAETH_GMAC2
451 +
452 +config GE2_RVMII_FORCE_100
453 + bool "RvMII_FORCE_100 (CPU)"
454 + depends on RAETH_GMAC2
455 +
456 +config GE2_RGMII_FORCE_1000
457 + bool "RGMII_FORCE_1000 (GigaSW, CPU)"
458 + depends on RAETH_GMAC2
459 + select RALINK_SPI
460 +
461 +config GE2_RGMII_AN
462 + bool "RGMII_AN (External GigaPhy)"
463 + depends on RAETH_GMAC2
464 +
465 +config GE2_INTERNAL_GPHY
466 + bool "RGMII_AN (Internal GigaPny)"
467 + depends on RAETH_GMAC2
468 + select LAN_WAN_SUPPORT
469 +
470 +endchoice
471 +
472 +config GE_RGMII_INTERNAL_P0_AN
473 + bool
474 + depends on GE2_INTERNAL_GPHY
475 + default y if WAN_AT_P0
476 +
477 +config GE_RGMII_INTERNAL_P4_AN
478 + bool
479 + depends on GE2_INTERNAL_GPHY
480 + default y if WAN_AT_P4
481 +
482 +config MAC_TO_GIGAPHY_MODE_ADDR2
483 + hex
484 + default 0 if GE_RGMII_INTERNAL_P0_AN
485 + default 4 if GE_RGMII_INTERNAL_P4_AN
486 + depends on GE_RGMII_INTERNAL_P0_AN || GE_RGMII_INTERNAL_P4_AN
487 +
488 +config MAC_TO_GIGAPHY_MODE_ADDR2
489 + hex "GE2 Phy Address"
490 + default 0x1E
491 + depends on GE2_MII_AN || GE2_RGMII_AN
492 +
493 +#force 100M
494 +config RAETH_ROUTER
495 +bool
496 +default y if GE1_MII_FORCE_100 || GE2_MII_FORCE_100 || GE1_RVMII_FORCE_100 || GE2_RVMII_FORCE_100
497 +
498 +#force 1000M
499 +config MAC_TO_MAC_MODE
500 +bool
501 +default y if GE1_RGMII_FORCE_1000 || GE2_RGMII_FORCE_1000
502 +depends on (RALINK_RT2880 || RALINK_RT3883)
503 +
504 +#AN
505 +config GIGAPHY
506 +bool
507 +default y if GE1_RGMII_AN || GE2_RGMII_AN
508 +
509 +#AN
510 +config 100PHY
511 +bool
512 +default y if GE1_MII_AN || GE2_MII_AN
513 --- /dev/null
514 +++ b/drivers/net/ethernet/raeth/Makefile
515 @@ -0,0 +1,67 @@
516 +obj-$(CONFIG_RAETH) += raeth.o
517 +raeth-objs := ra_mac.o mii_mgr.o ra_rfrw.o
518 +
519 +ifeq ($(CONFIG_MTK_SMB_HOOK),y)
520 +obj-y += smb_hook.o
521 +obj-m += smb.o
522 +smb-objs := smb_nf.o
523 +endif
524 +
525 +#EXTRA_CFLAGS += -DCONFIG_RAETH_MULTIPLE_RX_RING
526 +
527 +ifeq ($(CONFIG_RAETH_QOS),y)
528 +raeth-objs += ra_qos.o
529 +endif
530 +
531 +ifeq ($(CONFIG_RAETH_QDMA),y)
532 +raeth-objs += raether_qdma.o
533 +endif
534 +
535 +ifneq ($(CONFIG_RAETH_QDMA),y)
536 +raeth-objs += raether_pdma.o
537 +endif
538 +
539 +raeth-objs += raether.o
540 +
541 +ifeq ($(CONFIG_ETHTOOL),y)
542 +raeth-objs += ra_ethtool.o
543 +endif
544 +
545 +ifeq ($(CONFIG_RALINK_RT3052_MP2),y)
546 +raeth-objs += mcast.o
547 +endif
548 +
549 +ifeq ($(CONFIG_RAETH_NETLINK),y)
550 +raeth-objs += ra_netlink.o
551 +endif
552 +
553 +ifeq ($(CONFIG_RAETH_PDMA_DVT),y)
554 +raeth-objs += dvt/raether_pdma_dvt.o
555 +obj-m += dvt/pkt_gen.o
556 +obj-m += dvt/pkt_gen_udp_frag.o
557 +obj-m += dvt/pkt_gen_tcp_frag.o
558 +endif
559 +
560 +ifeq ($(CONFIG_RAETH_HW_LRO),y)
561 +raeth-objs += raether_hwlro.o
562 +endif
563 +
564 +ifeq ($(CONFIG_RAETH_GMAC2),y)
565 +EXTRA_CFLAGS += -DCONFIG_PSEUDO_SUPPORT
566 +endif
567 +
568 +ifeq ($(CONFIG_ETH_MEMORY_OPTIMIZATION),y)
569 +EXTRA_CFLAGS += -DMEMORY_OPTIMIZATION
570 +endif
571 +
572 +ifeq ($(CONFIG_RT2860V2_AP_MEMORY_OPTIMIZATION),y)
573 +EXTRA_CFLAGS += -DMEMORY_OPTIMIZATION
574 +endif
575 +
576 +ifeq ($(CONFIG_RA_NETWORK_WORKQUEUE_BH),y)
577 +EXTRA_CFLAGS += -DWORKQUEUE_BH
578 +endif
579 +
580 +ifeq ($(CONFIG_TASKLET_WORKQUEUE_SW),y)
581 +EXTRA_CFLAGS += -DTASKLET_WORKQUEUE_SW
582 +endif
583 --- /dev/null
584 +++ b/drivers/net/ethernet/raeth/Makefile.release
585 @@ -0,0 +1,60 @@
586 +obj-$(CONFIG_RAETH) += raeth.o
587 +raeth-objs := ra_mac.o mii_mgr.o ra_rfrw.o
588 +
589 +ifeq ($(CONFIG_MTK_SMB_HOOK),y)
590 +obj-y += smb_hook.o
591 +obj-m += smb.o
592 +smb-objs := smb_nf.o
593 +endif
594 +
595 +#EXTRA_CFLAGS += -DCONFIG_RAETH_MULTIPLE_RX_RING
596 +
597 +ifeq ($(CONFIG_RAETH_QOS),y)
598 +raeth-objs += ra_qos.o
599 +endif
600 +
601 +ifeq ($(CONFIG_RAETH_QDMA),y)
602 +raeth-objs += raether_qdma.o
603 +endif
604 +
605 +ifneq ($(CONFIG_RAETH_QDMA),y)
606 +raeth-objs += raether_pdma.o
607 +endif
608 +
609 +raeth-objs += raether.o
610 +
611 +ifeq ($(CONFIG_ETHTOOL),y)
612 +raeth-objs += ra_ethtool.o
613 +endif
614 +
615 +ifeq ($(CONFIG_RALINK_RT3052_MP2),y)
616 +raeth-objs += mcast.o
617 +endif
618 +
619 +ifeq ($(CONFIG_RAETH_NETLINK),y)
620 +raeth-objs += ra_netlink.o
621 +endif
622 +
623 +ifeq ($(CONFIG_RAETH_HW_LRO),y)
624 +raeth-objs += raether_hwlro.o
625 +endif
626 +
627 +ifeq ($(CONFIG_RAETH_GMAC2),y)
628 +EXTRA_CFLAGS += -DCONFIG_PSEUDO_SUPPORT
629 +endif
630 +
631 +ifeq ($(CONFIG_ETH_MEMORY_OPTIMIZATION),y)
632 +EXTRA_CFLAGS += -DMEMORY_OPTIMIZATION
633 +endif
634 +
635 +ifeq ($(CONFIG_RT2860V2_AP_MEMORY_OPTIMIZATION),y)
636 +EXTRA_CFLAGS += -DMEMORY_OPTIMIZATION
637 +endif
638 +
639 +ifeq ($(CONFIG_RA_NETWORK_WORKQUEUE_BH),y)
640 +EXTRA_CFLAGS += -DWORKQUEUE_BH
641 +endif
642 +
643 +ifeq ($(CONFIG_TASKLET_WORKQUEUE_SW),y)
644 +EXTRA_CFLAGS += -DTASKLET_WORKQUEUE_SW
645 +endif
646 --- /dev/null
647 +++ b/drivers/net/ethernet/raeth/csr_netlink.h
648 @@ -0,0 +1,27 @@
649 +#ifndef CSR_NETLINK_H
650 +#define CSR_NETLINK_H
651 +
652 +#define CSR_NETLINK 30
653 +#define CSR_READ 0
654 +#define CSR_WRITE 1
655 +#define CSR_TEST 2
656 +
657 +#define RALINK_CSR_GROUP 2882
658 +
659 +typedef struct rt2880_csr_msg {
660 + int enable;
661 + char reg_name[32];
662 + unsigned long address;
663 + unsigned long default_value;
664 + unsigned long reserved_bits; /* 1 : not reserved, 0 : reserved */
665 + unsigned long write_mask;
666 + unsigned long write_value;
667 + int status;
668 +} CSR_MSG;
669 +
670 +int csr_msg_send(CSR_MSG* msg);
671 +int csr_msg_recv(void);
672 +
673 +// static CSR_MSG input_csr_msg;
674 +
675 +#endif
676 --- /dev/null
677 +++ b/drivers/net/ethernet/raeth/dvt/pkt_gen.c
678 @@ -0,0 +1,88 @@
679 +//#include <linux/config.h>
680 +#include <linux/version.h>
681 +#include <linux/module.h>
682 +#include <linux/skbuff.h>
683 +#include <linux/kernel.h>
684 +#include <linux/init.h>
685 +#include <linux/netfilter.h>
686 +#include <linux/netdevice.h>
687 +#include <linux/types.h>
688 +#include <asm/uaccess.h>
689 +#include <linux/moduleparam.h>
690 +
691 +char *ifname="eth3";
692 +
693 +static int32_t PktGenInitMod(void)
694 +{
695 +
696 + struct net_dev *dev;
697 + struct sk_buff *skb;
698 + int i=0;
699 +
700 + unsigned char pkt[]={
701 + //0xff, 0xff, 0xff, 0xff, 0xff, 0xff, // dest bcast mac
702 + 0x00, 0x21, 0x86, 0xee, 0xe3, 0x95, // dest macA
703 + //0x00, 0x30, 0xdb, 0x02, 0x02, 0x01, // dest macB
704 + 0x00, 0x0c, 0x43, 0x28, 0x80, 0x33, // src mac
705 + 0x81, 0x00, // vlan tag
706 + //0x81, 0x10, // vlan tag
707 + //0x87, 0x39, // do not learn
708 + //0xc1, 0x03, // vlan tag SA=0, VID=2, LV=1
709 + 0x00, 0x03, // pri=0, vlan=3
710 + 0x08, 0x00, // eth type=ip
711 + 0x45, 0x00, 0x00, 0x30, 0x12, 0x34, 0x40, 0x00, 0xff, 0x06,
712 + 0x40, 0x74, 0x0a, 0x0a, 0x1e, 0x0a, 0x0a, 0x0a, 0x1e, 0x0b,
713 + 0x00, 0x1e, 0x00, 0x28, 0x00, 0x1c, 0x81, 0x06, 0x00, 0x00,
714 + 0x00, 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
715 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
716 +
717 + skb = alloc_skb(256, GFP_ATOMIC);
718 +
719 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
720 + if((dev=dev_get_by_name(&init_net,ifname))){
721 +#else
722 + if((dev=dev_get_by_name(ifname))){
723 +#endif
724 +
725 +
726 +
727 + skb->dev=dev;
728 + skb_put(skb,sizeof(pkt));
729 + memcpy(skb->data, pkt, sizeof(pkt));
730 +
731 + printk("send pkt(len=%d) to %s\n", skb->len, skb->dev->name);
732 +
733 +
734 + for(i=0;i<sizeof(pkt);i++){
735 + if(i%16==0) {
736 + printk("\n");
737 + }
738 + printk("%02X-",skb->data[i]);
739 + }
740 +
741 + dev_queue_xmit(skb);
742 + }else{
743 + printk("interface %s not found\n",ifname);
744 + return 1;
745 + }
746 +
747 + return 0;
748 +}
749 +
750 +static void PktGenCleanupMod(void)
751 +{
752 +}
753 +
754 +module_init(PktGenInitMod);
755 +module_exit(PktGenCleanupMod);
756 +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,12)
757 +MODULE_PARM (ifname, "s");
758 +#else
759 +module_param (ifname, charp, 0);
760 +#endif
761 +
762 +MODULE_DESCRIPTION("Ralink PktGen Module");
763 +MODULE_AUTHOR("Steven Liu");
764 +MODULE_LICENSE("Proprietary");
765 +MODULE_PARM_DESC (ifname, "interface name");
766 +
767 --- /dev/null
768 +++ b/drivers/net/ethernet/raeth/dvt/pkt_gen_tcp_frag.c
769 @@ -0,0 +1,138 @@
770 +//#include <linux/config.h>
771 +#include <linux/version.h>
772 +#include <linux/module.h>
773 +#include <linux/skbuff.h>
774 +#include <linux/kernel.h>
775 +#include <linux/init.h>
776 +#include <linux/netfilter.h>
777 +#include <linux/netdevice.h>
778 +#include <linux/types.h>
779 +#include <asm/uaccess.h>
780 +#include <linux/moduleparam.h>
781 +
782 +char *ifname="eth3";
783 +
784 +
785 +static int32_t PktGenInitMod(void)
786 +{
787 + unsigned char pkt_1[]={
788 + 0x00, 0x21, 0x86, 0xee, 0xe3, 0x90, // dest mac
789 + 0x00, 0x0c, 0x43, 0x28, 0x80, 0x33, // src mac
790 + 0x08, 0x00, // type: ip
791 + 0x45, 0x00, 0x00, 0x34, // ip: ..., total len (0x034 = 52)
792 + 0xa1, 0x78, 0x20, 0x00, // ip: id, frag, frag offset
793 + 0x80, 0x06, 0x63, 0x07, // ip: ttl, protocol, hdr checksum (0x6307)
794 + 0x0a, 0x0a, 0x1e, 0x7b, // src ip (10.10.30.123)
795 + 0x0a, 0x0a, 0x1e, 0x05, // dst ip (10.10.30.5)
796 + 0x0d, 0xd5, //tcp src port
797 + 0x13, 0x89, //tcp dst port
798 + 0x40, 0xf5, 0x15, 0x04, //tcp sequence number
799 + 0xf6, 0x4f, 0x1e, 0x31, //tcp ack number
800 + 0x50, 0x10, 0xfc, 0x00, //tcp flags, win size
801 + 0xf1, 0xfe, 0x00, 0x00, //tcp checksum (0xf1fe)
802 + 0x01, 0x02, 0x03, 0x04, 0x05, //payload (12 bytes)
803 + 0x06, 0x07, 0x08, 0x09, 0x0a,
804 + 0x0b, 0x0c
805 + };
806 +
807 + unsigned char pkt_2[]={
808 + 0x00, 0x21, 0x86, 0xee, 0xe3, 0x90, // dest mac
809 + 0x00, 0x0c, 0x43, 0x28, 0x80, 0x33, // src mac
810 + 0x08, 0x00, // type: ip
811 + 0x45, 0x00, 0x00, 0x20, // ip: ..., total len (0x020 = 32)
812 + 0xa1, 0x78, 0x00, 0x04, // ip: id, frag, frag offset (32)
813 + 0x40, 0x11, 0x63, 0x07, // ip: ttl, protocol, hdr checksum (0x6307)
814 + 0x0a, 0x0a, 0x1e, 0x7b, // src ip (10.10.30.123)
815 + 0x0a, 0x0a, 0x1e, 0x05, // dst ip (10.10.30.5)
816 + 0x11, 0x12, 0x13, 0x14, 0x15, //payload (12 bytes)
817 + 0x16, 0x17, 0x18, 0x19, 0x1a,
818 + 0x1b, 0x1c
819 + };
820 +
821 + struct net_dev *dev;
822 + struct sk_buff *skb_1;
823 + struct sk_buff *skb_2;
824 + int i=0;
825 +
826 + skb_1 = alloc_skb(256, GFP_ATOMIC);
827 + skb_2 = alloc_skb(256, GFP_ATOMIC);
828 +
829 +
830 +#if 1
831 +/* send packet 1 */
832 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
833 + if((dev=dev_get_by_name(&init_net,ifname))){
834 +#else
835 + if((dev=dev_get_by_name(ifname))){
836 +#endif
837 +
838 + skb_1->dev=dev;
839 + skb_put(skb_1,sizeof(pkt_1));
840 + memcpy(skb_1->data, pkt_1, sizeof(pkt_1));
841 +
842 + printk("send pkt(len=%d) to %s\n", skb_1->len, skb_1->dev->name);
843 +
844 +
845 + for(i=0;i<sizeof(pkt_1);i++){
846 + if(i%16==0) {
847 + printk("\n");
848 + }
849 + printk("%02X-",skb_1->data[i]);
850 + }
851 +
852 + dev_queue_xmit(skb_1);
853 + }else{
854 + printk("interface %s not found\n",ifname);
855 + return 1;
856 + }
857 +#endif
858 +
859 +#if 1
860 +/* send packet 2 */
861 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
862 + if((dev=dev_get_by_name(&init_net,ifname))){
863 +#else
864 + if((dev=dev_get_by_name(ifname))){
865 +#endif
866 +
867 + skb_2->dev=dev;
868 + skb_put(skb_2,sizeof(pkt_2));
869 + memcpy(skb_2->data, pkt_2, sizeof(pkt_2));
870 +
871 + printk("send pkt(len=%d) to %s\n", skb_2->len, skb_2->dev->name);
872 +
873 +
874 + for(i=0;i<sizeof(pkt_2);i++){
875 + if(i%16==0) {
876 + printk("\n");
877 + }
878 + printk("%02X-",skb_2->data[i]);
879 + }
880 +
881 + dev_queue_xmit(skb_2);
882 + }else{
883 + printk("interface %s not found\n",ifname);
884 + return 1;
885 + }
886 +#endif
887 +
888 + return 0;
889 +}
890 +
891 +static void PktGenCleanupMod(void)
892 +{
893 +}
894 +
895 +module_init(PktGenInitMod);
896 +module_exit(PktGenCleanupMod);
897 +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,12)
898 +MODULE_PARM (ifname, "s");
899 +#else
900 +module_param (ifname, charp, 0);
901 +#endif
902 +
903 +MODULE_DESCRIPTION("Ralink PktGen Module");
904 +MODULE_AUTHOR("Steven Liu");
905 +MODULE_LICENSE("Proprietary");
906 +MODULE_PARM_DESC (ifname, "interface name");
907 +
908 --- /dev/null
909 +++ b/drivers/net/ethernet/raeth/dvt/pkt_gen_udp_frag.c
910 @@ -0,0 +1,191 @@
911 +//#include <linux/config.h>
912 +#include <linux/version.h>
913 +#include <linux/module.h>
914 +#include <linux/skbuff.h>
915 +#include <linux/kernel.h>
916 +#include <linux/init.h>
917 +#include <linux/netfilter.h>
918 +#include <linux/netdevice.h>
919 +#include <linux/types.h>
920 +#include <asm/uaccess.h>
921 +#include <linux/moduleparam.h>
922 +
923 +char *ifname="eth3";
924 +
925 +
926 +static int32_t PktGenInitMod(void)
927 +{
928 +#if 0
929 + unsigned char pkt_0[]={
930 +// 0x00, 0x21, 0x86, 0xee, 0xe3, 0x95, // dest mac
931 + 0x00, 0x21, 0x86, 0xee, 0xe3, 0x90, // dest mac
932 + 0x00, 0x0c, 0x43, 0x28, 0x80, 0x33, // src mac
933 + 0x08, 0x00, // type: ip
934 + 0x45, 0x00, 0x00, 0x26, // ip: ..., total len (0x026 = 38)
935 +// 0xa1, 0x78, 0x20, 0x00, // ip: id, frag, frag offset
936 + 0xa1, 0x78, 0x40, 0x00, // ip: id, frag, frag offset
937 + 0x40, 0x11, 0x63, 0x07, // ip: ttl, protocol, hdr checksum (0x6307)
938 + 0x0a, 0x0a, 0x1e, 0x7b, // src ip (10.10.30.123)
939 +// 0x0a, 0x0a, 0x1e, 0x03, // dst ip (10.10.30.3)
940 + 0x0a, 0x0a, 0x1e, 0x05, // dst ip (10.10.30.5)
941 + 0xca, 0x7b, //udp src port
942 + 0x13, 0x89, //udp dst port
943 + 0x00, 0x12, //udp len (0x01c = 18)
944 + 0x2f, 0x96, //udp checksum (0x2f96)
945 + 0x01, 0x02, 0x03, 0x04, 0x05, //payload (10 bytes)
946 + 0x06, 0x07, 0x08, 0x09, 0x0a
947 + };
948 +#endif
949 +
950 + unsigned char pkt_1[]={
951 +// 0x00, 0x21, 0x86, 0xee, 0xe3, 0x95, // dest mac
952 + 0x00, 0x21, 0x86, 0xee, 0xe3, 0x90, // dest mac
953 + 0x00, 0x0c, 0x43, 0x28, 0x80, 0x33, // src mac
954 + 0x08, 0x00, // type: ip
955 + 0x45, 0x00, 0x00, 0x24, // ip: ..., total len (0x024 = 36)
956 + 0xa1, 0x78, 0x20, 0x00, // ip: id, frag, frag offset
957 +// 0xa1, 0x78, 0x40, 0x00, // ip: id, frag, frag offset
958 + 0x40, 0x11, 0x63, 0x07, // ip: ttl, protocol, hdr checksum (0x6307)
959 + 0x0a, 0x0a, 0x1e, 0x7b, // src ip (10.10.30.123)
960 +// 0x0a, 0x0a, 0x1e, 0x03, // dst ip (10.10.30.3)
961 + 0x0a, 0x0a, 0x1e, 0x05, // dst ip (10.10.30.5)
962 + 0xca, 0x7b, //udp src port
963 + 0x13, 0x89, //udp dst port
964 + 0x00, 0x1a, //udp len (0x01a = 26)
965 + 0x2f, 0x96, //udp checksum (0x2f96)
966 + 0x01, 0x02, 0x03, 0x04, 0x05, //payload (8 bytes)
967 + 0x06, 0x07, 0x08
968 + };
969 +
970 + unsigned char pkt_2[]={
971 +// 0x00, 0x21, 0x86, 0xee, 0xe3, 0x95, // dest mac
972 + 0x00, 0x21, 0x86, 0xee, 0xe3, 0x90, // dest mac
973 + 0x00, 0x0c, 0x43, 0x28, 0x80, 0x33, // src mac
974 + 0x08, 0x00, // type: ip
975 + 0x45, 0x00, 0x00, 0x1e, // ip: ..., total len (0x01e = 30)
976 + 0xa1, 0x78, 0x00, 0x02, // ip: id, frag, frag offset (16)
977 + 0x40, 0x11, 0x63, 0x07, // ip: ttl, protocol, hdr checksum (0x6307)
978 + 0x0a, 0x0a, 0x1e, 0x7b, // src ip (10.10.30.123)
979 +// 0x0a, 0x0a, 0x1e, 0x03, // dst ip (10.10.30.3)
980 + 0x0a, 0x0a, 0x1e, 0x05, // dst ip (10.10.30.5)
981 + 0x11, 0x12, 0x13, 0x14, 0x15, //payload (10 bytes)
982 + 0x16, 0x17, 0x18, 0x19, 0x1a
983 + };
984 +
985 + struct net_dev *dev;
986 +// struct sk_buff *skb_0;
987 + struct sk_buff *skb_1;
988 + struct sk_buff *skb_2;
989 + int i=0;
990 +
991 +// skb_0 = alloc_skb(256, GFP_ATOMIC);
992 + skb_1 = alloc_skb(256, GFP_ATOMIC);
993 + skb_2 = alloc_skb(256, GFP_ATOMIC);
994 +
995 +#if 0
996 +/* send packet 0 */
997 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
998 + if((dev=dev_get_by_name(&init_net,ifname))){
999 +#else
1000 + if((dev=dev_get_by_name(ifname))){
1001 +#endif
1002 +
1003 + skb_0->dev=dev;
1004 + skb_put(skb_0,sizeof(pkt_0));
1005 + memcpy(skb_0->data, pkt_0, sizeof(pkt_0));
1006 +
1007 + printk("send pkt(len=%d) to %s\n", skb_0->len, skb_0->dev->name);
1008 +
1009 +
1010 + for(i=0;i<sizeof(pkt_0);i++){
1011 + if(i%16==0) {
1012 + printk("\n");
1013 + }
1014 + printk("%02X-",skb_0->data[i]);
1015 + }
1016 +
1017 + dev_queue_xmit(skb_0);
1018 + }else{
1019 + printk("interface %s not found\n",ifname);
1020 + return 1;
1021 + }
1022 +#endif
1023 +
1024 +#if 1
1025 +/* send packet 1 */
1026 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
1027 + if((dev=dev_get_by_name(&init_net,ifname))){
1028 +#else
1029 + if((dev=dev_get_by_name(ifname))){
1030 +#endif
1031 +
1032 + skb_1->dev=dev;
1033 + skb_put(skb_1,sizeof(pkt_1));
1034 + memcpy(skb_1->data, pkt_1, sizeof(pkt_1));
1035 +
1036 + printk("send pkt(len=%d) to %s\n", skb_1->len, skb_1->dev->name);
1037 +
1038 +
1039 + for(i=0;i<sizeof(pkt_1);i++){
1040 + if(i%16==0) {
1041 + printk("\n");
1042 + }
1043 + printk("%02X-",skb_1->data[i]);
1044 + }
1045 +
1046 + dev_queue_xmit(skb_1);
1047 + }else{
1048 + printk("interface %s not found\n",ifname);
1049 + return 1;
1050 + }
1051 +#endif
1052 +
1053 +#if 1
1054 +/* send packet 2 */
1055 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
1056 + if((dev=dev_get_by_name(&init_net,ifname))){
1057 +#else
1058 + if((dev=dev_get_by_name(ifname))){
1059 +#endif
1060 +
1061 + skb_2->dev=dev;
1062 + skb_put(skb_2,sizeof(pkt_2));
1063 + memcpy(skb_2->data, pkt_2, sizeof(pkt_2));
1064 +
1065 + printk("send pkt(len=%d) to %s\n", skb_2->len, skb_2->dev->name);
1066 +
1067 +
1068 + for(i=0;i<sizeof(pkt_2);i++){
1069 + if(i%16==0) {
1070 + printk("\n");
1071 + }
1072 + printk("%02X-",skb_2->data[i]);
1073 + }
1074 +
1075 + dev_queue_xmit(skb_2);
1076 + }else{
1077 + printk("interface %s not found\n",ifname);
1078 + return 1;
1079 + }
1080 +#endif
1081 +
1082 + return 0;
1083 +}
1084 +
1085 +static void PktGenCleanupMod(void)
1086 +{
1087 +}
1088 +
1089 +module_init(PktGenInitMod);
1090 +module_exit(PktGenCleanupMod);
1091 +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,12)
1092 +MODULE_PARM (ifname, "s");
1093 +#else
1094 +module_param (ifname, charp, 0);
1095 +#endif
1096 +
1097 +MODULE_DESCRIPTION("Ralink PktGen Module");
1098 +MODULE_AUTHOR("Steven Liu");
1099 +MODULE_LICENSE("Proprietary");
1100 +MODULE_PARM_DESC (ifname, "interface name");
1101 +
1102 --- /dev/null
1103 +++ b/drivers/net/ethernet/raeth/dvt/raether_pdma_dvt.c
1104 @@ -0,0 +1,1527 @@
1105 +#include <linux/module.h>
1106 +#include <linux/version.h>
1107 +#include <linux/kernel.h>
1108 +#include <linux/types.h>
1109 +#include <linux/pci.h>
1110 +#include <linux/init.h>
1111 +#include <linux/skbuff.h>
1112 +#include <linux/if_vlan.h>
1113 +#include <linux/if_ether.h>
1114 +#include <linux/fs.h>
1115 +#include <asm/uaccess.h>
1116 +#include <asm/rt2880/surfboardint.h>
1117 +#if defined(CONFIG_RAETH_TSO)
1118 +#include <linux/tcp.h>
1119 +#include <net/ipv6.h>
1120 +#include <linux/ip.h>
1121 +#include <net/ip.h>
1122 +#include <net/tcp.h>
1123 +#include <linux/in.h>
1124 +#include <linux/ppp_defs.h>
1125 +#include <linux/if_pppox.h>
1126 +#endif
1127 +#if defined(CONFIG_RAETH_LRO)
1128 +#include <linux/inet_lro.h>
1129 +#endif
1130 +#include <linux/delay.h>
1131 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)
1132 +#include <linux/sched.h>
1133 +#endif
1134 +
1135 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 0)
1136 +#include <asm/rt2880/rt_mmap.h>
1137 +#else
1138 +#include <linux/libata-compat.h>
1139 +#endif
1140 +
1141 +#include "../ra2882ethreg.h"
1142 +#include "../raether.h"
1143 +#include "../ra_mac.h"
1144 +#include "../ra_ioctl.h"
1145 +#include "../ra_rfrw.h"
1146 +#ifdef CONFIG_RAETH_NETLINK
1147 +#include "../ra_netlink.h"
1148 +#endif
1149 +#if defined(CONFIG_RAETH_QOS)
1150 +#include "../ra_qos.h"
1151 +#endif
1152 +#include "raether_pdma_dvt.h"
1153 +
1154 +/* Global variables */
1155 +static unsigned int g_pdma_dvt_show_config;
1156 +static unsigned int g_pdma_dvt_rx_test_config;
1157 +static unsigned int g_pdma_dvt_tx_test_config;
1158 +static unsigned int g_pdma_dvt_debug_test_config;
1159 +static unsigned int g_pdma_dvt_lro_test_config;
1160 +
1161 +unsigned int g_pdma_dev_lanport = 0;
1162 +unsigned int g_pdma_dev_wanport = 0;
1163 +
1164 +void skb_dump(struct sk_buff *sk)
1165 +{
1166 + unsigned int i;
1167 +
1168 + printk("skb_dump: from %s with len %d (%d) headroom=%d tailroom=%d\n",
1169 + sk->dev ? sk->dev->name : "ip stack", sk->len, sk->truesize,
1170 + skb_headroom(sk), skb_tailroom(sk));
1171 +
1172 + /* for(i=(unsigned int)sk->head;i<=(unsigned int)sk->tail;i++) { */
1173 + /* for(i=(unsigned int)sk->head;i<=(unsigned int)sk->data+20;i++) { */
1174 + for (i = (unsigned int)sk->head; i <= (unsigned int)sk->data + 60; i++) {
1175 + if ((i % 20) == 0)
1176 + printk("\n");
1177 + if (i == (unsigned int)sk->data)
1178 + printk("{");
1179 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 21)
1180 + if (i == (unsigned int)sk->transport_header)
1181 + printk("#");
1182 + if (i == (unsigned int)sk->network_header)
1183 + printk("|");
1184 + if (i == (unsigned int)sk->mac_header)
1185 + printk("*");
1186 +#else
1187 + if (i == (unsigned int)sk->h.raw)
1188 + printk("#");
1189 + if (i == (unsigned int)sk->nh.raw)
1190 + printk("|");
1191 + if (i == (unsigned int)sk->mac.raw)
1192 + printk("*");
1193 +#endif
1194 + printk("%02X-", *((unsigned char *)i));
1195 + if (i == (unsigned int)sk->tail)
1196 + printk("}");
1197 + }
1198 + printk("\n");
1199 +}
1200 +
1201 +#if defined(CONFIG_RAETH_HW_LRO)
1202 +/* PDMA LRO test functions start */
1203 +int pdma_lro_disable_dvt(void)
1204 +{
1205 + unsigned int regVal = 0;
1206 +
1207 + printk("pdma_lro_disable_dvt()\n");
1208 +
1209 + /* 1. Invalid LRO ring1~3 */
1210 + SET_PDMA_RXRING_VALID(ADMA_RX_RING1, 0);
1211 + SET_PDMA_RXRING_VALID(ADMA_RX_RING2, 0);
1212 + SET_PDMA_RXRING_VALID(ADMA_RX_RING3, 0);
1213 +
1214 + /* 2 Polling relinguish */
1215 + while (sysRegRead(ADMA_LRO_CTRL_DW0) & PDMA_LRO_RELINGUISH) {;
1216 + }
1217 +
1218 + /* 3. Disable LRO */
1219 + regVal = sysRegRead(ADMA_LRO_CTRL_DW0);
1220 + regVal &= ~(PDMA_LRO_EN);
1221 + sysRegWrite(ADMA_LRO_CTRL_DW0, regVal);
1222 +
1223 +#if 0
1224 + /* 4. Disable non-lro multiple rx */
1225 + SET_PDMA_NON_LRO_MULTI_EN(0);
1226 +
1227 + /* 5.1. Set GDM1 to ring0 */
1228 + SET_GDM_PID1_RXID_SEL(0);
1229 + /* 5.2. Set GDM2 to ring0 */
1230 + SET_GDM_PID2_RXID_SEL(0);
1231 +#endif
1232 +
1233 + return 0;
1234 +}
1235 +
1236 +int pdma_lro_force_aggre_dvt(void)
1237 +{
1238 + unsigned int regVal = 0;
1239 + unsigned int ip;
1240 +
1241 + printk("pdma_lro_force_aggre_dvt()\n");
1242 +
1243 +/* pdma rx ring1 */
1244 + /* 1. Set RX ring mode to force port */
1245 + SET_PDMA_RXRING_MODE(ADMA_RX_RING1, PDMA_RX_FORCE_PORT);
1246 +
1247 + /* 2. Configure lro ring */
1248 + /* 2.1 set src/destination TCP ports */
1249 + SET_PDMA_RXRING_TCP_SRC_PORT(ADMA_RX_RING1, 3423);
1250 + SET_PDMA_RXRING_TCP_DEST_PORT(ADMA_RX_RING1, 2301);
1251 + /* 2.2 set src/destination IPs */
1252 + str_to_ip(&ip, "10.10.10.3");
1253 + sysRegWrite(LRO_RX_RING1_SIP_DW0, ip);
1254 + str_to_ip(&ip, "10.10.10.100");
1255 + sysRegWrite(LRO_RX_RING1_DIP_DW0, ip);
1256 + SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING1, 1);
1257 +
1258 + /* 2.3 Valid LRO ring */
1259 + SET_PDMA_RXRING_VALID(ADMA_RX_RING1, 1);
1260 +
1261 + /* 2.4 Set AGE timer */
1262 + SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING1, 0);
1263 +
1264 + /* 2.5 Set max AGG timer */
1265 + SET_PDMA_RXRING_AGG_TIME(ADMA_RX_RING1, 0);
1266 +
1267 + /* 2.6 Set max LRO agg count */
1268 + SET_PDMA_RXRING_MAX_AGG_CNT(ADMA_RX_RING1, HW_LRO_MAX_AGG_CNT);
1269 +
1270 + /* 3. IPv4 checksum update enable */
1271 + SET_PDMA_LRO_IPV4_CSUM_UPDATE_EN(1);
1272 +
1273 + /* 4. Polling relinguish */
1274 + while (sysRegRead(ADMA_LRO_CTRL_DW0) & PDMA_LRO_RELINGUISH) {;
1275 + }
1276 +
1277 + /* 5. Enable LRO */
1278 + regVal = sysRegRead(ADMA_LRO_CTRL_DW0);
1279 + regVal |= PDMA_LRO_EN;
1280 + sysRegWrite(ADMA_LRO_CTRL_DW0, regVal);
1281 +
1282 + return 0;
1283 +}
1284 +
1285 +int pdma_lro_auto_aggre_dvt(void)
1286 +{
1287 + unsigned int regVal = 0;
1288 + unsigned int ip;
1289 +
1290 + printk("pdma_lro_auto_aggre_dvt()\n");
1291 +
1292 + /* 1.1 Set my IP_1 */
1293 + str_to_ip(&ip, "10.10.10.254");
1294 + sysRegWrite(LRO_RX_RING0_DIP_DW0, ip);
1295 + sysRegWrite(LRO_RX_RING0_DIP_DW1, 0);
1296 + sysRegWrite(LRO_RX_RING0_DIP_DW2, 0);
1297 + sysRegWrite(LRO_RX_RING0_DIP_DW3, 0);
1298 + SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING0, 1);
1299 +
1300 + /* 1.2 Set my IP_2 */
1301 + str_to_ip(&ip, "10.10.20.254");
1302 + sysRegWrite(LRO_RX_RING1_DIP_DW0, ip);
1303 + sysRegWrite(LRO_RX_RING1_DIP_DW1, 0);
1304 + sysRegWrite(LRO_RX_RING1_DIP_DW2, 0);
1305 + sysRegWrite(LRO_RX_RING1_DIP_DW3, 0);
1306 + SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING1, 1);
1307 +
1308 + /* 1.3 Set my IP_3 */
1309 + sysRegWrite(LRO_RX_RING2_DIP_DW3, 0x20010238);
1310 + sysRegWrite(LRO_RX_RING2_DIP_DW2, 0x08000000);
1311 + sysRegWrite(LRO_RX_RING2_DIP_DW1, 0x00000000);
1312 + sysRegWrite(LRO_RX_RING2_DIP_DW0, 0x00000254);
1313 + SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING2, 1);
1314 +
1315 + /* 1.4 Set my IP_4 */
1316 + sysRegWrite(LRO_RX_RING3_DIP_DW3, 0x20010238);
1317 + sysRegWrite(LRO_RX_RING3_DIP_DW2, 0x08010000);
1318 + sysRegWrite(LRO_RX_RING3_DIP_DW1, 0x00000000);
1319 + sysRegWrite(LRO_RX_RING3_DIP_DW0, 0x00000254);
1320 + SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING3, 1);
1321 +
1322 + /* 2.1 Set RX ring1~3 to auto-learn modes */
1323 + SET_PDMA_RXRING_MODE(ADMA_RX_RING1, PDMA_RX_AUTO_LEARN);
1324 + SET_PDMA_RXRING_MODE(ADMA_RX_RING2, PDMA_RX_AUTO_LEARN);
1325 + SET_PDMA_RXRING_MODE(ADMA_RX_RING3, PDMA_RX_AUTO_LEARN);
1326 +
1327 + /* 2.2 Valid LRO ring */
1328 + SET_PDMA_RXRING_VALID(ADMA_RX_RING0, 1);
1329 + SET_PDMA_RXRING_VALID(ADMA_RX_RING1, 1);
1330 + SET_PDMA_RXRING_VALID(ADMA_RX_RING2, 1);
1331 + SET_PDMA_RXRING_VALID(ADMA_RX_RING3, 1);
1332 +
1333 + /* 2.3 Set AGE timer */
1334 + SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING1, 0);
1335 + SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING2, 0);
1336 + SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING3, 0);
1337 +
1338 + /* 2.4 Set max AGG timer */
1339 + SET_PDMA_RXRING_AGG_TIME(ADMA_RX_RING1, 0);
1340 + SET_PDMA_RXRING_AGG_TIME(ADMA_RX_RING2, 0);
1341 + SET_PDMA_RXRING_AGG_TIME(ADMA_RX_RING3, 0);
1342 +
1343 + /* 2.5 Set max LRO agg count */
1344 + SET_PDMA_RXRING_MAX_AGG_CNT(ADMA_RX_RING1, HW_LRO_MAX_AGG_CNT);
1345 + SET_PDMA_RXRING_MAX_AGG_CNT(ADMA_RX_RING2, HW_LRO_MAX_AGG_CNT);
1346 + SET_PDMA_RXRING_MAX_AGG_CNT(ADMA_RX_RING3, HW_LRO_MAX_AGG_CNT);
1347 +
1348 + /* 3.0 IPv6 LRO enable */
1349 + SET_PDMA_LRO_IPV6_EN(1);
1350 +
1351 + /* 3.1 IPv4 checksum update disable */
1352 + SET_PDMA_LRO_IPV4_CSUM_UPDATE_EN(1);
1353 +
1354 + /* 3.2 switch priority comparision to byte count mode */
1355 + SET_PDMA_LRO_ALT_SCORE_MODE(PDMA_LRO_ALT_BYTE_CNT_MODE);
1356 +
1357 + /* 3.3 bandwidth threshold setting */
1358 + SET_PDMA_LRO_BW_THRESHOLD(0);
1359 +
1360 + /* 3.4 auto-learn score delta setting */
1361 + sysRegWrite(LRO_ALT_SCORE_DELTA, 0);
1362 +
1363 + /* 3.5 Set ALT timer to 20us: (unit: 20us) */
1364 + SET_PDMA_LRO_ALT_REFRESH_TIMER_UNIT(HW_LRO_TIMER_UNIT);
1365 + /* 3.6 Set ALT refresh timer to 1 sec. (unit: 20us) */
1366 + SET_PDMA_LRO_ALT_REFRESH_TIMER(HW_LRO_REFRESH_TIME);
1367 +
1368 + /* 4. Polling relinguish */
1369 + while (sysRegRead(ADMA_LRO_CTRL_DW0) & PDMA_LRO_RELINGUISH) {;
1370 + }
1371 +
1372 + /* 5. Enable LRO */
1373 + regVal = sysRegRead(ADMA_LRO_CTRL_DW0);
1374 + regVal |= PDMA_LRO_EN;
1375 + sysRegWrite(ADMA_LRO_CTRL_DW0, regVal);
1376 +
1377 + return 0;
1378 +}
1379 +
1380 +int pdma_lro_auto_ipv6_dvt(void)
1381 +{
1382 + unsigned int regVal = 0;
1383 +
1384 + printk("pdma_lro_auto_ipv6_dvt()\n");
1385 +
1386 + /* 1. Set my IP */
1387 + sysRegWrite(LRO_RX_RING1_DIP_DW3, 0x20010238);
1388 + sysRegWrite(LRO_RX_RING1_DIP_DW2, 0x08000000);
1389 + sysRegWrite(LRO_RX_RING1_DIP_DW1, 0x00000000);
1390 + sysRegWrite(LRO_RX_RING1_DIP_DW0, 0x00000254);
1391 +
1392 + /* 2.1 Set RX ring1~3 to auto-learn modes */
1393 + SET_PDMA_RXRING_MODE(ADMA_RX_RING1, PDMA_RX_AUTO_LEARN);
1394 + SET_PDMA_RXRING_MODE(ADMA_RX_RING2, PDMA_RX_AUTO_LEARN);
1395 + SET_PDMA_RXRING_MODE(ADMA_RX_RING3, PDMA_RX_AUTO_LEARN);
1396 +
1397 + /* 2.2 Valid LRO ring */
1398 + SET_PDMA_RXRING_VALID(ADMA_RX_RING1, 1);
1399 + SET_PDMA_RXRING_VALID(ADMA_RX_RING2, 1);
1400 + SET_PDMA_RXRING_VALID(ADMA_RX_RING3, 1);
1401 +
1402 + /* 2.3 Set AGE timer */
1403 + SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING1, HW_LRO_AGE_TIME);
1404 + SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING2, HW_LRO_AGE_TIME);
1405 + SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING3, HW_LRO_AGE_TIME);
1406 +
1407 + /* 3.0 IPv6 LRO enable */
1408 + SET_PDMA_LRO_IPV6_EN(1);
1409 +
1410 + /* 3.1 IPv4 checksum update disable */
1411 + SET_PDMA_LRO_IPV4_CSUM_UPDATE_EN(1);
1412 +
1413 + /* 3.2 switch priority comparision to byte count mode */
1414 + SET_PDMA_LRO_ALT_SCORE_MODE(PDMA_LRO_ALT_BYTE_CNT_MODE);
1415 +
1416 + /* 3.3 bandwidth threshold setting */
1417 + SET_PDMA_LRO_BW_THRESHOLD(0);
1418 +
1419 + /* 3.4 auto-learn score delta setting */
1420 + sysRegWrite(LRO_ALT_SCORE_DELTA, 0);
1421 +
1422 + /* 3.5 Set ALT timer to 500us: (unit: 20us) */
1423 + SET_PDMA_LRO_ALT_REFRESH_TIMER_UNIT(25);
1424 + /* 3.6 Set ALT refresh timer to 1 sec. (unit: 500us) */
1425 + SET_PDMA_LRO_ALT_REFRESH_TIMER(2000);
1426 +
1427 + /* 3.7 Set max AGG timer: 10 msec. */
1428 + SET_PDMA_LRO_MAX_AGG_TIME(HW_LRO_AGG_TIME);
1429 +
1430 + /* 4. Polling relinguish */
1431 + while (sysRegRead(ADMA_LRO_CTRL_DW0) & PDMA_LRO_RELINGUISH) {;
1432 + }
1433 +
1434 + /* 5. Enable LRO */
1435 + regVal = sysRegRead(ADMA_LRO_CTRL_DW0);
1436 + regVal |= PDMA_LRO_EN;
1437 + sysRegWrite(ADMA_LRO_CTRL_DW0, regVal);
1438 +
1439 + return 0;
1440 +}
1441 +
1442 +int pdma_lro_auto_myIP_dvt(void)
1443 +{
1444 + unsigned int regVal = 0;
1445 + unsigned int ip;
1446 +
1447 + printk("pdma_lro_auto_myIP_dvt()\n");
1448 +
1449 + /* 1.1 Set my IP_1 */
1450 + str_to_ip(&ip, "10.10.10.254");
1451 + sysRegWrite(LRO_RX_RING0_DIP_DW0, ip);
1452 + sysRegWrite(LRO_RX_RING0_DIP_DW1, 0);
1453 + sysRegWrite(LRO_RX_RING0_DIP_DW2, 0);
1454 + sysRegWrite(LRO_RX_RING0_DIP_DW3, 0);
1455 + SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING0, 1);
1456 + /* 1.2 Set my IP_2 */
1457 + str_to_ip(&ip, "10.10.20.254");
1458 + sysRegWrite(LRO_RX_RING1_DIP_DW0, ip);
1459 + sysRegWrite(LRO_RX_RING1_DIP_DW1, 0);
1460 + sysRegWrite(LRO_RX_RING1_DIP_DW2, 0);
1461 + sysRegWrite(LRO_RX_RING1_DIP_DW3, 0);
1462 + SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING1, 1);
1463 + /* 1.3 Set my IP_3 */
1464 + sysRegWrite(LRO_RX_RING2_DIP_DW3, 0x20010238);
1465 + sysRegWrite(LRO_RX_RING2_DIP_DW2, 0x08000000);
1466 + sysRegWrite(LRO_RX_RING2_DIP_DW1, 0x00000000);
1467 + sysRegWrite(LRO_RX_RING2_DIP_DW0, 0x00000254);
1468 + SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING2, 1);
1469 + /* 1.4 Set my IP_4 */
1470 + sysRegWrite(LRO_RX_RING3_DIP_DW3, 0x20010238);
1471 + sysRegWrite(LRO_RX_RING3_DIP_DW2, 0x08010000);
1472 + sysRegWrite(LRO_RX_RING3_DIP_DW1, 0x00000000);
1473 + sysRegWrite(LRO_RX_RING3_DIP_DW0, 0x00000254);
1474 + SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING3, 1);
1475 +
1476 + /* 2.1 Set RX ring1~3 to auto-learn modes */
1477 + SET_PDMA_RXRING_MODE(ADMA_RX_RING1, PDMA_RX_AUTO_LEARN);
1478 + SET_PDMA_RXRING_MODE(ADMA_RX_RING2, PDMA_RX_AUTO_LEARN);
1479 + SET_PDMA_RXRING_MODE(ADMA_RX_RING3, PDMA_RX_AUTO_LEARN);
1480 +
1481 + /* 2.2 Valid LRO ring */
1482 + SET_PDMA_RXRING_VALID(ADMA_RX_RING0, 1);
1483 + SET_PDMA_RXRING_VALID(ADMA_RX_RING1, 1);
1484 + SET_PDMA_RXRING_VALID(ADMA_RX_RING2, 1);
1485 + SET_PDMA_RXRING_VALID(ADMA_RX_RING3, 1);
1486 +
1487 + /* 2.3 Set AGE timer */
1488 + SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING1, HW_LRO_AGE_TIME);
1489 + SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING2, HW_LRO_AGE_TIME);
1490 + SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING3, HW_LRO_AGE_TIME);
1491 +
1492 + /* 3.0 IPv6 LRO enable */
1493 + SET_PDMA_LRO_IPV6_EN(1);
1494 +
1495 + /* 3.1 IPv4 checksum update disable */
1496 + SET_PDMA_LRO_IPV4_CSUM_UPDATE_EN(1);
1497 +
1498 + /* 3.2 switch priority comparision to byte count mode */
1499 + SET_PDMA_LRO_ALT_SCORE_MODE(PDMA_LRO_ALT_BYTE_CNT_MODE);
1500 +
1501 + /* 3.3 bandwidth threshold setting */
1502 + SET_PDMA_LRO_BW_THRESHOLD(0);
1503 +
1504 + /* 3.4 auto-learn score delta setting */
1505 + sysRegWrite(LRO_ALT_SCORE_DELTA, 0);
1506 +
1507 + /* 3.5 Set ALT timer to 500us: (unit: 20us) */
1508 + SET_PDMA_LRO_ALT_REFRESH_TIMER_UNIT(25);
1509 + /* 3.6 Set ALT refresh timer to 1 sec. (unit: 500us) */
1510 + SET_PDMA_LRO_ALT_REFRESH_TIMER(2000);
1511 +
1512 + /* 3.7 Set max AGG timer: 10 msec. */
1513 + SET_PDMA_LRO_MAX_AGG_TIME(HW_LRO_AGG_TIME);
1514 +
1515 + /* 4. Polling relinguish */
1516 + while (sysRegRead(ADMA_LRO_CTRL_DW0) & PDMA_LRO_RELINGUISH) {;
1517 + }
1518 +
1519 + /* 5. Enable LRO */
1520 + regVal = sysRegRead(ADMA_LRO_CTRL_DW0);
1521 + regVal |= PDMA_LRO_EN;
1522 + sysRegWrite(ADMA_LRO_CTRL_DW0, regVal);
1523 +
1524 + return 0;
1525 +}
1526 +
1527 +int pdma_lro_dly_int_dvt(int index)
1528 +{
1529 + unsigned int regVal = 0;
1530 + unsigned int ip;
1531 +
1532 + printk("pdma_lro_dly_int_dvt(%d)\n", index);
1533 +
1534 +#if 0
1535 + /* 1.1 Set my IP_1 */
1536 + /* str_to_ip( &ip, "10.10.10.254" ); */
1537 + str_to_ip(&ip, "10.10.10.100");
1538 + sysRegWrite(LRO_RX_RING0_DIP_DW0, ip);
1539 + sysRegWrite(LRO_RX_RING0_DIP_DW1, 0);
1540 + sysRegWrite(LRO_RX_RING0_DIP_DW2, 0);
1541 + sysRegWrite(LRO_RX_RING0_DIP_DW3, 0);
1542 +#else
1543 + /* 1.1 set src/destination TCP ports */
1544 + SET_PDMA_RXRING_TCP_SRC_PORT(ADMA_RX_RING1, 3423);
1545 + SET_PDMA_RXRING_TCP_DEST_PORT(ADMA_RX_RING1, 2301);
1546 + SET_PDMA_RXRING_TCP_SRC_PORT(ADMA_RX_RING2, 3423);
1547 + SET_PDMA_RXRING_TCP_DEST_PORT(ADMA_RX_RING2, 2301);
1548 + SET_PDMA_RXRING_TCP_SRC_PORT(ADMA_RX_RING3, 3423);
1549 + SET_PDMA_RXRING_TCP_DEST_PORT(ADMA_RX_RING3, 2301);
1550 + /* 1.2 set src/destination IPs */
1551 + str_to_ip(&ip, "10.10.10.3");
1552 + sysRegWrite(LRO_RX_RING1_SIP_DW0, ip);
1553 + str_to_ip(&ip, "10.10.10.100");
1554 + sysRegWrite(LRO_RX_RING1_DIP_DW0, ip);
1555 + str_to_ip(&ip, "10.10.10.3");
1556 + sysRegWrite(LRO_RX_RING2_SIP_DW0, ip);
1557 + str_to_ip(&ip, "10.10.10.100");
1558 + sysRegWrite(LRO_RX_RING2_DIP_DW0, ip);
1559 + str_to_ip(&ip, "10.10.10.3");
1560 + sysRegWrite(LRO_RX_RING3_SIP_DW0, ip);
1561 + str_to_ip(&ip, "10.10.10.100");
1562 + sysRegWrite(LRO_RX_RING3_DIP_DW0, ip);
1563 + SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING1, 1);
1564 + SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING2, 1);
1565 + SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING3, 1);
1566 +#endif
1567 +
1568 + if (index == 0) {
1569 + /* 1.2 Disable DLY_INT for lro ring */
1570 + SET_PDMA_LRO_DLY_INT_EN(0);
1571 + } else {
1572 + /* 1.2 Enable DLY_INT for lro ring */
1573 + SET_PDMA_LRO_DLY_INT_EN(1);
1574 + }
1575 +
1576 + /* 1.3 LRO ring DLY_INT setting */
1577 + if (index == 1) {
1578 + sysRegWrite(LRO_RX1_DLY_INT, DELAY_INT_INIT);
1579 + } else if (index == 2) {
1580 + sysRegWrite(LRO_RX2_DLY_INT, DELAY_INT_INIT);
1581 + } else if (index == 3) {
1582 + sysRegWrite(LRO_RX3_DLY_INT, DELAY_INT_INIT);
1583 + }
1584 +#if 0
1585 + /* 2.1 Set RX rings to auto-learn modes */
1586 + SET_PDMA_RXRING_MODE(ADMA_RX_RING1, PDMA_RX_AUTO_LEARN);
1587 + SET_PDMA_RXRING_MODE(ADMA_RX_RING2, PDMA_RX_AUTO_LEARN);
1588 + SET_PDMA_RXRING_MODE(ADMA_RX_RING3, PDMA_RX_AUTO_LEARN);
1589 +#else
1590 + /* 2.0 set rx ring mode */
1591 + SET_PDMA_RXRING_MODE(ADMA_RX_RING1, PDMA_RX_FORCE_PORT);
1592 + SET_PDMA_RXRING_MODE(ADMA_RX_RING2, PDMA_RX_FORCE_PORT);
1593 + SET_PDMA_RXRING_MODE(ADMA_RX_RING3, PDMA_RX_FORCE_PORT);
1594 +
1595 + /* 2.1 IPv4 force port mode */
1596 + SET_PDMA_RXRING_IPV4_FORCE_MODE(ADMA_RX_RING1, 1);
1597 + SET_PDMA_RXRING_IPV4_FORCE_MODE(ADMA_RX_RING2, 1);
1598 + SET_PDMA_RXRING_IPV4_FORCE_MODE(ADMA_RX_RING3, 1);
1599 +#endif
1600 +
1601 + /* 2.2 Valid LRO ring */
1602 + SET_PDMA_RXRING_VALID(ADMA_RX_RING0, 1);
1603 + if ((index == 0) || (index == 1)) {
1604 + SET_PDMA_RXRING_VALID(ADMA_RX_RING1, 1);
1605 + SET_PDMA_RXRING_VALID(ADMA_RX_RING2, 0);
1606 + SET_PDMA_RXRING_VALID(ADMA_RX_RING3, 0);
1607 + } else if (index == 2) {
1608 + SET_PDMA_RXRING_VALID(ADMA_RX_RING1, 0);
1609 + SET_PDMA_RXRING_VALID(ADMA_RX_RING2, 1);
1610 + SET_PDMA_RXRING_VALID(ADMA_RX_RING3, 0);
1611 + } else {
1612 + SET_PDMA_RXRING_VALID(ADMA_RX_RING1, 0);
1613 + SET_PDMA_RXRING_VALID(ADMA_RX_RING2, 0);
1614 + SET_PDMA_RXRING_VALID(ADMA_RX_RING3, 1);
1615 + }
1616 +
1617 + /* 2.3 Set AGE timer */
1618 + SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING1, HW_LRO_AGE_TIME);
1619 + SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING2, HW_LRO_AGE_TIME);
1620 + SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING3, HW_LRO_AGE_TIME);
1621 +
1622 + /* 3.1 IPv4 checksum update enable */
1623 + SET_PDMA_LRO_IPV4_CSUM_UPDATE_EN(1);
1624 +
1625 + /* 3.2 switch priority comparision to byte count mode */
1626 + SET_PDMA_LRO_ALT_SCORE_MODE(PDMA_LRO_ALT_BYTE_CNT_MODE);
1627 +
1628 + /* 3.3 bandwidth threshold setting */
1629 + SET_PDMA_LRO_BW_THRESHOLD(0);
1630 +
1631 + /* 3.4 auto-learn score delta setting */
1632 + sysRegWrite(LRO_ALT_SCORE_DELTA, 0);
1633 +
1634 + /* 3.5 Set ALT timer to 500us: (unit: 20us) */
1635 + SET_PDMA_LRO_ALT_REFRESH_TIMER_UNIT(25);
1636 + /* 3.6 Set ALT refresh timer to 1 sec. (unit: 500us) */
1637 + SET_PDMA_LRO_ALT_REFRESH_TIMER(2000);
1638 +
1639 + /* 3.7 Set max AGG timer */
1640 + SET_PDMA_LRO_MAX_AGG_TIME(HW_LRO_AGG_TIME);
1641 +
1642 + /* 4. Polling relinguish */
1643 + while (sysRegRead(ADMA_LRO_CTRL_DW0) & PDMA_LRO_RELINGUISH) {;
1644 + }
1645 +
1646 + /* 5. Enable LRO */
1647 + regVal = sysRegRead(ADMA_LRO_CTRL_DW0);
1648 + regVal |= PDMA_LRO_EN;
1649 + sysRegWrite(ADMA_LRO_CTRL_DW0, regVal);
1650 +
1651 + return 0;
1652 +}
1653 +
1654 +int pdma_lro_dly_int0_dvt(void)
1655 +{
1656 + return pdma_lro_dly_int_dvt(0);
1657 +}
1658 +
1659 +int pdma_lro_dly_int1_dvt(void)
1660 +{
1661 + return pdma_lro_dly_int_dvt(1);
1662 +}
1663 +
1664 +int pdma_lro_dly_int2_dvt(void)
1665 +{
1666 + return pdma_lro_dly_int_dvt(2);
1667 +}
1668 +
1669 +int pdma_lro_dly_int3_dvt(void)
1670 +{
1671 + return pdma_lro_dly_int_dvt(3);
1672 +}
1673 +
1674 +#endif /* CONFIG_RAETH_HW_LRO */
1675 +
1676 +#if defined(CONFIG_RAETH_MULTIPLE_RX_RING)
1677 +int pdma_gdm_rxid_config(void)
1678 +{
1679 + unsigned int regVal = 0;
1680 +
1681 + printk("pdma_gdm_rxid_config()\n");
1682 +
1683 + /* 1. Set RX ring1~3 to pse modes */
1684 + SET_PDMA_RXRING_MODE(ADMA_RX_RING1, PDMA_RX_PSE_MODE);
1685 + SET_PDMA_RXRING_MODE(ADMA_RX_RING2, PDMA_RX_PSE_MODE);
1686 + SET_PDMA_RXRING_MODE(ADMA_RX_RING3, PDMA_RX_PSE_MODE);
1687 +
1688 + /* 2. Enable non-lro multiple rx */
1689 + SET_PDMA_NON_LRO_MULTI_EN(1);
1690 +
1691 + return 0;
1692 +}
1693 +
1694 +int pdma_non_lro_portid_dvt(void)
1695 +{
1696 + unsigned int regVal = 0;
1697 +
1698 + printk("pdma_non_lro_portid_dvt()\n");
1699 +
1700 + /* 1. Set GDM1 to ring3 */
1701 + SET_GDM_PID1_RXID_SEL(3);
1702 +#if 0
1703 + /* 2. Set GDM2 to ring1 */
1704 + SET_GDM_PID2_RXID_SEL(1);
1705 +#endif
1706 +
1707 + /* 3. Set priority rule: pid */
1708 + SET_GDM_RXID_PRI_SEL(GDM_PRI_PID);
1709 +
1710 + /* PDMA multi-rx enable */
1711 + pdma_gdm_rxid_config();
1712 +
1713 + return 0;
1714 +}
1715 +
1716 +int pdma_non_lro_stag_dvt(void)
1717 +{
1718 + unsigned int regVal = 0;
1719 +
1720 + printk("pdma_non_lro_stag_dvt()\n");
1721 +
1722 + /* 1. Set STAG4 to ring0 */
1723 + GDM_STAG_RXID_SEL(4, 0);
1724 + /* 2. Set STAG3 to ring1 */
1725 + GDM_STAG_RXID_SEL(3, 1);
1726 + /* 3. Set STAG2 to ring2 */
1727 + GDM_STAG_RXID_SEL(2, 2);
1728 + /* 4. Set STAG1 to ring3 */
1729 + GDM_STAG_RXID_SEL(1, 3);
1730 +
1731 + /* 5. Set priority rule: stag/pid */
1732 + SET_GDM_RXID_PRI_SEL(GDM_PRI_PID);
1733 +
1734 + /* PDMA multi-rx enable */
1735 + pdma_gdm_rxid_config();
1736 +
1737 + return 0;
1738 +}
1739 +
1740 +int pdma_non_lro_vlan_dvt(void)
1741 +{
1742 + unsigned int regVal = 0;
1743 +
1744 + printk("pdma_non_lro_vlan_dvt()\n");
1745 +
1746 + /* 1. Set vlan priority=3 to ring1 */
1747 + SET_GDM_VLAN_PRI_RXID_SEL(3, 1);
1748 + /* 2. Set vlan priority=2 to ring2 */
1749 + SET_GDM_VLAN_PRI_RXID_SEL(2, 2);
1750 + /* 3. Set vlan priority=1 to ring3 */
1751 + SET_GDM_VLAN_PRI_RXID_SEL(1, 3);
1752 + /* 4. Set vlan priority=0 to ring3 */
1753 + SET_GDM_VLAN_PRI_RXID_SEL(0, 3);
1754 +
1755 + /* 1. Set vlan priority=4 to ring1 */
1756 + SET_GDM_VLAN_PRI_RXID_SEL(4, 1);
1757 + /* 2. Set vlan priority=5 to ring2 */
1758 + SET_GDM_VLAN_PRI_RXID_SEL(5, 2);
1759 + /* 3. Set vlan priority=6 to ring3 */
1760 + SET_GDM_VLAN_PRI_RXID_SEL(6, 3);
1761 + /* 4. Set vlan priority=7 to ring3 */
1762 + SET_GDM_VLAN_PRI_RXID_SEL(7, 3);
1763 +
1764 + /* 4. Set priority rule: vlan > pid */
1765 + SET_GDM_RXID_PRI_SEL(GDM_PRI_VLAN_PID);
1766 +
1767 + /* PDMA multi-rx enable */
1768 + pdma_gdm_rxid_config();
1769 +
1770 + return 0;
1771 +}
1772 +
1773 +int pdma_non_lro_tcpack_dvt(void)
1774 +{
1775 + unsigned int regVal = 0;
1776 +
1777 + printk("pdma_non_lro_tcpack_dvt()\n");
1778 +
1779 + /* 1. Enable TCP ACK with zero payload check */
1780 + SET_GDM_TCP_ACK_WZPC(1);
1781 + /* 2. Set TCP ACK to ring3 */
1782 + SET_GDM_TCP_ACK_RXID_SEL(3);
1783 +
1784 + /* 3. Set priority rule: ack > pid */
1785 + SET_GDM_RXID_PRI_SEL(GDM_PRI_ACK_PID);
1786 +
1787 + /* PDMA multi-rx enable */
1788 + pdma_gdm_rxid_config();
1789 +
1790 + return 0;
1791 +}
1792 +
1793 +int pdma_non_lro_pri1_dvt(void)
1794 +{
1795 + unsigned int regVal = 0;
1796 +
1797 + printk("pdma_non_lro_pri1_dvt()\n");
1798 +
1799 + /* 1. Set GDM1 to ring0 */
1800 + SET_GDM_PID1_RXID_SEL(0);
1801 +
1802 + /* 2.1 Disable TCP ACK with zero payload check */
1803 + SET_GDM_TCP_ACK_WZPC(0);
1804 + /* 2.2 Set TCP ACK to ring1 */
1805 + SET_GDM_TCP_ACK_RXID_SEL(1);
1806 +
1807 + /* 3. Set vlan priority=1 to ring2 */
1808 + SET_GDM_VLAN_PRI_RXID_SEL(1, 2);
1809 +
1810 + /* 4. Set priority rule: vlan > ack > pid */
1811 + SET_GDM_RXID_PRI_SEL(GDM_PRI_VLAN_ACK_PID);
1812 +
1813 + /* PDMA multi-rx enable */
1814 + pdma_gdm_rxid_config();
1815 +
1816 + return 0;
1817 +}
1818 +
1819 +int pdma_non_lro_pri2_dvt(void)
1820 +{
1821 + unsigned int regVal = 0;
1822 +
1823 + printk("pdma_non_lro_pri2_dvt()\n");
1824 +
1825 + /* 1. Set GDM1 to ring0 */
1826 + SET_GDM_PID1_RXID_SEL(0);
1827 +
1828 + /* 2.1 Disable TCP ACK with zero payload check */
1829 + SET_GDM_TCP_ACK_WZPC(0);
1830 + /* 2.2 Set TCP ACK to ring1 */
1831 + SET_GDM_TCP_ACK_RXID_SEL(1);
1832 +
1833 + /* 3. Set vlan priority=1 to ring2 */
1834 + SET_GDM_VLAN_PRI_RXID_SEL(1, 2);
1835 +
1836 + /* 4. Set priority rule: ack > vlan > pid */
1837 + SET_GDM_RXID_PRI_SEL(GDM_PRI_ACK_VLAN_PID);
1838 +
1839 + /* PDMA multi-rx enable */
1840 + pdma_gdm_rxid_config();
1841 +
1842 + return 0;
1843 +}
1844 +#endif /* CONFIG_RAETH_MULTIPLE_RX_RING */
1845 +const static PDMA_LRO_DVT_FUNC pdma_dvt_lro_func[] = {
1846 +#if defined(CONFIG_RAETH_HW_LRO)
1847 + [0] = pdma_lro_disable_dvt, /* PDMA_TEST_LRO_DISABLE */
1848 + [1] = pdma_lro_force_aggre_dvt, /* PDMA_TEST_LRO_FORCE_PORT */
1849 + [2] = pdma_lro_auto_aggre_dvt, /* PDMA_TEST_LRO_AUTO_LEARN */
1850 + [3] = pdma_lro_auto_ipv6_dvt, /* PDMA_TEST_LRO_AUTO_IPV6 */
1851 + [4] = pdma_lro_auto_myIP_dvt, /* PDMA_TEST_LRO_AUTO_MYIP */
1852 + [5] = pdma_lro_force_aggre_dvt, /* PDMA_TEST_LRO_FORCE_AGGREGATE */
1853 +#endif /* CONFIG_RAETH_HW_LRO */
1854 +#if defined(CONFIG_RAETH_MULTIPLE_RX_RING)
1855 + [6] = pdma_non_lro_portid_dvt, /* PDMA_TEST_NON_LRO_PORT_ID */
1856 + [7] = pdma_non_lro_stag_dvt, /* PDMA_TEST_NON_LRO_STAG */
1857 + [8] = pdma_non_lro_vlan_dvt, /* PDMA_TEST_NON_LRO_VLAN */
1858 + [9] = pdma_non_lro_tcpack_dvt, /* PDMA_TEST_NON_LRO_TCP_ACK */
1859 + [10] = pdma_non_lro_pri1_dvt, /* PDMA_TEST_NON_LRO_PRI1 */
1860 + [11] = pdma_non_lro_pri2_dvt, /* PDMA_TEST_NON_LRO_PRI2 */
1861 +#endif /* CONFIG_RAETH_MULTIPLE_RX_RING */
1862 +#if defined(CONFIG_RAETH_HW_LRO)
1863 + [12] = pdma_lro_dly_int0_dvt, /* PDMA_TEST_LRO_DLY_INT0 */
1864 + [13] = pdma_lro_dly_int1_dvt, /* PDMA_TEST_LRO_DLY_INT1 */
1865 + [14] = pdma_lro_dly_int2_dvt, /* PDMA_TEST_LRO_DLY_INT2 */
1866 + [15] = pdma_lro_dly_int3_dvt, /* PDMA_TEST_LRO_DLY_INT3 */
1867 +#endif /* CONFIG_RAETH_HW_LRO */
1868 +};
1869 +
1870 +/* PDMA LRO test functions end */
1871 +
1872 +#if defined(CONFIG_RAETH_HW_LRO) || defined(CONFIG_RAETH_MULTIPLE_RX_RING)
1873 +void raeth_pdma_lro_dvt(int rx_ring_no, END_DEVICE *ei_local,
1874 + int rx_dma_owner_idx0)
1875 +{
1876 + if (pdma_dvt_get_show_config() & PDMA_SHOW_RX_DESC) {
1877 + if (rx_ring_no == 1) {
1878 + printk("------- rt2880_eth_recv (ring1) --------\n");
1879 + printk("rx_info1=0x%x\n",
1880 + *(unsigned int *)
1881 + &ei_local->rx_ring1[rx_dma_owner_idx0].
1882 + rxd_info1);
1883 + printk("rx_info2=0x%x\n",
1884 + *(unsigned int *)
1885 + &ei_local->rx_ring1[rx_dma_owner_idx0].
1886 + rxd_info2);
1887 + printk("rx_info3=0x%x\n",
1888 + *(unsigned int *)
1889 + &ei_local->rx_ring1[rx_dma_owner_idx0].
1890 + rxd_info3);
1891 + printk("rx_info4=0x%x\n",
1892 + *(unsigned int *)
1893 + &ei_local->rx_ring1[rx_dma_owner_idx0].
1894 + rxd_info4);
1895 + printk("-------------------------------\n");
1896 + } else if (rx_ring_no == 2) {
1897 + printk("------- rt2880_eth_recv (ring2) --------\n");
1898 + printk("rx_info1=0x%x\n",
1899 + *(unsigned int *)
1900 + &ei_local->rx_ring2[rx_dma_owner_idx0].
1901 + rxd_info1);
1902 + printk("rx_info2=0x%x\n",
1903 + *(unsigned int *)
1904 + &ei_local->rx_ring2[rx_dma_owner_idx0].
1905 + rxd_info2);
1906 + printk("rx_info3=0x%x\n",
1907 + *(unsigned int *)
1908 + &ei_local->rx_ring2[rx_dma_owner_idx0].
1909 + rxd_info3);
1910 + printk("rx_info4=0x%x\n",
1911 + *(unsigned int *)
1912 + &ei_local->rx_ring2[rx_dma_owner_idx0].
1913 + rxd_info4);
1914 + printk("-------------------------------\n");
1915 + } else if (rx_ring_no == 3) {
1916 + printk("------- rt2880_eth_recv (ring3) --------\n");
1917 + printk("rx_info1=0x%x\n",
1918 + *(unsigned int *)
1919 + &ei_local->rx_ring3[rx_dma_owner_idx0].
1920 + rxd_info1);
1921 + printk("rx_info2=0x%x\n",
1922 + *(unsigned int *)
1923 + &ei_local->rx_ring3[rx_dma_owner_idx0].
1924 + rxd_info2);
1925 + printk("rx_info3=0x%x\n",
1926 + *(unsigned int *)
1927 + &ei_local->rx_ring3[rx_dma_owner_idx0].
1928 + rxd_info3);
1929 + printk("rx_info4=0x%x\n",
1930 + *(unsigned int *)
1931 + &ei_local->rx_ring3[rx_dma_owner_idx0].
1932 + rxd_info4);
1933 + printk("-------------------------------\n");
1934 + }
1935 +#if 0
1936 + else {
1937 + printk("------- rt2880_eth_recv (ring0) --------\n");
1938 + printk("rx_info1=0x%x\n",
1939 + *(unsigned int *)
1940 + &ei_local->rx_ring0[rx_dma_owner_idx0].
1941 + rxd_info1);
1942 + printk("rx_info2=0x%x\n",
1943 + *(unsigned int *)
1944 + &ei_local->rx_ring0[rx_dma_owner_idx0].
1945 + rxd_info2);
1946 + printk("rx_info3=0x%x\n",
1947 + *(unsigned int *)
1948 + &ei_local->rx_ring0[rx_dma_owner_idx0].
1949 + rxd_info3);
1950 + printk("rx_info4=0x%x\n",
1951 + *(unsigned int *)
1952 + &ei_local->rx_ring0[rx_dma_owner_idx0].
1953 + rxd_info4);
1954 + printk("-------------------------------\n");
1955 + }
1956 +#endif
1957 + }
1958 + if ((pdma_dvt_get_show_config() & PDMA_SHOW_DETAIL_RX_DESC) ||
1959 + (pdma_dvt_get_lro_test_config()==PDMA_TEST_LRO_FORCE_PORT)) {
1960 + if (rx_ring_no == 1) {
1961 + printk("------- rt2880_eth_recv (ring1) --------\n");
1962 + printk("rx_info1.PDP0=0x%x\n",
1963 + ei_local->rx_ring1[rx_dma_owner_idx0].
1964 + rxd_info1.PDP0);
1965 + printk("rx_info2.DDONE_bit=0x%x\n",
1966 + ei_local->rx_ring1[rx_dma_owner_idx0].
1967 + rxd_info2.DDONE_bit);
1968 + printk("rx_info2.LS0=0x%x\n",
1969 + ei_local->rx_ring1[rx_dma_owner_idx0].
1970 + rxd_info2.LS0);
1971 + printk("rx_info2.PLEN0=0x%x\n",
1972 + ei_local->rx_ring1[rx_dma_owner_idx0].
1973 + rxd_info2.PLEN0);
1974 + printk("rx_info2.TAG=0x%x\n",
1975 + ei_local->rx_ring1[rx_dma_owner_idx0].
1976 + rxd_info2.TAG);
1977 +#if defined(CONFIG_ARCH_MT7623)
1978 + printk("rx_info2.LRO_AGG_CNT=0x%x\n",
1979 + ei_local->rx_ring1[rx_dma_owner_idx0].
1980 + rxd_info2.LRO_AGG_CNT);
1981 + printk("rx_info2.REV=0x%x\n",
1982 + ei_local->rx_ring1[rx_dma_owner_idx0].
1983 + rxd_info2.REV);
1984 +#else
1985 + printk("rx_info2.LS1=0x%x\n",
1986 + ei_local->rx_ring1[rx_dma_owner_idx0].
1987 + rxd_info2.LS1);
1988 +#endif /* CONFIG_RAETH_HW_LRO */
1989 + printk("rx_info2.PLEN1=0x%x\n",
1990 + ei_local->rx_ring1[rx_dma_owner_idx0].
1991 + rxd_info2.PLEN1);
1992 + printk("rx_info3.TPID=0x%x\n",
1993 + ei_local->rx_ring1[rx_dma_owner_idx0].
1994 + rxd_info3.TPID);
1995 + printk("rx_info3.VID=0x%x\n",
1996 + ei_local->rx_ring1[rx_dma_owner_idx0].
1997 + rxd_info3.VID);
1998 + printk("rx_info4.IP6=0x%x\n",
1999 + ei_local->rx_ring1[rx_dma_owner_idx0].
2000 + rxd_info4.IP6);
2001 + printk("rx_info4.IP4=0x%x\n",
2002 + ei_local->rx_ring1[rx_dma_owner_idx0].
2003 + rxd_info4.IP4);
2004 + printk("rx_info4.IP4F=0x%x\n",
2005 + ei_local->rx_ring1[rx_dma_owner_idx0].
2006 + rxd_info4.IP4F);
2007 + printk("rx_info4.TACK=0x%x\n",
2008 + ei_local->rx_ring1[rx_dma_owner_idx0].
2009 + rxd_info4.TACK);
2010 + printk("rx_info4.L4VLD=0x%x\n",
2011 + ei_local->rx_ring1[rx_dma_owner_idx0].
2012 + rxd_info4.L4VLD);
2013 + printk("rx_info4.L4F=0x%x\n",
2014 + ei_local->rx_ring1[rx_dma_owner_idx0].
2015 + rxd_info4.L4F);
2016 + printk("rx_info4.SPORT=0x%x\n",
2017 + ei_local->rx_ring1[rx_dma_owner_idx0].
2018 + rxd_info4.SP);
2019 + printk("rx_info4.CRSN=0x%x\n",
2020 + ei_local->rx_ring1[rx_dma_owner_idx0].
2021 + rxd_info4.CRSN);
2022 + printk("rx_info4.FOE_Entry=0x%x\n",
2023 + ei_local->rx_ring1[rx_dma_owner_idx0].
2024 + rxd_info4.FOE_Entry);
2025 + printk("-------------------------------\n");
2026 + } else if (rx_ring_no == 2) {
2027 + printk("------- rt2880_eth_recv (ring2) --------\n");
2028 + printk("rx_info1.PDP0=0x%x\n",
2029 + ei_local->rx_ring2[rx_dma_owner_idx0].
2030 + rxd_info1.PDP0);
2031 + printk("rx_info2.DDONE_bit=0x%x\n",
2032 + ei_local->rx_ring2[rx_dma_owner_idx0].
2033 + rxd_info2.DDONE_bit);
2034 + printk("rx_info2.LS0=0x%x\n",
2035 + ei_local->rx_ring2[rx_dma_owner_idx0].
2036 + rxd_info2.LS0);
2037 + printk("rx_info2.PLEN0=0x%x\n",
2038 + ei_local->rx_ring2[rx_dma_owner_idx0].
2039 + rxd_info2.PLEN0);
2040 + printk("rx_info2.TAG=0x%x\n",
2041 + ei_local->rx_ring2[rx_dma_owner_idx0].
2042 + rxd_info2.TAG);
2043 +#if defined(CONFIG_ARCH_MT7623)
2044 + printk("rx_info2.LRO_AGG_CNT=0x%x\n",
2045 + ei_local->rx_ring2[rx_dma_owner_idx0].
2046 + rxd_info2.LRO_AGG_CNT);
2047 + printk("rx_info2.REV=0x%x\n",
2048 + ei_local->rx_ring2[rx_dma_owner_idx0].
2049 + rxd_info2.REV);
2050 +#else
2051 + printk("rx_info2.LS1=0x%x\n",
2052 + ei_local->rx_ring2[rx_dma_owner_idx0].
2053 + rxd_info2.LS1);
2054 +#endif /* CONFIG_RAETH_HW_LRO */
2055 + printk("rx_info2.PLEN1=0x%x\n",
2056 + ei_local->rx_ring2[rx_dma_owner_idx0].
2057 + rxd_info2.PLEN1);
2058 + printk("rx_info3.TPID=0x%x\n",
2059 + ei_local->rx_ring2[rx_dma_owner_idx0].
2060 + rxd_info3.TPID);
2061 + printk("rx_info3.VID=0x%x\n",
2062 + ei_local->rx_ring2[rx_dma_owner_idx0].
2063 + rxd_info3.VID);
2064 + printk("rx_info4.IP6=0x%x\n",
2065 + ei_local->rx_ring2[rx_dma_owner_idx0].
2066 + rxd_info4.IP6);
2067 + printk("rx_info4.IP4=0x%x\n",
2068 + ei_local->rx_ring2[rx_dma_owner_idx0].
2069 + rxd_info4.IP4);
2070 + printk("rx_info4.IP4F=0x%x\n",
2071 + ei_local->rx_ring2[rx_dma_owner_idx0].
2072 + rxd_info4.IP4F);
2073 + printk("rx_info4.TACK=0x%x\n",
2074 + ei_local->rx_ring2[rx_dma_owner_idx0].
2075 + rxd_info4.TACK);
2076 + printk("rx_info4.L4VLD=0x%x\n",
2077 + ei_local->rx_ring2[rx_dma_owner_idx0].
2078 + rxd_info4.L4VLD);
2079 + printk("rx_info4.L4F=0x%x\n",
2080 + ei_local->rx_ring2[rx_dma_owner_idx0].
2081 + rxd_info4.L4F);
2082 + printk("rx_info4.SPORT=0x%x\n",
2083 + ei_local->rx_ring2[rx_dma_owner_idx0].
2084 + rxd_info4.SP);
2085 + printk("rx_info4.CRSN=0x%x\n",
2086 + ei_local->rx_ring2[rx_dma_owner_idx0].
2087 + rxd_info4.CRSN);
2088 + printk("rx_info4.FOE_Entry=0x%x\n",
2089 + ei_local->rx_ring2[rx_dma_owner_idx0].
2090 + rxd_info4.FOE_Entry);
2091 + printk("-------------------------------\n");
2092 + } else if (rx_ring_no == 3) {
2093 + printk("------- rt2880_eth_recv (ring3) --------\n");
2094 + printk("rx_info1.PDP0=0x%x\n",
2095 + ei_local->rx_ring3[rx_dma_owner_idx0].
2096 + rxd_info1.PDP0);
2097 + printk("rx_info2.DDONE_bit=0x%x\n",
2098 + ei_local->rx_ring3[rx_dma_owner_idx0].
2099 + rxd_info2.DDONE_bit);
2100 + printk("rx_info2.LS0=0x%x\n",
2101 + ei_local->rx_ring3[rx_dma_owner_idx0].
2102 + rxd_info2.LS0);
2103 + printk("rx_info2.PLEN0=0x%x\n",
2104 + ei_local->rx_ring3[rx_dma_owner_idx0].
2105 + rxd_info2.PLEN0);
2106 + printk("rx_info2.TAG=0x%x\n",
2107 + ei_local->rx_ring3[rx_dma_owner_idx0].
2108 + rxd_info2.TAG);
2109 +#if defined(CONFIG_ARCH_MT7623)
2110 + printk("rx_info2.LRO_AGG_CNT=0x%x\n",
2111 + ei_local->rx_ring3[rx_dma_owner_idx0].
2112 + rxd_info2.LRO_AGG_CNT);
2113 + printk("rx_info2.REV=0x%x\n",
2114 + ei_local->rx_ring3[rx_dma_owner_idx0].
2115 + rxd_info2.REV);
2116 +#else
2117 + printk("rx_info2.LS1=0x%x\n",
2118 + ei_local->rx_ring3[rx_dma_owner_idx0].
2119 + rxd_info2.LS1);
2120 +#endif /* CONFIG_RAETH_HW_LRO */
2121 + printk("rx_info2.PLEN1=0x%x\n",
2122 + ei_local->rx_ring3[rx_dma_owner_idx0].
2123 + rxd_info2.PLEN1);
2124 + printk("rx_info3.TPID=0x%x\n",
2125 + ei_local->rx_ring3[rx_dma_owner_idx0].
2126 + rxd_info3.TPID);
2127 + printk("rx_info3.VID=0x%x\n",
2128 + ei_local->rx_ring3[rx_dma_owner_idx0].
2129 + rxd_info3.VID);
2130 + printk("rx_info4.IP6=0x%x\n",
2131 + ei_local->rx_ring3[rx_dma_owner_idx0].
2132 + rxd_info4.IP6);
2133 + printk("rx_info4.IP4=0x%x\n",
2134 + ei_local->rx_ring3[rx_dma_owner_idx0].
2135 + rxd_info4.IP4);
2136 + printk("rx_info4.IP4F=0x%x\n",
2137 + ei_local->rx_ring3[rx_dma_owner_idx0].
2138 + rxd_info4.IP4F);
2139 + printk("rx_info4.TACK=0x%x\n",
2140 + ei_local->rx_ring3[rx_dma_owner_idx0].
2141 + rxd_info4.TACK);
2142 + printk("rx_info4.L4VLD=0x%x\n",
2143 + ei_local->rx_ring3[rx_dma_owner_idx0].
2144 + rxd_info4.L4VLD);
2145 + printk("rx_info4.L4F=0x%x\n",
2146 + ei_local->rx_ring3[rx_dma_owner_idx0].
2147 + rxd_info4.L4F);
2148 + printk("rx_info4.SPORT=0x%x\n",
2149 + ei_local->rx_ring3[rx_dma_owner_idx0].
2150 + rxd_info4.SP);
2151 + printk("rx_info4.CRSN=0x%x\n",
2152 + ei_local->rx_ring3[rx_dma_owner_idx0].
2153 + rxd_info4.CRSN);
2154 + printk("rx_info4.FOE_Entry=0x%x\n",
2155 + ei_local->rx_ring3[rx_dma_owner_idx0].
2156 + rxd_info4.FOE_Entry);
2157 + printk("-------------------------------\n");
2158 + }
2159 +#if 0
2160 + else {
2161 + printk("------- rt2880_eth_recv (ring0) --------\n");
2162 + printk("rx_info1.PDP0=0x%x\n",
2163 + ei_local->rx_ring0[rx_dma_owner_idx0].
2164 + rxd_info1.PDP0);
2165 + printk("rx_info2.DDONE_bit=0x%x\n",
2166 + ei_local->rx_ring0[rx_dma_owner_idx0].
2167 + rxd_info2.DDONE_bit);
2168 + printk("rx_info2.LS0=0x%x\n",
2169 + ei_local->rx_ring0[rx_dma_owner_idx0].
2170 + rxd_info2.LS0);
2171 + printk("rx_info2.PLEN0=0x%x\n",
2172 + ei_local->rx_ring0[rx_dma_owner_idx0].
2173 + rxd_info2.PLEN0);
2174 + printk("rx_info2.TAG=0x%x\n",
2175 + ei_local->rx_ring0[rx_dma_owner_idx0].
2176 + rxd_info2.TAG);
2177 + printk("rx_info2.LS1=0x%x\n",
2178 + ei_local->rx_ring0[rx_dma_owner_idx0].
2179 + rxd_info2.LS1);
2180 + printk("rx_info2.PLEN1=0x%x\n",
2181 + ei_local->rx_ring0[rx_dma_owner_idx0].
2182 + rxd_info2.PLEN1);
2183 + printk("rx_info3.TPID=0x%x\n",
2184 + ei_local->rx_ring0[rx_dma_owner_idx0].
2185 + rxd_info3.TPID);
2186 + printk("rx_info3.VID=0x%x\n",
2187 + ei_local->rx_ring0[rx_dma_owner_idx0].
2188 + rxd_info3.VID);
2189 + printk("rx_info4.IP6=0x%x\n",
2190 + ei_local->rx_ring0[rx_dma_owner_idx0].
2191 + rxd_info4.IP6);
2192 + printk("rx_info4.IP4=0x%x\n",
2193 + ei_local->rx_ring0[rx_dma_owner_idx0].
2194 + rxd_info4.IP4);
2195 + printk("rx_info4.IP4F=0x%x\n",
2196 + ei_local->rx_ring0[rx_dma_owner_idx0].
2197 + rxd_info4.IP4F);
2198 + printk("rx_info4.TACK=0x%x\n",
2199 + ei_local->rx_ring0[rx_dma_owner_idx0].
2200 + rxd_info4.TACK);
2201 + printk("rx_info4.L4VLD=0x%x\n",
2202 + ei_local->rx_ring0[rx_dma_owner_idx0].
2203 + rxd_info4.L4VLD);
2204 + printk("rx_info4.L4F=0x%x\n",
2205 + ei_local->rx_ring0[rx_dma_owner_idx0].
2206 + rxd_info4.L4F);
2207 + printk("rx_info4.SPORT=0x%x\n",
2208 + ei_local->rx_ring0[rx_dma_owner_idx0].
2209 + rxd_info4.SP);
2210 + printk("rx_info4.CRSN=0x%x\n",
2211 + ei_local->rx_ring0[rx_dma_owner_idx0].
2212 + rxd_info4.CRSN);
2213 + printk("rx_info4.FOE_Entry=0x%x\n",
2214 + ei_local->rx_ring0[rx_dma_owner_idx0].
2215 + rxd_info4.FOE_Entry);
2216 + printk("-------------------------------\n");
2217 + }
2218 +#endif
2219 + }
2220 + if (pdma_dvt_get_lro_test_config() == PDMA_TEST_LRO_FORCE_AGGREGATE) {
2221 + if (rx_ring_no == 1) {
2222 + printk("PASS!!! => RING1: rxd_info1.PDP0=0x%x\n",
2223 + ei_local->rx_ring1[rx_dma_owner_idx0].
2224 + rxd_info1.PDP0);
2225 + skb_dump(ei_local->netrx1_skbuf[rx_dma_owner_idx0]);
2226 + pdma_dvt_reset_config();
2227 + }
2228 + }
2229 +}
2230 +#endif
2231 +
2232 +int pdma_dvt_show_ctrl(int par1, int par2)
2233 +{
2234 + if (par2 == 0)
2235 + g_pdma_dvt_show_config = 0;
2236 + else
2237 + g_pdma_dvt_show_config |= (1 << par2);
2238 +
2239 + return 0;
2240 +}
2241 +
2242 +int pdma_dvt_test_rx_ctrl(int par1, int par2)
2243 +{
2244 + if (par2 == 0)
2245 + g_pdma_dvt_rx_test_config = 0;
2246 + else
2247 + g_pdma_dvt_rx_test_config |= (1 << par2);
2248 +
2249 + return 0;
2250 +}
2251 +
2252 +int pdma_dvt_test_tx_ctrl(int par1, int par2)
2253 +{
2254 + if (par2 == 0)
2255 + g_pdma_dvt_tx_test_config = 0;
2256 + else
2257 + g_pdma_dvt_tx_test_config |= (1 << par2);
2258 +
2259 + return 0;
2260 +}
2261 +
2262 +int pdma_dvt_test_debug_ctrl(int par1, int par2)
2263 +{
2264 + if (par2 == 0)
2265 + g_pdma_dvt_debug_test_config = 0;
2266 + else
2267 + g_pdma_dvt_debug_test_config |= (1 << par2);
2268 +
2269 + return 0;
2270 +}
2271 +
2272 +int pdma_dvt_test_lro_ctrl(int par1, int par2)
2273 +{
2274 + g_pdma_dvt_lro_test_config = par2;
2275 +
2276 +#if defined(CONFIG_RAETH_HW_LRO) || defined(CONFIG_RAETH_MULTIPLE_RX_RING)
2277 + if (pdma_dvt_lro_func[par2])
2278 + (*pdma_dvt_lro_func[par2]) ();
2279 +#endif /* #if defined (CONFIG_RAETH_HW_LRO) */
2280 +
2281 + return 0;
2282 +}
2283 +
2284 +unsigned int pdma_dvt_get_show_config()
2285 +{
2286 + return g_pdma_dvt_show_config;
2287 +}
2288 +
2289 +unsigned int pdma_dvt_get_rx_test_config()
2290 +{
2291 + return g_pdma_dvt_rx_test_config;
2292 +}
2293 +
2294 +unsigned int pdma_dvt_get_tx_test_config()
2295 +{
2296 + return g_pdma_dvt_tx_test_config;
2297 +}
2298 +
2299 +unsigned int pdma_dvt_get_debug_test_config()
2300 +{
2301 + return g_pdma_dvt_debug_test_config;
2302 +}
2303 +
2304 +unsigned int pdma_dvt_get_lro_test_config()
2305 +{
2306 + return g_pdma_dvt_lro_test_config;
2307 +}
2308 +
2309 +void pdma_dvt_reset_config()
2310 +{
2311 + g_pdma_dvt_show_config = 0;
2312 + g_pdma_dvt_rx_test_config = 0;
2313 + g_pdma_dvt_tx_test_config = 0;
2314 + g_pdma_dvt_lro_test_config = 0;
2315 +}
2316 +
2317 +void raeth_pdma_rx_desc_dvt(END_DEVICE *ei_local, int rx_dma_owner_idx0)
2318 +{
2319 +#if 0
2320 + unsigned int udf = 0;
2321 +#endif
2322 +
2323 + if (pdma_dvt_get_show_config() & PDMA_SHOW_RX_DESC) {
2324 + printk("------- rt2880_eth_recv --------\n");
2325 + printk("rx_info1=0x%x\n",
2326 + *(unsigned int *)&ei_local->
2327 + rx_ring0[rx_dma_owner_idx0].rxd_info1);
2328 + printk("rx_info2=0x%x\n",
2329 + *(unsigned int *)&ei_local->
2330 + rx_ring0[rx_dma_owner_idx0].rxd_info2);
2331 + printk("rx_info3=0x%x\n",
2332 + *(unsigned int *)&ei_local->
2333 + rx_ring0[rx_dma_owner_idx0].rxd_info3);
2334 + printk("rx_info4=0x%x\n",
2335 + *(unsigned int *)&ei_local->
2336 + rx_ring0[rx_dma_owner_idx0].rxd_info4);
2337 + printk("-------------------------------\n");
2338 + }
2339 + if ((pdma_dvt_get_show_config() & PDMA_SHOW_DETAIL_RX_DESC) ||
2340 + pdma_dvt_get_rx_test_config()) {
2341 +#if 0
2342 + udf = ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.IP6 << 5 |
2343 + ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.IP4 << 4 |
2344 + ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.IP4F << 3 |
2345 + ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.TACK << 2 |
2346 + ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.L4VLD << 1 |
2347 + ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.L4F;
2348 +#endif
2349 + printk("------- rt2880_eth_recv --------\n");
2350 + printk("rx_info1.PDP0=0x%x\n",
2351 + ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info1.PDP0);
2352 + printk("rx_info2.DDONE_bit=0x%x\n",
2353 + ei_local->rx_ring0[rx_dma_owner_idx0].
2354 + rxd_info2.DDONE_bit);
2355 + printk("rx_info2.LS0=0x%x\n",
2356 + ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info2.LS0);
2357 + printk("rx_info2.PLEN0=0x%x\n",
2358 + ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info2.PLEN0);
2359 + printk("rx_info2.TAG=0x%x\n",
2360 + ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info2.TAG);
2361 +#if defined(CONFIG_ARCH_MT7623)
2362 + printk("rx_info2.LRO_AGG_CNT=0x%x\n",
2363 + ei_local->rx_ring0[rx_dma_owner_idx0].
2364 + rxd_info2.LRO_AGG_CNT);
2365 +#else
2366 + printk("rx_info2.LS1=0x%x\n",
2367 + ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info2.LS1);
2368 +#endif /* CONFIG_RAETH_HW_LRO */
2369 + printk("rx_info2.PLEN1=0x%x\n",
2370 + ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info2.PLEN1);
2371 + printk("rx_info3.TPID=0x%x\n",
2372 + ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info3.TPID);
2373 + printk("rx_info3.VID=0x%x\n",
2374 + ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info3.VID);
2375 +#if 0
2376 + printk("rx_info4.UDF=0x%x\n", udf);
2377 +#endif
2378 + printk("rx_info4.IP6=0x%x\n",
2379 + ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.IP6);
2380 + printk("rx_info4.IP4=0x%x\n",
2381 + ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.IP4);
2382 + printk("rx_info4.IP4F=0x%x\n",
2383 + ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.IP4F);
2384 + printk("rx_info4.TACK=0x%x\n",
2385 + ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.TACK);
2386 + printk("rx_info4.L4VLD=0x%x\n",
2387 + ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.L4VLD);
2388 + printk("rx_info4.L4F=0x%x\n",
2389 + ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.L4F);
2390 + printk("rx_info4.SPORT=0x%x\n",
2391 + ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.SP);
2392 + printk("rx_info4.CRSN=0x%x\n",
2393 + ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.CRSN);
2394 + printk("rx_info4.FOE_Entry=0x%x\n",
2395 + ei_local->rx_ring0[rx_dma_owner_idx0].
2396 + rxd_info4.FOE_Entry);
2397 + printk("-------------------------------\n");
2398 + }
2399 + if ((pdma_dvt_get_rx_test_config() & PDMA_TEST_RX_IPV6)) {
2400 + if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.IP6) {
2401 + printk("PASS!!! => rx_info4.IP6=0x%x\n",
2402 + ei_local->rx_ring0[rx_dma_owner_idx0].
2403 + rxd_info4.IP6);
2404 + pdma_dvt_reset_config();
2405 + }
2406 + } else if ((pdma_dvt_get_rx_test_config() & PDMA_TEST_RX_IPV4)) {
2407 + if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.IP4) {
2408 + printk("PASS!!! => rx_info4.IP4=0x%x\n",
2409 + ei_local->rx_ring0[rx_dma_owner_idx0].
2410 + rxd_info4.IP4);
2411 + pdma_dvt_reset_config();
2412 + }
2413 + } else if ((pdma_dvt_get_rx_test_config() & PDMA_TEST_RX_IPV4F)) {
2414 + if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.IP4F) {
2415 + printk("PASS!!! => rx_info4.IP4F=0x%x\n",
2416 + ei_local->rx_ring0[rx_dma_owner_idx0].
2417 + rxd_info4.IP4F);
2418 + pdma_dvt_reset_config();
2419 + }
2420 + } else if ((pdma_dvt_get_rx_test_config() & PDMA_TEST_RX_L4VLD)) {
2421 + if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.L4VLD) {
2422 + printk("PASS!!! => rx_info4.L4VLD=0x%x\n",
2423 + ei_local->rx_ring0[rx_dma_owner_idx0].
2424 + rxd_info4.L4VLD);
2425 + pdma_dvt_reset_config();
2426 + }
2427 + } else if ((pdma_dvt_get_rx_test_config() & PDMA_TEST_RX_L4F)) {
2428 + if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.L4F) {
2429 + printk("PASS!!! => rx_info4.L4F=0x%x\n",
2430 + ei_local->rx_ring0[rx_dma_owner_idx0].
2431 + rxd_info4.L4F);
2432 + pdma_dvt_reset_config();
2433 + }
2434 + } else if ((pdma_dvt_get_rx_test_config() & PDMA_TEST_RX_SPORT)) {
2435 + if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.SP == 1) {
2436 + g_pdma_dev_lanport++;
2437 + } else if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.SP ==
2438 + 2) {
2439 + g_pdma_dev_wanport++;
2440 + }
2441 + if (g_pdma_dev_lanport && g_pdma_dev_wanport) {
2442 + printk
2443 + ("PASS!!! => g_pdma_dev_lanport=0x%x, g_pdma_dev_wanport=0x%x",
2444 + g_pdma_dev_lanport, g_pdma_dev_wanport);
2445 +
2446 + g_pdma_dev_lanport = 0;
2447 + g_pdma_dev_wanport = 0;
2448 + pdma_dvt_reset_config();
2449 + }
2450 + } else if ((pdma_dvt_get_rx_test_config() & PDMA_TEST_RX_VID_OFF)) {
2451 + if (!ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info3.VID) {
2452 + printk("PASS!!! => rxd_info3.VID=0x%x\n",
2453 + ei_local->rx_ring0[rx_dma_owner_idx0].
2454 + rxd_info3.VID);
2455 + pdma_dvt_reset_config();
2456 + }
2457 + } else if ((pdma_dvt_get_rx_test_config() & PDMA_TEST_RX_VID_ON)) {
2458 + printk("RX data: (PDP0=%x)\n",
2459 + (unsigned int)ei_local->
2460 + netrx0_skbuf[rx_dma_owner_idx0]->data);
2461 +
2462 + skb_dump(ei_local->netrx0_skbuf[rx_dma_owner_idx0]);
2463 +
2464 + if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info3.VID &&
2465 + ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info2.TAG) {
2466 + printk("PASS!!! => rxd_info2.TAG=0x%x\n",
2467 + ei_local->rx_ring0[rx_dma_owner_idx0].
2468 + rxd_info2.TAG);
2469 + printk("PASS!!! => rxd_info3.VID=0x%x\n",
2470 + ei_local->rx_ring0[rx_dma_owner_idx0].
2471 + rxd_info3.VID);
2472 + pdma_dvt_reset_config();
2473 + }
2474 + }
2475 +}
2476 +
2477 +void raeth_pdma_tx_vlan_dvt(END_DEVICE *ei_local,
2478 + unsigned long tx_cpu_owner_idx0)
2479 +{
2480 + if ((pdma_dvt_get_tx_test_config() & PDMA_TEST_TX_VLAN_ON)) {
2481 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.VLAN_TAG = 0x10000 | 0xE007; /* VLAN_TAG = 0x1E007 */
2482 + } else if ((pdma_dvt_get_tx_test_config() & PDMA_TEST_TX_VLAN_ZERO)) {
2483 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.VLAN_TAG = 0x10000 | 0x0000; /* VLAN_TAG = 0x10000 */
2484 + } else if ((pdma_dvt_get_tx_test_config() & PDMA_TEST_TX_VLAN_MAX)) {
2485 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.VLAN_TAG = 0x10000 | 0xFFFF; /* VLAN_TAG = 0x1FFFF */
2486 + }
2487 +}
2488 +
2489 +void raeth_pdma_tx_desc_dvt(END_DEVICE *ei_local,
2490 + unsigned long tx_cpu_owner_idx0)
2491 +{
2492 + if (PDMA_TEST_RX_UDF == pdma_dvt_get_rx_test_config()) {
2493 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FPORT = 4; /* PPE */
2494 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.UDF = 0x2F;
2495 + }
2496 + if (pdma_dvt_get_show_config() & PDMA_SHOW_TX_DESC) {
2497 + printk("------- rt2880_eth_send --------\n");
2498 + printk("tx_info1=%x\n",
2499 + *(unsigned int *)&ei_local->
2500 + tx_ring0[tx_cpu_owner_idx0].txd_info1);
2501 + printk("tx_info2=%x\n",
2502 + *(unsigned int *)&ei_local->
2503 + tx_ring0[tx_cpu_owner_idx0].txd_info2);
2504 + printk("tx_info3=%x\n",
2505 + *(unsigned int *)&ei_local->
2506 + tx_ring0[tx_cpu_owner_idx0].txd_info3);
2507 + printk("tx_info4=%x\n",
2508 + *(unsigned int *)&ei_local->
2509 + tx_ring0[tx_cpu_owner_idx0].txd_info4);
2510 + printk("--------------------------------\n");
2511 + }
2512 + if ((pdma_dvt_get_show_config() & PDMA_SHOW_DETAIL_TX_DESC) ||
2513 + pdma_dvt_get_tx_test_config()) {
2514 + printk("------- rt2880_eth_send --------\n");
2515 + printk("tx_info1.SDP0=%x\n",
2516 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info1.SDP0);
2517 + printk("tx_info2.DDONE_bit=%x\n",
2518 + ei_local->tx_ring0[tx_cpu_owner_idx0].
2519 + txd_info2.DDONE_bit);
2520 + printk("tx_info2.LS0_bit=%x\n",
2521 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.LS0_bit);
2522 + printk("tx_info2.SDL0=%x\n",
2523 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.SDL0);
2524 + printk("tx_info2.BURST_bit=%x\n",
2525 + ei_local->tx_ring0[tx_cpu_owner_idx0].
2526 + txd_info2.BURST_bit);
2527 + printk("tx_info2.LS1_bit=%x\n",
2528 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.LS1_bit);
2529 + printk("tx_info2.SDL1=%x\n",
2530 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.SDL1);
2531 + printk("tx_info3.SDP1=%x\n",
2532 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info3.SDP1);
2533 + printk("tx_info4.TUI_CO=%x\n",
2534 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.TUI_CO);
2535 + printk("tx_info4.TSO=%x\n",
2536 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.TSO);
2537 + printk("tx_info4.FPORT=%x\n",
2538 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FPORT);
2539 + printk("tx_info4.UDF=%x\n",
2540 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.UDF);
2541 + printk("tx_info4.RESV=%x\n",
2542 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.RESV);
2543 + printk("tx_info4.VLAN_TAG=%x\n",
2544 + ei_local->tx_ring0[tx_cpu_owner_idx0].
2545 + txd_info4.VLAN_TAG);
2546 + printk("--------------------------------\n");
2547 + }
2548 + if ((pdma_dvt_get_tx_test_config() & PDMA_TEST_TX_LAN_SPORT)) {
2549 + if (ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FPORT == 1) {
2550 + printk("PASS!!! => txd_info4.FPORT=0x%x\n",
2551 + ei_local->tx_ring0[tx_cpu_owner_idx0].
2552 + txd_info4.FPORT);
2553 + pdma_dvt_reset_config();
2554 + }
2555 + } else if ((pdma_dvt_get_tx_test_config() & PDMA_TEST_TX_WAN_SPORT)) {
2556 + if (ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FPORT == 2) {
2557 + printk("PASS!!! => txd_info4.FPORT=0x%x\n",
2558 + ei_local->tx_ring0[tx_cpu_owner_idx0].
2559 + txd_info4.FPORT);
2560 + pdma_dvt_reset_config();
2561 + }
2562 + } else if ((pdma_dvt_get_tx_test_config() & PDMA_TEST_TX_VLAN_ON)) {
2563 + if (ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.VLAN_TAG) {
2564 + printk("PASS!!! => txd_info4.VLAN_TAG=0x%x\n",
2565 + ei_local->tx_ring0[tx_cpu_owner_idx0].
2566 + txd_info4.VLAN_TAG);
2567 + /* pdma_dvt_reset_config(); */
2568 + }
2569 + } else if ((pdma_dvt_get_tx_test_config() & PDMA_TEST_TX_VLAN_OFF)) {
2570 + if (!ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.VLAN_TAG) {
2571 + printk("PASS!!! => txd_info4.VLAN_TAG=0x%x\n",
2572 + ei_local->tx_ring0[tx_cpu_owner_idx0].
2573 + txd_info4.VLAN_TAG);
2574 + pdma_dvt_reset_config();
2575 + }
2576 + } else if ((pdma_dvt_get_tx_test_config() & PDMA_TEST_TX_VLAN_ZERO)) {
2577 + if (ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.VLAN_TAG) {
2578 + printk("PASS!!! => txd_info4.VLAN_TAG=0x%x\n",
2579 + ei_local->tx_ring0[tx_cpu_owner_idx0].
2580 + txd_info4.VLAN_TAG);
2581 + /* pdma_dvt_reset_config(); */
2582 + }
2583 + } else if ((pdma_dvt_get_tx_test_config() & PDMA_TEST_TX_VLAN_MAX)) {
2584 + if (ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.VLAN_TAG) {
2585 + printk("PASS!!! => txd_info4.VLAN_TAG=0x%x\n",
2586 + ei_local->tx_ring0[tx_cpu_owner_idx0].
2587 + txd_info4.VLAN_TAG);
2588 + /* pdma_dvt_reset_config(); */
2589 + }
2590 + }
2591 +}
2592 +
2593 +void raeth_pdma_lro_dly_int_dvt(void)
2594 +{
2595 + unsigned int reg_int_val;
2596 +
2597 + reg_int_val = sysRegRead(RAETH_FE_INT_STATUS);
2598 +
2599 + if (pdma_dvt_get_lro_test_config() == PDMA_TEST_LRO_DLY_INT0) {
2600 + if ((reg_int_val & RX_DLY_INT)) {
2601 + printk("PASS!!! => reg_int_val=0x%x\n", reg_int_val);
2602 + pdma_dvt_reset_config();
2603 + }
2604 + } else if (pdma_dvt_get_lro_test_config() == PDMA_TEST_LRO_DLY_INT1) {
2605 + if ((reg_int_val & RING1_RX_DLY_INT)) {
2606 + printk("PASS!!! => reg_int_val=0x%x\n", reg_int_val);
2607 + pdma_dvt_reset_config();
2608 + }
2609 + } else if (pdma_dvt_get_lro_test_config() == PDMA_TEST_LRO_DLY_INT2) {
2610 + if ((reg_int_val & RING2_RX_DLY_INT)) {
2611 + printk("PASS!!! => reg_int_val=0x%x\n", reg_int_val);
2612 + pdma_dvt_reset_config();
2613 + }
2614 + } else if (pdma_dvt_get_lro_test_config() == PDMA_TEST_LRO_DLY_INT3) {
2615 + if ((reg_int_val & RING3_RX_DLY_INT)) {
2616 + printk("PASS!!! => reg_int_val=0x%x\n", reg_int_val);
2617 + pdma_dvt_reset_config();
2618 + }
2619 + }
2620 +}
2621 +
2622 +void pdma_dvt_set_dma_mode(void)
2623 +{
2624 +#if defined(CONFIG_RAETH_PDMA_LEGACY_MODE)
2625 + unsigned int regVal;
2626 + regVal = sysRegRead(ADMA_LRO_CTRL_DW3);
2627 + regVal &= ~(BIT(15));
2628 + sysRegWrite(ADMA_LRO_CTRL_DW3, regVal);
2629 +#endif /* CONFIG_RAETH_PDMA_DVT */
2630 +}
2631 +
2632 --- /dev/null
2633 +++ b/drivers/net/ethernet/raeth/dvt/raether_pdma_dvt.h
2634 @@ -0,0 +1,75 @@
2635 +/* Show controls */
2636 +#define PDMA_SHOW_RX_DESC (1 << 1)
2637 +#define PDMA_SHOW_TX_DESC (1 << 2)
2638 +#define PDMA_SHOW_DETAIL_RX_DESC (1 << 3)
2639 +#define PDMA_SHOW_DETAIL_TX_DESC (1 << 4)
2640 +
2641 +/* Rx test controls */
2642 +#define PDMA_TEST_RX_UDF (1 << 1)
2643 +#define PDMA_TEST_RX_IPV6 (1 << 2)
2644 +#define PDMA_TEST_RX_IPV4 (1 << 3)
2645 +#define PDMA_TEST_RX_IPV4F (1 << 4)
2646 +#define PDMA_TEST_RX_L4VLD (1 << 5)
2647 +#define PDMA_TEST_RX_L4F (1 << 6)
2648 +#define PDMA_TEST_RX_SPORT (1 << 7)
2649 +#define PDMA_TEST_RX_VID_ON (1 << 8)
2650 +#define PDMA_TEST_RX_VID_OFF (1 << 9)
2651 +
2652 +/* Tx test controls */
2653 +#define PDMA_TEST_TX_LAN_SPORT (1 << 1)
2654 +#define PDMA_TEST_TX_WAN_SPORT (1 << 2)
2655 +#define PDMA_TEST_TX_VLAN_ON (1 << 3)
2656 +#define PDMA_TEST_TX_VLAN_OFF (1 << 4)
2657 +#define PDMA_TEST_TX_VLAN_ZERO (1 << 5)
2658 +#define PDMA_TEST_TX_VLAN_MAX (1 << 6)
2659 +#define PDMA_TEST_TX_PDMA_LPK (1 << 31)
2660 +
2661 +/* Debug controls */
2662 +#define PDMA_TEST_TSO_DEBUG (1 << 1)
2663 +
2664 +/* LRO test controls */
2665 +typedef int (*PDMA_LRO_DVT_FUNC) (void);
2666 +
2667 +#define PDMA_TEST_LRO_DISABLE (0)
2668 +#define PDMA_TEST_LRO_FORCE_PORT (1)
2669 +#define PDMA_TEST_LRO_AUTO_LEARN (2)
2670 +#define PDMA_TEST_LRO_AUTO_IPV6 (3)
2671 +#define PDMA_TEST_LRO_AUTO_MYIP (4)
2672 +#define PDMA_TEST_LRO_FORCE_AGGREGATE (5)
2673 +#define PDMA_TEST_NON_LRO_PORT_ID (6)
2674 +#define PDMA_TEST_NON_LRO_STAG (7)
2675 +#define PDMA_TEST_NON_LRO_VLAN (8)
2676 +#define PDMA_TEST_NON_LRO_TCP_ACK (9)
2677 +#define PDMA_TEST_NON_LRO_PRI1 (10)
2678 +#define PDMA_TEST_NON_LRO_PRI2 (11)
2679 +#define PDMA_TEST_LRO_DLY_INT0 (12)
2680 +#define PDMA_TEST_LRO_DLY_INT1 (13)
2681 +#define PDMA_TEST_LRO_DLY_INT2 (14)
2682 +#define PDMA_TEST_LRO_DLY_INT3 (15)
2683 +
2684 +void skb_dump(struct sk_buff *sk);
2685 +
2686 +int pdma_dvt_show_ctrl(int par1, int par2);
2687 +int pdma_dvt_test_rx_ctrl(int par1, int par2);
2688 +int pdma_dvt_test_tx_ctrl(int par1, int par2);
2689 +int pdma_dvt_test_debug_ctrl(int par1, int par2);
2690 +int pdma_dvt_test_lro_ctrl(int par1, int par2);
2691 +
2692 +unsigned int pdma_dvt_get_show_config(void);
2693 +unsigned int pdma_dvt_get_rx_test_config(void);
2694 +unsigned int pdma_dvt_get_tx_test_config(void);
2695 +unsigned int pdma_dvt_get_debug_test_config(void);
2696 +unsigned int pdma_dvt_get_lro_test_config(void);
2697 +void pdma_dvt_reset_config(void);
2698 +
2699 +void raeth_pdma_rx_desc_dvt(END_DEVICE *ei_local, int rx_dma_owner_idx0);
2700 +void raeth_pdma_tx_vlan_dvt(END_DEVICE *ei_local,
2701 + unsigned long tx_cpu_owner_idx0);
2702 +void raeth_pdma_tx_desc_dvt(END_DEVICE *ei_local,
2703 + unsigned long tx_cpu_owner_idx0);
2704 +
2705 +void raeth_pdma_lro_dvt(int rx_ring_no, END_DEVICE *ei_local,
2706 + int rx_dma_owner_idx0);
2707 +void raeth_pdma_lro_dly_int_dvt(void);
2708 +void pdma_dvt_set_dma_mode(void);
2709 +
2710 --- /dev/null
2711 +++ b/drivers/net/ethernet/raeth/ethtool_readme.txt
2712 @@ -0,0 +1,44 @@
2713 +
2714 +Ethtool readme for selecting different PHY address.
2715 +
2716 +Before doing any ethtool command you should make sure the current PHY
2717 +address is expected. The default PHY address is 1(port 1).
2718 +
2719 +You can change current PHY address to X(0~4) by doing follow command:
2720 +# echo X > /proc/rt2880/gmac
2721 +
2722 +Ethtool command also would show the current PHY address as following.
2723 +
2724 +# ethtool eth2
2725 +Settings for eth2:
2726 + Supported ports: [ TP MII ]
2727 + Supported link modes: 10baseT/Half 10baseT/Full
2728 + 100baseT/Half 100baseT/Full
2729 + Supports auto-negotiation: Yes
2730 + Advertised link modes: 10baseT/Half 10baseT/Full
2731 + 100baseT/Half 100baseT/Full
2732 + Advertised auto-negotiation: No
2733 + Speed: 10Mb/s
2734 + Duplex: Full
2735 + Port: MII
2736 + PHYAD: 1
2737 + Transceiver: internal
2738 + Auto-negotiation: off
2739 + Current message level: 0x00000000 (0)
2740 + Link detected: no
2741 +
2742 +
2743 +The "PHYAD" field shows the current PHY address.
2744 +
2745 +
2746 +
2747 +Usage example
2748 +1) show port1 info
2749 +# echo 1 > /proc/rt2880/gmac # change phy address to 1
2750 +# ethtool eth2
2751 +
2752 +2) show port0 info
2753 +# echo 0 > /proc/rt2880/gmac # change phy address to 0
2754 +# ethtool eth2
2755 +
2756 +
2757 --- /dev/null
2758 +++ b/drivers/net/ethernet/raeth/mcast.c
2759 @@ -0,0 +1,187 @@
2760 +#include <linux/config.h>
2761 +#include <linux/version.h>
2762 +#include <linux/module.h>
2763 +#include <linux/skbuff.h>
2764 +#include <linux/kernel.h>
2765 +#include <linux/init.h>
2766 +#include <linux/types.h>
2767 +#include <linux/netdevice.h>
2768 +#include <linux/if_vlan.h>
2769 +
2770 +
2771 +#define MAX_MCAST_ENTRY 16
2772 +#define AGEING_TIME 5 //Unit: Sec
2773 +#define MAC_ARG(x) ((u8*)(x))[0],((u8*)(x))[1],((u8*)(x))[2], \
2774 + ((u8*)(x))[3],((u8*)(x))[4],((u8*)(x))[5]
2775 +
2776 +//#define MCAST_DEBUG
2777 +#ifdef MCAST_DEBUG
2778 +#define MCAST_PRINT(fmt, args...) printk(KERN_INFO fmt, ## args)
2779 +#else
2780 +#define MCAST_PRINT(fmt, args...) { }
2781 +#endif
2782 +
2783 +typedef struct {
2784 + uint8_t src_mac[6];
2785 + uint8_t dst_mac[6];
2786 + uint16_t vlan_id;
2787 + uint32_t valid;
2788 + uint32_t use_count;
2789 + unsigned long ageout;
2790 +} mcast_entry;
2791 +
2792 +mcast_entry mcast_tbl[MAX_MCAST_ENTRY];
2793 +atomic_t mcast_entry_num=ATOMIC_INIT(0);
2794 +DECLARE_MUTEX(mtbl_lock);
2795 +
2796 +uint32_t inline is_multicast_pkt(uint8_t *mac)
2797 +{
2798 + if(mac[0]==0x01 && mac[1]==0x00 && mac[2]==0x5E) {
2799 + return 1;
2800 + }else{
2801 + return 0;
2802 + }
2803 +}
2804 +
2805 +int32_t inline mcast_entry_get(uint16_t vlan_id, uint8_t *src_mac, uint8_t *dst_mac)
2806 +{
2807 + int i=0;
2808 +
2809 + for(i=0;i<MAX_MCAST_ENTRY;i++) {
2810 + if( (mcast_tbl[i].vlan_id == vlan_id) &&
2811 + memcmp(mcast_tbl[i].src_mac,src_mac, 6)==0 &&
2812 + memcmp(mcast_tbl[i].dst_mac, dst_mac, 6)==0 &&
2813 + mcast_tbl[i].valid == 1) {
2814 + return i;
2815 + }
2816 + }
2817 + return -1;
2818 +}
2819 +
2820 +int inline __add_mcast_entry(uint16_t vlan_id, uint8_t *src_mac, uint8_t *dst_mac)
2821 +{
2822 + int i=0;
2823 +
2824 + // use empty or ageout entry
2825 + for(i=0;i<MAX_MCAST_ENTRY;i++) {
2826 + if( mcast_tbl[i].valid==0 ||
2827 + time_after(jiffies, mcast_tbl[i].ageout)) {
2828 +
2829 + if(mcast_tbl[i].valid==0) {
2830 + atomic_inc(&mcast_entry_num);
2831 + }
2832 + mcast_tbl[i].vlan_id = vlan_id;
2833 + memcpy(mcast_tbl[i].src_mac, src_mac, 6);
2834 + memcpy(mcast_tbl[i].dst_mac, dst_mac, 6);
2835 + mcast_tbl[i].valid=1;
2836 + mcast_tbl[i].use_count=1;
2837 + mcast_tbl[i].ageout=jiffies + AGEING_TIME * HZ;
2838 +
2839 + return 1;
2840 + }
2841 + }
2842 +
2843 + MCAST_PRINT("RAETH: Multicast Table is FULL!!\n");
2844 + return 0;
2845 +}
2846 +
2847 +int inline mcast_entry_ins(uint16_t vlan_id, uint8_t *src_mac, uint8_t *dst_mac)
2848 +{
2849 + int entry_num=0, ret=0;
2850 +
2851 + down(&mtbl_lock);
2852 + if((entry_num = mcast_entry_get(vlan_id, src_mac, dst_mac)) >=0) {
2853 + mcast_tbl[entry_num].use_count++;
2854 + mcast_tbl[entry_num].ageout=jiffies + AGEING_TIME * HZ;
2855 + MCAST_PRINT("%s: Update %0X:%0X:%0X:%0X:%0X:%0X's use_count=%d\n" \
2856 + ,__FUNCTION__, MAC_ARG(dst_mac), mcast_tbl[entry_num].use_count);
2857 + ret = 1;
2858 + }else { //if entry not found, create new entry.
2859 + MCAST_PRINT("%s: Create new entry %0X:%0X:%0X:%0X:%0X:%0X\n", \
2860 + __FUNCTION__, MAC_ARG(dst_mac));
2861 + ret = __add_mcast_entry(vlan_id, src_mac,dst_mac);
2862 + }
2863 +
2864 + up(&mtbl_lock);
2865 + return ret;
2866 +
2867 +}
2868 +
2869 +
2870 +/*
2871 + * Return:
2872 + * 0: entry found
2873 + * 1: entry not found
2874 + */
2875 +int inline mcast_entry_del(uint16_t vlan_id, uint8_t *src_mac, uint8_t *dst_mac)
2876 +{
2877 + int entry_num;
2878 +
2879 + down(&mtbl_lock);
2880 + if((entry_num = mcast_entry_get(vlan_id, src_mac, dst_mac)) >=0) {
2881 + if((--mcast_tbl[entry_num].use_count)==0) {
2882 + MCAST_PRINT("%s: %0X:%0X:%0X:%0X:%0X:%0X (entry_num=%d)\n", \
2883 + __FUNCTION__, MAC_ARG(dst_mac), entry_num);
2884 + mcast_tbl[entry_num].valid=0;
2885 + atomic_dec(&mcast_entry_num);
2886 + }
2887 + up(&mtbl_lock);
2888 + return 0;
2889 + }else {
2890 + /* this multicast packet was not sent by meself, just ignore it */
2891 + up(&mtbl_lock);
2892 + return 1;
2893 + }
2894 +}
2895 +
2896 +/*
2897 + * Return
2898 + * 0: drop packet
2899 + * 1: continue
2900 + */
2901 +int32_t mcast_rx(struct sk_buff * skb)
2902 +{
2903 + struct vlan_ethhdr *eth = (struct vlan_ethhdr *)(skb->data-ETH_HLEN);
2904 +
2905 + /* if we do not send multicast packet before,
2906 + * we don't need to check re-inject multicast packet.
2907 + */
2908 + if (atomic_read(&mcast_entry_num)==0) {
2909 + return 1;
2910 + }
2911 +
2912 +
2913 + if(is_multicast_pkt(eth->h_dest)) {
2914 + MCAST_PRINT("%s: %0X:%0X:%0X:%0X:%0X:%0X\n", __FUNCTION__, \
2915 + MAC_ARG(eth->h_dest));
2916 +
2917 + if(ntohs(eth->h_vlan_proto)==0x8100) {
2918 + return mcast_entry_del(eth->h_vlan_TCI, eth->h_source, eth->h_dest);
2919 + } else {
2920 + return mcast_entry_del(0, eth->h_source, eth->h_dest);
2921 + }
2922 + }
2923 +
2924 + return 1;
2925 +}
2926 +
2927 +
2928 +int32_t mcast_tx(struct sk_buff *skb)
2929 +{
2930 + struct vlan_ethhdr *eth = (struct vlan_ethhdr *)(skb->data);
2931 +
2932 +
2933 + if(is_multicast_pkt(eth->h_dest)) {
2934 + MCAST_PRINT("%s: %0X:%0X:%0X:%0X:%0X:%0X\n", __FUNCTION__,\
2935 + MAC_ARG(eth->h_dest));
2936 +
2937 + if(ntohs(eth->h_vlan_proto)==0x8100) {
2938 + mcast_entry_ins(eth->h_vlan_TCI, eth->h_source, eth->h_dest);
2939 + } else {
2940 + mcast_entry_ins(0, eth->h_source, eth->h_dest);
2941 + }
2942 + }
2943 +
2944 + return 1;
2945 +}
2946 +
2947 --- /dev/null
2948 +++ b/drivers/net/ethernet/raeth/mii_mgr.c
2949 @@ -0,0 +1,603 @@
2950 +#include <linux/module.h>
2951 +#include <linux/version.h>
2952 +#include <linux/netdevice.h>
2953 +
2954 +#include <linux/kernel.h>
2955 +#include <linux/sched.h>
2956 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)
2957 +#include <asm/rt2880/rt_mmap.h>
2958 +#endif
2959 +
2960 +#include "ra2882ethreg.h"
2961 +#include "raether.h"
2962 +
2963 +
2964 +#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
2965 +#define PHY_CONTROL_0 0xC0
2966 +#define PHY_CONTROL_1 0xC4
2967 +#define MDIO_PHY_CONTROL_0 (RALINK_ETH_SW_BASE + PHY_CONTROL_0)
2968 +#define MDIO_PHY_CONTROL_1 (RALINK_ETH_SW_BASE + PHY_CONTROL_1)
2969 +
2970 +#define GPIO_MDIO_BIT (1<<7)
2971 +#define GPIO_PURPOSE_SELECT 0x60
2972 +#define GPIO_PRUPOSE (RALINK_SYSCTL_BASE + GPIO_PURPOSE_SELECT)
2973 +
2974 +#elif defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A)
2975 +
2976 +#define PHY_CONTROL_0 0x7004
2977 +#define MDIO_PHY_CONTROL_0 (RALINK_ETH_SW_BASE + PHY_CONTROL_0)
2978 +#define enable_mdio(x)
2979 +
2980 +#elif defined (CONFIG_RALINK_MT7620)
2981 +
2982 +#define PHY_CONTROL_0 0x7004
2983 +#define MDIO_PHY_CONTROL_0 (RALINK_ETH_SW_BASE + PHY_CONTROL_0)
2984 +#define enable_mdio(x)
2985 +
2986 +#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623)
2987 +
2988 +#define PHY_CONTROL_0 0x0004
2989 +#define MDIO_PHY_CONTROL_0 (RALINK_ETH_SW_BASE + PHY_CONTROL_0)
2990 +#define enable_mdio(x)
2991 +
2992 +#else
2993 +#define PHY_CONTROL_0 0x00
2994 +#define PHY_CONTROL_1 0x04
2995 +#define MDIO_PHY_CONTROL_0 (RALINK_FRAME_ENGINE_BASE + PHY_CONTROL_0)
2996 +#define MDIO_PHY_CONTROL_1 (RALINK_FRAME_ENGINE_BASE + PHY_CONTROL_1)
2997 +#define enable_mdio(x)
2998 +#endif
2999 +
3000 +#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
3001 +void enable_mdio(int enable)
3002 +{
3003 +#if !defined (CONFIG_P5_MAC_TO_PHY_MODE) && !defined(CONFIG_GE1_RGMII_AN) && !defined(CONFIG_GE2_RGMII_AN) && \
3004 + !defined (CONFIG_GE1_MII_AN) && !defined (CONFIG_GE2_MII_AN) && !defined (CONFIG_RALINK_MT7628)
3005 + u32 data = sysRegRead(GPIO_PRUPOSE);
3006 + if (enable)
3007 + data &= ~GPIO_MDIO_BIT;
3008 + else
3009 + data |= GPIO_MDIO_BIT;
3010 + sysRegWrite(GPIO_PRUPOSE, data);
3011 +#endif
3012 +}
3013 +#endif
3014 +
3015 +#if defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A)
3016 +
3017 +u32 mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data)
3018 +{
3019 + u32 volatile status = 0;
3020 + u32 rc = 0;
3021 + unsigned long volatile t_start = jiffies;
3022 + u32 volatile data = 0;
3023 +
3024 + /* We enable mdio gpio purpose register, and disable it when exit. */
3025 + enable_mdio(1);
3026 +
3027 + // make sure previous read operation is complete
3028 + while (1) {
3029 + // 0 : Read/write operation complete
3030 + if(!( sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
3031 + {
3032 + break;
3033 + }
3034 + else if (time_after(jiffies, t_start + 5*HZ)) {
3035 + enable_mdio(0);
3036 + printk("\n MDIO Read operation is ongoing !!\n");
3037 + return rc;
3038 + }
3039 + }
3040 +
3041 + data = (0x01 << 16) | (0x02 << 18) | (phy_addr << 20) | (phy_register << 25);
3042 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
3043 + data |= (1<<31);
3044 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
3045 + //printk("\n Set Command [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0);
3046 +
3047 +
3048 + // make sure read operation is complete
3049 + t_start = jiffies;
3050 + while (1) {
3051 + if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) {
3052 + status = sysRegRead(MDIO_PHY_CONTROL_0);
3053 + *read_data = (u32)(status & 0x0000FFFF);
3054 +
3055 + enable_mdio(0);
3056 + return 1;
3057 + }
3058 + else if (time_after(jiffies, t_start+5*HZ)) {
3059 + enable_mdio(0);
3060 + printk("\n MDIO Read operation is ongoing and Time Out!!\n");
3061 + return 0;
3062 + }
3063 + }
3064 +}
3065 +
3066 +u32 mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data)
3067 +{
3068 + unsigned long volatile t_start=jiffies;
3069 + u32 volatile data;
3070 +
3071 + enable_mdio(1);
3072 +
3073 + // make sure previous write operation is complete
3074 + while(1) {
3075 + if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
3076 + {
3077 + break;
3078 + }
3079 + else if (time_after(jiffies, t_start + 5 * HZ)) {
3080 + enable_mdio(0);
3081 + printk("\n MDIO Write operation ongoing\n");
3082 + return 0;
3083 + }
3084 + }
3085 +
3086 + data = (0x01 << 16)| (1<<18) | (phy_addr << 20) | (phy_register << 25) | write_data;
3087 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
3088 + data |= (1<<31);
3089 + sysRegWrite(MDIO_PHY_CONTROL_0, data); //start operation
3090 + //printk("\n Set Command [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0);
3091 +
3092 + t_start = jiffies;
3093 +
3094 + // make sure write operation is complete
3095 + while (1) {
3096 + if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) //0 : Read/write operation complete
3097 + {
3098 + enable_mdio(0);
3099 + return 1;
3100 + }
3101 + else if (time_after(jiffies, t_start + 5 * HZ)) {
3102 + enable_mdio(0);
3103 + printk("\n MDIO Write operation Time Out\n");
3104 + return 0;
3105 + }
3106 + }
3107 +}
3108 +#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7620) || defined (CONFIG_ARCH_MT7623)
3109 +
3110 +u32 __mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data)
3111 +{
3112 + u32 volatile status = 0;
3113 + u32 rc = 0;
3114 + unsigned long volatile t_start = jiffies;
3115 + u32 volatile data = 0;
3116 +
3117 + /* We enable mdio gpio purpose register, and disable it when exit. */
3118 + enable_mdio(1);
3119 +
3120 + // make sure previous read operation is complete
3121 + while (1) {
3122 + // 0 : Read/write operation complete
3123 + if(!( sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
3124 + {
3125 + break;
3126 + }
3127 + else if (time_after(jiffies, t_start + 5*HZ)) {
3128 + enable_mdio(0);
3129 + printk("\n MDIO Read operation is ongoing !!\n");
3130 + return rc;
3131 + }
3132 + }
3133 +
3134 + data = (0x01 << 16) | (0x02 << 18) | (phy_addr << 20) | (phy_register << 25);
3135 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
3136 + data |= (1<<31);
3137 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
3138 + //printk("\n Set Command [0x%08X] = [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0, data);
3139 +
3140 +
3141 + // make sure read operation is complete
3142 + t_start = jiffies;
3143 + while (1) {
3144 + if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) {
3145 + status = sysRegRead(MDIO_PHY_CONTROL_0);
3146 + *read_data = (u32)(status & 0x0000FFFF);
3147 +
3148 + enable_mdio(0);
3149 + return 1;
3150 + }
3151 + else if (time_after(jiffies, t_start+5*HZ)) {
3152 + enable_mdio(0);
3153 + printk("\n MDIO Read operation is ongoing and Time Out!!\n");
3154 + return 0;
3155 + }
3156 + }
3157 +}
3158 +
3159 +u32 __mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data)
3160 +{
3161 + unsigned long volatile t_start=jiffies;
3162 + u32 volatile data;
3163 +
3164 + enable_mdio(1);
3165 +
3166 + // make sure previous write operation is complete
3167 + while(1) {
3168 + if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
3169 + {
3170 + break;
3171 + }
3172 + else if (time_after(jiffies, t_start + 5 * HZ)) {
3173 + enable_mdio(0);
3174 + printk("\n MDIO Write operation ongoing\n");
3175 + return 0;
3176 + }
3177 + }
3178 +
3179 + data = (0x01 << 16)| (1<<18) | (phy_addr << 20) | (phy_register << 25) | write_data;
3180 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
3181 + data |= (1<<31);
3182 + sysRegWrite(MDIO_PHY_CONTROL_0, data); //start operation
3183 + //printk("\n Set Command [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0);
3184 +
3185 + t_start = jiffies;
3186 +
3187 + // make sure write operation is complete
3188 + while (1) {
3189 + if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) //0 : Read/write operation complete
3190 + {
3191 + enable_mdio(0);
3192 + return 1;
3193 + }
3194 + else if (time_after(jiffies, t_start + 5 * HZ)) {
3195 + enable_mdio(0);
3196 + printk("\n MDIO Write operation Time Out\n");
3197 + return 0;
3198 + }
3199 + }
3200 +}
3201 +
3202 +u32 mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data)
3203 +{
3204 +#if defined (CONFIG_GE1_RGMII_FORCE_1000) || defined (CONFIG_GE1_TRGMII_FORCE_1200) || defined (CONFIG_GE1_TRGMII_FORCE_2000) || defined (CONFIG_GE1_TRGMII_FORCE_2600) || defined (CONFIG_P5_RGMII_TO_MT7530_MODE)
3205 + u32 low_word;
3206 + u32 high_word;
3207 + u32 an_status = 0;
3208 +
3209 + if(phy_addr==31)
3210 + {
3211 + an_status = (*(unsigned long *)(ESW_PHY_POLLING) & (1<<31));
3212 + if(an_status){
3213 + *(unsigned long *)(ESW_PHY_POLLING) &= ~(1<<31);//(AN polling off)
3214 + }
3215 + //phase1: write page address phase
3216 + if(__mii_mgr_write(phy_addr, 0x1f, ((phy_register >> 6) & 0x3FF))) {
3217 + //phase2: write address & read low word phase
3218 + if(__mii_mgr_read(phy_addr, (phy_register >> 2) & 0xF, &low_word)) {
3219 + //phase3: write address & read high word phase
3220 + if(__mii_mgr_read(phy_addr, (0x1 << 4), &high_word)) {
3221 + *read_data = (high_word << 16) | (low_word & 0xFFFF);
3222 + if(an_status){
3223 + *(unsigned long *)(ESW_PHY_POLLING) |= (1<<31);//(AN polling on)
3224 + }
3225 + return 1;
3226 + }
3227 + }
3228 + }
3229 + if(an_status){
3230 + *(unsigned long *)(ESW_PHY_POLLING) |= (1<<31);//(AN polling on)
3231 + }
3232 + } else
3233 +#endif
3234 + {
3235 + if(__mii_mgr_read(phy_addr, phy_register, read_data)) {
3236 + return 1;
3237 + }
3238 + }
3239 +
3240 + return 0;
3241 +}
3242 +
3243 +u32 mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data)
3244 +{
3245 +#if defined (CONFIG_GE1_RGMII_FORCE_1000) || defined (CONFIG_GE1_TRGMII_FORCE_1200) || defined (CONFIG_GE1_TRGMII_FORCE_2000) || defined (CONFIG_GE1_TRGMII_FORCE_2600) || defined (CONFIG_P5_RGMII_TO_MT7530_MODE)
3246 + u32 an_status = 0;
3247 +
3248 + if(phy_addr == 31)
3249 + {
3250 + an_status = (*(unsigned long *)(ESW_PHY_POLLING) & (1<<31));
3251 + if(an_status){
3252 + *(unsigned long *)(ESW_PHY_POLLING) &= ~(1<<31);//(AN polling off)
3253 + }
3254 + //phase1: write page address phase
3255 + if(__mii_mgr_write(phy_addr, 0x1f, (phy_register >> 6) & 0x3FF)) {
3256 + //phase2: write address & read low word phase
3257 + if(__mii_mgr_write(phy_addr, ((phy_register >> 2) & 0xF), write_data & 0xFFFF)) {
3258 + //phase3: write address & read high word phase
3259 + if(__mii_mgr_write(phy_addr, (0x1 << 4), write_data >> 16)) {
3260 + if(an_status){
3261 + *(unsigned long *)(ESW_PHY_POLLING) |= (1<<31);//(AN polling on)
3262 + }
3263 + return 1;
3264 + }
3265 + }
3266 + }
3267 + if(an_status){
3268 + *(unsigned long *)(ESW_PHY_POLLING) |= (1<<31);//(AN polling on)
3269 + }
3270 + } else
3271 +#endif
3272 + {
3273 + if(__mii_mgr_write(phy_addr, phy_register, write_data)) {
3274 + return 1;
3275 + }
3276 + }
3277 +
3278 + return 0;
3279 +}
3280 +
3281 +u32 mii_mgr_cl45_set_address(u32 port_num, u32 dev_addr, u32 reg_addr)
3282 +{
3283 + u32 rc = 0;
3284 + unsigned long volatile t_start = jiffies;
3285 + u32 volatile data = 0;
3286 +
3287 + enable_mdio(1);
3288 +
3289 + while (1) {
3290 + if(!( sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
3291 + {
3292 + break;
3293 + }
3294 + else if (time_after(jiffies, t_start + 5*HZ)) {
3295 + enable_mdio(0);
3296 + printk("\n MDIO Read operation is ongoing !!\n");
3297 + return rc;
3298 + }
3299 + }
3300 + data = (dev_addr << 25) | (port_num << 20) | (0x00 << 18) | (0x00 << 16) | reg_addr;
3301 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
3302 + data |= (1<<31);
3303 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
3304 +
3305 + t_start = jiffies;
3306 + while (1) {
3307 + if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) //0 : Read/write operation complete
3308 + {
3309 + enable_mdio(0);
3310 + return 1;
3311 + }
3312 + else if (time_after(jiffies, t_start + 5 * HZ)) {
3313 + enable_mdio(0);
3314 + printk("\n MDIO Write operation Time Out\n");
3315 + return 0;
3316 + }
3317 + }
3318 +
3319 +}
3320 +
3321 +
3322 +u32 mii_mgr_read_cl45(u32 port_num, u32 dev_addr, u32 reg_addr, u32 *read_data)
3323 +{
3324 + u32 volatile status = 0;
3325 + u32 rc = 0;
3326 + unsigned long volatile t_start = jiffies;
3327 + u32 volatile data = 0;
3328 +
3329 + // set address first
3330 + mii_mgr_cl45_set_address(port_num, dev_addr, reg_addr);
3331 + //udelay(10);
3332 +
3333 + enable_mdio(1);
3334 +
3335 + while (1) {
3336 + if(!( sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
3337 + {
3338 + break;
3339 + }
3340 + else if (time_after(jiffies, t_start + 5*HZ)) {
3341 + enable_mdio(0);
3342 + printk("\n MDIO Read operation is ongoing !!\n");
3343 + return rc;
3344 + }
3345 + }
3346 + data = (dev_addr << 25) | (port_num << 20) | (0x03 << 18) | (0x00 << 16) | reg_addr;
3347 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
3348 + data |= (1<<31);
3349 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
3350 + t_start = jiffies;
3351 + while (1) {
3352 + if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) {
3353 + *read_data = (sysRegRead(MDIO_PHY_CONTROL_0) & 0x0000FFFF);
3354 + enable_mdio(0);
3355 + return 1;
3356 + }
3357 + else if (time_after(jiffies, t_start+5*HZ)) {
3358 + enable_mdio(0);
3359 + printk("\n Set Operation: MDIO Read operation is ongoing and Time Out!!\n");
3360 + return 0;
3361 + }
3362 + status = sysRegRead(MDIO_PHY_CONTROL_0);
3363 + }
3364 +
3365 +}
3366 +
3367 +u32 mii_mgr_write_cl45 (u32 port_num, u32 dev_addr, u32 reg_addr, u32 write_data)
3368 +{
3369 + u32 rc = 0;
3370 + unsigned long volatile t_start = jiffies;
3371 + u32 volatile data = 0;
3372 +
3373 + // set address first
3374 + mii_mgr_cl45_set_address(port_num, dev_addr, reg_addr);
3375 + //udelay(10);
3376 +
3377 + enable_mdio(1);
3378 + while (1) {
3379 + if(!( sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
3380 + {
3381 + break;
3382 + }
3383 + else if (time_after(jiffies, t_start + 5*HZ)) {
3384 + enable_mdio(0);
3385 + printk("\n MDIO Read operation is ongoing !!\n");
3386 + return rc;
3387 + }
3388 + }
3389 +
3390 + data = (dev_addr << 25) | (port_num << 20) | (0x01 << 18) | (0x00 << 16) | write_data;
3391 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
3392 + data |= (1<<31);
3393 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
3394 +
3395 + t_start = jiffies;
3396 +
3397 + while (1) {
3398 + if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
3399 + {
3400 + enable_mdio(0);
3401 + return 1;
3402 + }
3403 + else if (time_after(jiffies, t_start + 5 * HZ)) {
3404 + enable_mdio(0);
3405 + printk("\n MDIO Write operation Time Out\n");
3406 + return 0;
3407 + }
3408 +
3409 + }
3410 +}
3411 +
3412 +#else // not rt6855
3413 +
3414 +u32 mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data)
3415 +{
3416 + u32 volatile status = 0;
3417 + u32 rc = 0;
3418 + unsigned long volatile t_start = jiffies;
3419 +#if !defined (CONFIG_RALINK_RT3052) && !defined (CONFIG_RALINK_RT3352) && !defined (CONFIG_RALINK_RT5350) && !defined (CONFIG_RALINK_MT7628)
3420 + u32 volatile data = 0;
3421 +#endif
3422 +
3423 + /* We enable mdio gpio purpose register, and disable it when exit. */
3424 + enable_mdio(1);
3425 +
3426 + // make sure previous read operation is complete
3427 + while (1) {
3428 +#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
3429 + // rd_rdy: read operation is complete
3430 + if(!( sysRegRead(MDIO_PHY_CONTROL_1) & (0x1 << 1)))
3431 +#else
3432 + // 0 : Read/write operation complet
3433 + if(!( sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
3434 +#endif
3435 + {
3436 + break;
3437 + }
3438 + else if (time_after(jiffies, t_start + 5*HZ)) {
3439 + enable_mdio(0);
3440 + printk("\n MDIO Read operation is ongoing !!\n");
3441 + return rc;
3442 + }
3443 + }
3444 +
3445 +#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
3446 + sysRegWrite(MDIO_PHY_CONTROL_0 , (1<<14) | (phy_register << 8) | (phy_addr));
3447 +#else
3448 + data = (phy_addr << 24) | (phy_register << 16);
3449 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
3450 + data |= (1<<31);
3451 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
3452 +#endif
3453 + //printk("\n Set Command [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0);
3454 +
3455 +
3456 + // make sure read operation is complete
3457 + t_start = jiffies;
3458 + while (1) {
3459 +#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
3460 + if (sysRegRead(MDIO_PHY_CONTROL_1) & (0x1 << 1)) {
3461 + status = sysRegRead(MDIO_PHY_CONTROL_1);
3462 + *read_data = (u32)(status >>16);
3463 +
3464 + en