target/linux/mediatek/patches/0064-arm-mediatek-add-mt7623-pcie-support.patch

   1 From 29ceb2449cb3622ccfba9eb1c77bf2ac4162464b Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sat, 27 Jun 2015 13:15:29 +0200
   4 Subject: [PATCH 64/76] arm: mediatek: add mt7623 pcie support
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  arch/arm/mach-mediatek/Makefile |    2 +-
   9  arch/arm/mach-mediatek/pcie.c   |  383 +++++++++++++++++++++++++++++++++++++++
  10  arch/arm/mach-mediatek/pcie.h   |   14 ++
  11  3 files changed, 398 insertions(+), 1 deletion(-)
  12  create mode 100644 arch/arm/mach-mediatek/pcie.c
  13  create mode 100644 arch/arm/mach-mediatek/pcie.h
  14
  15 --- a/arch/arm/mach-mediatek/Makefile
  16 +++ b/arch/arm/mach-mediatek/Makefile
  17 @@ -1,4 +1,4 @@
  18  ifeq ($(CONFIG_SMP),y)
  19  obj-$(CONFIG_ARCH_MEDIATEK) += platsmp.o
  20  endif
  21 -obj-$(CONFIG_ARCH_MEDIATEK) += mediatek.o
  22 +obj-$(CONFIG_ARCH_MEDIATEK) += mediatek.o pcie.o
  23 --- /dev/null
  24 +++ b/arch/arm/mach-mediatek/pcie.c
  25 @@ -0,0 +1,383 @@
  26 +/*
  27 + *  Mediatek MT7623 SoC PCIE support
  28 + *
  29 + *  Copyright (C) 2015 Mediatek
  30 + *  Copyright (C) 2015 John Crispin <blogic@openwrt.org>
  31 + *
  32 + *  This program is free software; you can redistribute it and/or modify it
  33 + *  under the terms of the GNU General Public License version 2 as published
  34 + *  by the Free Software Foundation.
  35 + */
  36 +
  37 +#include <linux/kernel.h>
  38 +#include <linux/pci.h>
  39 +#include <linux/ioport.h>
  40 +#include <linux/interrupt.h>
  41 +#include <linux/spinlock.h>
  42 +#include <linux/init.h>
  43 +#include <linux/io.h>
  44 +#include <linux/delay.h>
  45 +#include <asm/irq.h>
  46 +#include <asm/mach/pci.h>
  47 +#include <linux/module.h>
  48 +#include <linux/of.h>
  49 +#include <linux/of_irq.h>
  50 +#include <linux/of_pci.h>
  51 +#include <linux/reset.h>
  52 +#include <linux/platform_device.h>
  53 +
  54 +#include "pcie.h"
  55 +
  56 +#define PCICFG                 0x00
  57 +#define PCIINT                 0x08
  58 +#define PCIENA                 0x0C
  59 +#define CFGADDR                        0x20
  60 +#define CFGDATA                        0x24
  61 +#define MEMBASE                        0x28
  62 +#define IOBASE                 0x2C
  63 +
  64 +#define BAR0SETUP              0x10
  65 +#define IMBASEBAR0             0x18
  66 +#define PCIE_CLASS             0x34
  67 +#define PCIE_SISTAT            0x50
  68 +
  69 +#define MTK_PCIE_HIGH_PERF     BIT(14)
  70 +#define PCIEP0_BASE            0x2000
  71 +#define PCIEP1_BASE            0x3000
  72 +#define PCIEP2_BASE            0x4000
  73 +
  74 +#define PHY_P0_CTL             0x9000
  75 +#define PHY_P1_CTL             0xA000
  76 +#define PHY_P2_CTL             0x4000
  77 +
  78 +#define RSTCTL_PCIE0_RST       BIT(24)
  79 +#define RSTCTL_PCIE1_RST       BIT(25)
  80 +#define RSTCTL_PCIE2_RST       BIT(26)
  81 +
  82 +static void __iomem *pcie_base;
  83 +static int pcie_card_link;
  84 +
  85 +static struct mtk_pcie_port {
  86 +       int id;
  87 +       int enable;
  88 +       u32 base;
  89 +       u32 phy_base;
  90 +       u32 perst_n;
  91 +       u32 reset;
  92 +       u32 interrupt;
  93 +       u32 link;
  94 +} mtk_pcie_port[] = {
  95 +       { 0, 1, PCIEP0_BASE, PHY_P0_CTL, BIT(1), RSTCTL_PCIE0_RST, BIT(20) },
  96 +       { 1, 1, PCIEP1_BASE, PHY_P1_CTL, BIT(2), RSTCTL_PCIE1_RST, BIT(21) },
  97 +       { 2, 0, PCIEP2_BASE, PHY_P2_CTL, BIT(3), RSTCTL_PCIE2_RST, BIT(22) },
  98 +};
  99 +
 100 +#define mtk_foreach_port(p)            \
 101 +       for (p = mtk_pcie_port; p != &mtk_pcie_port[ARRAY_SIZE(mtk_pcie_port)]; p++)
 102 +
 103 +#define mtk_foreach_port_enabled(p)    \
 104 +       mtk_foreach_port(p)             \
 105 +               if (p->enable)
 106 +
 107 +#define mtk_foreach_port_link(p)       \
 108 +       mtk_foreach_port(p)             \
 109 +               if (p->link)
 110 +
 111 +static struct mtk_phy_init {
 112 +       uint32_t reg;
 113 +       uint32_t mask;
 114 +       uint32_t val;
 115 +} mtk_phy_init[] = {
 116 +       { 0xC00, 0x33000, 0x22000 },
 117 +       { 0xB04, 0xe0000000, 0x40000000 },
 118 +       { 0xB00, 0xe, 0x4 },
 119 +       { 0xC3C, 0xffff0000, 0x3c0000 },
 120 +       { 0xC48, 0xffff, 0x36 },
 121 +       { 0xC0C, 0x30000000, 0x10000000 },
 122 +       { 0xC08, 0x3800c0, 0xc0 },
 123 +       { 0xC10, 0xf0000, 0x20000 },
 124 +       { 0xC0C, 0xf000, 0x1000 },
 125 +       { 0xC14, 0xf0000, 0xa0000 },
 126 +};
 127 +
 128 +static inline void pcie_w32(u32 val, unsigned reg)
 129 +{
 130 +       iowrite32(val, pcie_base + reg);
 131 +}
 132 +
 133 +static inline u32 pcie_r32(unsigned reg)
 134 +{
 135 +       return ioread32(pcie_base + reg);
 136 +}
 137 +
 138 +static inline void pcie_m32(u32 mask, u32 val, unsigned reg)
 139 +{
 140 +       u32 v = pcie_r32(reg);
 141 +
 142 +       v &= mask;
 143 +       v |= val;
 144 +       pcie_w32(v, reg);
 145 +}
 146 +
 147 +static int pcie_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
 148 +{
 149 +       unsigned int slot = PCI_SLOT(devfn);
 150 +       u8 func = PCI_FUNC(devfn);
 151 +       u32 address;
 152 +       u32 data;
 153 +       u32 num = 0;
 154 +
 155 +       if (bus)
 156 +               num = bus->number;
 157 +
 158 +       address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) | (func << 8) | (where & 0xfc);
 159 +       pcie_m32(0xf0000000, address, CFGADDR);
 160 +       data = pcie_r32(CFGDATA);
 161 +
 162 +       switch (size) {
 163 +       case 1:
 164 +               *val = (data >> ((where & 3) << 3)) & 0xff;
 165 +               break;
 166 +       case 2:
 167 +               *val = (data >> ((where & 3) << 3)) & 0xffff;
 168 +               break;
 169 +       case 4:
 170 +               *val = data;
 171 +               break;
 172 +       }
 173 +
 174 +       return PCIBIOS_SUCCESSFUL;
 175 +}
 176 +
 177 +static int pcie_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
 178 +{
 179 +       unsigned int slot = PCI_SLOT(devfn);
 180 +       u8 func = PCI_FUNC(devfn);
 181 +       u32 address;
 182 +       u32 data;
 183 +       u32 num = 0;
 184 +
 185 +       if (bus)
 186 +               num = bus->number;
 187 +
 188 +       address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) | (func << 8) | (where & 0xfc);
 189 +       pcie_m32(0xf0000000, address, CFGADDR);
 190 +       data = pcie_r32(CFGDATA);
 191 +
 192 +       switch (size) {
 193 +       case 1:
 194 +               data = (data & ~(0xff << ((where & 3) << 3))) |
 195 +               (val << ((where & 3) << 3));
 196 +               break;
 197 +       case 2:
 198 +               data = (data & ~(0xffff << ((where & 3) << 3))) |
 199 +               (val << ((where & 3) << 3));
 200 +               break;
 201 +       case 4:
 202 +               data = val;
 203 +               break;
 204 +       }
 205 +
 206 +       pcie_w32(data, CFGDATA);
 207 +
 208 +       return PCIBIOS_SUCCESSFUL;
 209 +}
 210 +
 211 +static struct pci_ops mtk_pcie_ops = {
 212 +       .read   = pcie_config_read,
 213 +       .write  = pcie_config_write,
 214 +};
 215 +
 216 +static struct resource pci_mem = {
 217 +       .name   = "PCIe Memory space",
 218 +       .start  = MEM_DIRECT1,
 219 +       .end    = (u32) (MEM_DIRECT1 + (unsigned char *) 0x0fffffff),
 220 +       .flags  = IORESOURCE_MEM,
 221 +};
 222 +
 223 +static struct resource pci_io = {
 224 +       .name   = "PCIe IO space",
 225 +       .start  = IO_WIN,
 226 +       .end    = (u32) (IO_WIN + (unsigned char *) 0x0ffff),
 227 +       .flags  = IORESOURCE_IO,
 228 +};
 229 +
 230 +static int __init mtk_pcie_setup(int nr, struct pci_sys_data *sys)
 231 +{
 232 +       sys->mem_offset = 0;
 233 +       sys->io_offset = 0;
 234 +
 235 +       request_resource(&ioport_resource, &pci_io);
 236 +       request_resource(&iomem_resource, &pci_mem);
 237 +
 238 +       pci_add_resource_offset(&sys->resources, &pci_io, sys->io_offset);
 239 +       pci_add_resource_offset(&sys->resources, &pci_mem, sys->mem_offset);
 240 +
 241 +       return 1;
 242 +}
 243 +
 244 +static struct pci_bus * __init mtk_pcie_scan_bus(int nr, struct pci_sys_data *sys)
 245 +{
 246 +       return pci_scan_root_bus(NULL, sys->busnr, &mtk_pcie_ops, sys,
 247 +                                &sys->resources);
 248 +}
 249 +
 250 +static int __init mtk_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 251 +{
 252 +       u16 cmd;
 253 +       u32 val;
 254 +
 255 +       if (dev->bus->number == 0) {
 256 +               pcie_config_write(NULL, slot, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
 257 +               pcie_config_read(NULL, slot, 0, PCI_BASE_ADDRESS_0, &val);
 258 +               printk("BAR0 at bus %d, slot %d\n", dev->bus->number, slot);
 259 +       }
 260 +
 261 +       printk("bus=0x%x, slot = 0x%x, pin=0x%x, irq=0x%x\n", dev->bus->number, slot, pin, dev->irq);
 262 +
 263 +       pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14);
 264 +       pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF);
 265 +       pci_read_config_word(dev, PCI_COMMAND, &cmd);
 266 +       cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
 267 +       pci_write_config_word(dev, PCI_COMMAND, cmd);
 268 +       pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
 269 +
 270 +       return dev->irq;
 271 +}
 272 +
 273 +static void __init mtk_pcie_preinit(void)
 274 +{
 275 +       struct mtk_pcie_port *port;
 276 +       u32 val = 0;
 277 +       int i;
 278 +
 279 +       pcibios_min_io = 0;
 280 +       pcibios_min_mem = 0;
 281 +
 282 +#if defined (CONFIG_PCIE_PORT2)
 283 +       printk("%s: PCIe/USB3 combo PHY mode (%x) =%x\n", __func__, SYSCFG1, REGDATA(SYSCFG1));
 284 +       REGDATA(SYSCFG1) &= ~(0x300000);
 285 +       printk("%s: PCIe/USB3 combo PHY mode (%x) =%x\n", __func__, SYSCFG1, REGDATA(SYSCFG1));
 286 +#endif
 287 +
 288 +       /* PCIe RC Reset */
 289 +       val = 0;
 290 +       mtk_foreach_port_enabled(port)
 291 +               val |= port->reset;
 292 +       REGDATA(RSTCTL) |= val;
 293 +       mdelay(10);
 294 +       REGDATA(RSTCTL) &= ~val;
 295 +       mdelay(10);
 296 +
 297 +       /* Configure PCIe PHY */
 298 +       mtk_foreach_port_enabled(port) {
 299 +               for (i = 0; i < ARRAY_SIZE(mtk_phy_init); i++) {
 300 +                       u32 val = pcie_r32(port->phy_base + mtk_phy_init[i].reg);
 301 +                       val &= ~mtk_phy_init[i].mask;
 302 +                       val |= mtk_phy_init[i].val;
 303 +                       pcie_w32(val, port->phy_base + mtk_phy_init[i].reg);
 304 +               }
 305 +               mdelay(10);
 306 +       }
 307 +
 308 +       /* Enable RC */
 309 +       mtk_foreach_port_enabled(port) {
 310 +               val = 0;
 311 +               pcie_config_read(NULL, port->id, 0, 0x73c, &val);
 312 +               val &= ~(0x9fff)<<16;
 313 +               val |= 0x806c<<16;
 314 +               pcie_config_write(NULL, port->id, 0, 0x73c, val);
 315 +       }
 316 +
 317 +       /* PCIe EP reset */
 318 +       val = 0;
 319 +       mtk_foreach_port_enabled(port)
 320 +               val |= port->perst_n;
 321 +       val |= MTK_PCIE_HIGH_PERF;
 322 +       pcie_w32(pcie_r32(PCICFG) | val, PCICFG);
 323 +       mdelay(10);
 324 +       pcie_w32(pcie_r32(PCICFG) & ~val, PCICFG);
 325 +       mdelay(10);
 326 +
 327 +       /* check the link status */
 328 +       val = 0;
 329 +       mtk_foreach_port_enabled(port) {
 330 +               if ((pcie_r32(port->base + PCIE_SISTAT) & 0x1))
 331 +                       port->link = 1;
 332 +               else
 333 +                       val |= port->reset;
 334 +       }
 335 +       REGDATA(RSTCTL) |= val;
 336 +
 337 +       mtk_foreach_port_link(port)
 338 +               pcie_card_link++;
 339 +
 340 +       printk("PCIe Link count = %d\n", pcie_card_link);
 341 +       if (!pcie_card_link)
 342 +               return;
 343 +
 344 +       pcie_w32(MEM_WIN, MEMBASE);
 345 +       pcie_w32(IO_WIN, IOBASE);
 346 +
 347 +       mtk_foreach_port_link(port) {
 348 +               pcie_m32(0, port->interrupt, PCIENA);
 349 +               pcie_w32(0x7FFF0001, port->base + BAR0SETUP);
 350 +               pcie_w32(MEMORY_BASE, port->base + IMBASEBAR0);
 351 +               pcie_w32(0x06040001, port->base + PCIE_CLASS);
 352 +               printk("PCIE%d Setup OK\n", port->id);
 353 +       }
 354 +       val = 0;
 355 +
 356 +       pcie_config_read(NULL, pcie_card_link - 1, 0, 0x4, &val);
 357 +       pcie_config_write(NULL, pcie_card_link - 1, 0, 0x4, val|0x4);
 358 +       pcie_config_read(NULL, pcie_card_link - 1, 0, 0x70c, &val);
 359 +       val &= ~(0xff3) << 8;
 360 +       val |= 0x50 << 8;
 361 +       pcie_config_write(NULL, pcie_card_link - 1, 0, 0x70c, val);
 362 +       pcie_config_read(NULL, pcie_card_link - 1, 0, 0x70c, &val);
 363 +}
 364 +
 365 +static struct hw_pci mtk_pci __initdata = {
 366 +       .nr_controllers         = 1,
 367 +       .map_irq                = mtk_pcie_map_irq,
 368 +       .setup                  = mtk_pcie_setup,
 369 +       .scan                   = mtk_pcie_scan_bus,
 370 +       .preinit                = mtk_pcie_preinit,
 371 +};
 372 +
 373 +extern void mt7623_ethifsys_init(void);
 374 +static int mtk_pcie_probe(struct platform_device *pdev)
 375 +{
 376 +       struct resource *pcie_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 377 +
 378 +       pcie_base = devm_ioremap_resource(&pdev->dev, pcie_res);
 379 +        if (!pcie_base)
 380 +               return -ENOMEM;
 381 +
 382 +       mt7623_ethifsys_init();
 383 +       pci_common_init_dev(&pdev->dev, &mtk_pci);
 384 +
 385 +       return 0;
 386 +}
 387 +
 388 +static const struct of_device_id mtk_pcie_ids[] = {
 389 +       { .compatible = "mediatek,mt7623-pcie" },
 390 +       {},
 391 +};
 392 +MODULE_DEVICE_TABLE(of, mtk_pcie_ids);
 393 +
 394 +static struct platform_driver mtk_pcie_driver = {
 395 +       .probe = mtk_pcie_probe,
 396 +       .driver = {
 397 +               .name = "mt7623-pcie",
 398 +               .owner = THIS_MODULE,
 399 +               .of_match_table = of_match_ptr(mtk_pcie_ids),
 400 +       },
 401 +};
 402 +
 403 +static int __init mtk_pcie_init(void)
 404 +{
 405 +       return platform_driver_register(&mtk_pcie_driver);
 406 +}
 407 +
 408 +late_initcall(mtk_pcie_init);
 409 --- /dev/null
 410 +++ b/arch/arm/mach-mediatek/pcie.h
 411 @@ -0,0 +1,14 @@
 412 +#define SYSCTL_BASE    0xFA000000
 413 +#define MEM_WIN                0x1A150000
 414 +#define IO_WIN         0x1A160000
 415 +#define MEM_DIRECT1    0x60000000
 416 +#define MEMORY_BASE    0x80000000
 417 +
 418 +#define REGADDR(x, y)  (x##_BASE + y)
 419 +#define REGDATA(x)                     *((volatile unsigned int *)(x))
 420 +
 421 +#define SYSCFG1                REGADDR(SYSCTL, 0x14)
 422 +#define RSTCTL         REGADDR(SYSCTL, 0x34)
 423 +
 424 +
 425 +