c54cab95118b25971c814d96520f0eb23327622a
[openwrt/openwrt.git] / target / linux / mpc85xx / files / arch / powerpc / boot / dts / tl-wdr4900-v1.dts
1 /*
2 * TP-Link TL-WDR4900 v1 Device Tree Source
3 *
4 * Copyright 2013 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12 /include/ "fsl/p1010si-pre.dtsi"
13
14 / {
15 model = "TP-Link TL-WDR4900 v1";
16 compatible = "tplink,tl-wdr4900-v1";
17
18 chosen {
19 bootargs = "console=ttyS0,115200";
20 /*
21 stdout-path = "/soc@ffe00000/serial@4500";
22 */
23 };
24
25 aliases {
26 spi0 = &spi0;
27 };
28
29 memory {
30 device_type = "memory";
31 };
32
33 soc: soc@ffe00000 {
34 ranges = <0x0 0x0 0xffe00000 0x100000>;
35
36 spi0: spi@7000 {
37 flash@0 {
38 #address-cells = <1>;
39 #size-cells = <1>;
40 compatible = "jedec,spi-nor";
41 reg = <0>;
42 spi-max-frequency = <25000000>;
43
44 u-boot@0 {
45 reg = <0x0 0x0050000>;
46 label = "u-boot";
47 read-only;
48 };
49
50 dtb@50000 {
51 reg = <0x00050000 0x00010000>;
52 label = "dtb";
53 read-only;
54 };
55
56 kernel@60000 {
57 reg = <0x00060000 0x002a0000>;
58 label = "kernel";
59 };
60
61 rootfs@300000 {
62 reg = <0x00300000 0x00ce0000>;
63 label = "rootfs";
64 };
65
66 config: config@fe0000 {
67 reg = <0x00fe0000 0x00010000>;
68 label = "config";
69 read-only;
70 };
71
72 caldata@ff0000 {
73 reg = <0x00ff0000 0x00010000>;
74 label = "caldata";
75 read-only;
76 };
77
78 firmware@60000 {
79 reg = <0x00060000 0x00f80000>;
80 label = "firmware";
81 };
82 };
83 };
84
85 gpio0: gpio-controller@fc00 {
86 };
87
88 usb@22000 {
89 phy_type = "utmi";
90 dr_mode = "host";
91 };
92
93 mdio@24000 {
94 phy0: ethernet-phy@0 {
95 reg = <0x0>;
96 qca,ar8327-initvals = <
97 0x00004 0x07600000 /* PAD0_MODE */
98 0x00008 0x00000000 /* PAD5_MODE */
99 0x0000c 0x01000000 /* PAD6_MODE */
100 0x00010 0x40000000 /* POWER_ON_STRIP */
101 0x00050 0xcf35cf35 /* LED_CTRL0 */
102 0x00054 0xcf35cf35 /* LED_CTRL1 */
103 0x00058 0xcf35cf35 /* LED_CTRL2 */
104 0x0005c 0x03ffff00 /* LED_CTRL3 */
105 0x0007c 0x0000007e /* PORT0_STATUS */
106 0x00094 0x00000200 /* PORT6_STATUS */
107 >;
108 };
109 };
110
111 mdio@25000 {
112 status = "disabled";
113 };
114
115 mdio@26000 {
116 status = "disabled";
117 };
118
119 enet0: ethernet@b0000 {
120 phy-handle = <&phy0>;
121 phy-connection-type = "rgmii-id";
122 mtd-mac-address = <&config 0x144>;
123 };
124
125 enet1: ethernet@b1000 {
126 status = "disabled";
127 };
128
129 enet2: ethernet@b2000 {
130 status = "disabled";
131 };
132
133 sdhc@2e000 {
134 status = "disabled";
135 };
136
137 serial1: serial@4600 {
138 status = "disabled";
139 };
140
141 can0: can@1c000 {
142 status = "disabled";
143 };
144
145 can1: can@1d000 {
146 status = "disabled";
147 };
148
149 ptp_clock@b0e00 {
150 compatible = "fsl,etsec-ptp";
151 reg = <0xb0e00 0xb0>;
152 interrupts = <68 2 0 0 69 2 0 0 70 2 0 0>;
153 fsl,cksel = <1>;
154 fsl,tclk-period = <5>;
155 fsl,tmr-prsc = <2>;
156 fsl,tmr-add = <0xcccccccd>;
157 fsl,tmr-fiper1 = <0x3b9ac9fb>; /* 1PPS */
158 fsl,tmr-fiper2 = <0x00018696>;
159 fsl,max-adj = <249999999>;
160 };
161 };
162
163 pci0: pcie@ffe09000 {
164 reg = <0 0xffe09000 0 0x1000>;
165 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
166 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
167 pcie@0 {
168 ranges = <0x2000000 0x0 0xa0000000
169 0x2000000 0x0 0xa0000000
170 0x0 0x20000000
171
172 0x1000000 0x0 0x0
173 0x1000000 0x0 0x0
174 0x0 0x100000>;
175 };
176 };
177
178 pci1: pcie@ffe0a000 {
179 reg = <0 0xffe0a000 0 0x1000>;
180 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
181 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
182 pcie@0 {
183 ranges = <0x2000000 0x0 0x80000000
184 0x2000000 0x0 0x80000000
185 0x0 0x20000000
186
187 0x1000000 0x0 0x0
188 0x1000000 0x0 0x0
189 0x0 0x100000>;
190 };
191 };
192
193 ifc: ifc@ffe1e000 {
194 status = "disabled";
195 };
196
197 leds {
198 compatible = "gpio-leds";
199
200 system {
201 gpios = <&gpio0 2 1>; /* active low */
202 label = "tp-link:blue:system";
203 };
204
205 usb1 {
206 gpios = <&gpio0 3 1>; /* active low */
207 label = "tp-link:green:usb1";
208 };
209
210 usb2 {
211 gpios = <&gpio0 4 1>; /* active low */
212 label = "tp-link:green:usb2";
213 };
214
215 usbpower {
216 gpios = <&gpio0 10 1>; /* active low */
217 label = "tp-link:usb:power";
218 };
219 };
220
221 buttons {
222 compatible = "gpio-keys";
223
224 reset {
225 label = "Reset button";
226 gpios = <&gpio0 5 1>; /* active low */
227 linux,code = <0x198>; /* KEY_RESTART */
228 };
229
230 rfkill {
231 label = "RFKILL switch";
232 gpios = <&gpio0 11 1>; /* active low */
233 linux,code = <0xf7>; /* RFKill */
234 };
235 };
236 };
237
238 /include/ "fsl/p1010si-post.dtsi"
239
240 /*
241 * The TL-WDR4900 v1 uses the NXP (Freescale) P1014 SoC which is closely
242 * related to the P1010.
243 *
244 * NXP QP1010FS.pdf "QorIQ P1010 and P1014 Communications Processors"
245 * datasheet states that the P1014 does not include the accelerated crypto
246 * module (CAAM/SEC4) which is present in the P1010.
247 *
248 * NXP Appliation Note AN4938 Rev. 2 implies that some P1014 may contain the
249 * SEC4 module, but states that SoCs with System Version Register values
250 * 0x80F10110 or 0x80F10120 do not have the security feature.
251 *
252 * All v1.3 TL-WDR4900 tested have SVR == 0x80F10110 which AN4938 describes
253 * as: core rev 1.0, "P1014 (without security)".
254 *
255 * The SVR value is reported by uboot on the serial console.
256 */
257
258 / {
259 soc: soc@ffe00000 {
260 /delete-node/ crypto@30000; /* Pulled in by p1010si-post */
261 };
262 };