48f93944bf33668e990bea40e9ac62740c397f5f
[openwrt/openwrt.git] / target / linux / mvebu / patches-4.1 / 203-dt_bindings_extend_mvebu_gpio_documentation_with_pwm.patch
1 Document the optional parameters needed for PWM operation of gpio
2 lines.
3
4 Signed-off-by: Andrew Lunn <andrew@lunn.ch>
5 ---
6 .../devicetree/bindings/gpio/gpio-mvebu.txt | 31 ++++++++++++++++++++++
7 1 file changed, 31 insertions(+)
8
9 --- a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
10 +++ b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
11 @@ -38,6 +38,23 @@ Required properties:
12 - #gpio-cells: Should be two. The first cell is the pin number. The
13 second cell is reserved for flags, unused at the moment.
14
15 +Optional properties:
16 +
17 +In order to use the gpio lines in PWM mode, some additional optional
18 +properties are required. Only Armada 370 and XP supports these
19 +properties.
20 +
21 +- reg: an additional register set is needed, for the GPIO Blink
22 + Counter on/off registers.
23 +
24 +- reg-names: Must contain an entry "pwm" corresponding to the
25 + additional register range needed for pwm operation.
26 +
27 +- #pwm-cells: Should be two. The first cell is the pin number. The
28 + second cell is reserved for flags, unused at the moment.
29 +
30 +- clocks: Must be a phandle to the clock for the gpio controller.
31 +
32 Example:
33
34 gpio0: gpio@d0018100 {
35 @@ -51,3 +68,17 @@ Example:
36 #interrupt-cells = <2>;
37 interrupts = <16>, <17>, <18>, <19>;
38 };
39 +
40 + gpio1: gpio@18140 {
41 + compatible = "marvell,orion-gpio";
42 + reg = <0x18140 0x40>, <0x181c8 0x08>;
43 + reg-names = "gpio", "pwm";
44 + ngpios = <17>;
45 + gpio-controller;
46 + #gpio-cells = <2>;
47 + #pwm-cells = <2>;
48 + interrupt-controller;
49 + #interrupt-cells = <2>;
50 + interrupts = <87>, <88>, <89>;
51 + clocks = <&coreclk 0>;
52 + };