mvebu: new subtarget cortex A53
[openwrt/openwrt.git] / target / linux / mvebu / patches-4.14 / 500-clk-mvebu-armada-37xx-periph-cosmetic-changes.patch
1 From adf4e289dd7f801c3fe12e0e6b491e11e548cd3d Mon Sep 17 00:00:00 2001
2 From: Gregory CLEMENT <gregory.clement@free-electrons.com>
3 Date: Thu, 30 Nov 2017 14:40:27 +0100
4 Subject: clk: mvebu: armada-37xx-periph: cosmetic changes
5
6 This patches fixes few cosmetic issues such as alignment, blank lines
7 and required space.
8
9 Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
10 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
11 ---
12 drivers/clk/mvebu/armada-37xx-periph.c | 17 +++++++++--------
13 1 file changed, 9 insertions(+), 8 deletions(-)
14
15 --- a/drivers/clk/mvebu/armada-37xx-periph.c
16 +++ b/drivers/clk/mvebu/armada-37xx-periph.c
17 @@ -79,6 +79,7 @@ static const struct clk_div_table clk_ta
18 { .val = 1, .div = 4, },
19 { .val = 0, .div = 0, }, /* last entry */
20 };
21 +
22 static const struct clk_ops clk_double_div_ops;
23
24 #define PERIPH_GATE(_name, _bit) \
25 @@ -217,7 +218,7 @@ PERIPH_CLK_FULL(counter, 23, 20, DIV_SEL
26 PERIPH_CLK_FULL_DD(eip97, 24, 24, DIV_SEL2, DIV_SEL2, 22, 19);
27 PERIPH_CLK_MUX_DIV(cpu, 22, DIV_SEL0, 28, clk_table6);
28
29 -static struct clk_periph_data data_nb[] ={
30 +static struct clk_periph_data data_nb[] = {
31 REF_CLK_FULL_DD(mmc),
32 REF_CLK_FULL_DD(sata_host),
33 REF_CLK_FULL_DD(sec_at),
34 @@ -281,7 +282,7 @@ static unsigned int get_div(void __iomem
35 }
36
37 static unsigned long clk_double_div_recalc_rate(struct clk_hw *hw,
38 - unsigned long parent_rate)
39 + unsigned long parent_rate)
40 {
41 struct clk_double_div *double_div = to_clk_double_div(hw);
42 unsigned int div;
43 @@ -303,6 +304,7 @@ static const struct of_device_id armada_
44 .data = data_sb, },
45 { }
46 };
47 +
48 static int armada_3700_add_composite_clk(const struct clk_periph_data *data,
49 void __iomem *reg, spinlock_t *lock,
50 struct device *dev, struct clk_hw **hw)
51 @@ -355,9 +357,9 @@ static int armada_3700_add_composite_clk
52 }
53
54 *hw = clk_hw_register_composite(dev, data->name, data->parent_names,
55 - data->num_parents, mux_hw,
56 - mux_ops, rate_hw, rate_ops,
57 - gate_hw, gate_ops, CLK_IGNORE_UNUSED);
58 + data->num_parents, mux_hw,
59 + mux_ops, rate_hw, rate_ops,
60 + gate_hw, gate_ops, CLK_IGNORE_UNUSED);
61
62 if (IS_ERR(*hw))
63 return PTR_ERR(*hw);
64 @@ -406,12 +408,11 @@ static int armada_3700_periph_clock_prob
65 if (armada_3700_add_composite_clk(&data[i], reg,
66 &driver_data->lock, dev, hw))
67 dev_err(dev, "Can't register periph clock %s\n",
68 - data[i].name);
69 -
70 + data[i].name);
71 }
72
73 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
74 - driver_data->hw_data);
75 + driver_data->hw_data);
76 if (ret) {
77 for (i = 0; i < num_periph; i++)
78 clk_hw_unregister(driver_data->hw_data->hws[i]);