target/linux/mvebu/patches-4.14/527-PCI-aardvark-fix-PCIe-max-read-request-size-setting.patch

   1 From patchwork Thu Sep 28 12:58:37 2017
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   5 Subject: [v2,6/7] PCI: aardvark: fix PCIe max read request size setting
   6 X-Patchwork-Submitter: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   7 X-Patchwork-Id: 819591
   8 Message-Id: <20170928125838.11887-7-thomas.petazzoni@free-electrons.com>
   9 To: Bjorn Helgaas <bhelgaas@google.com>, linux-pci@vger.kernel.org
  10 Cc: Jason Cooper <jason@lakedaemon.net>, Andrew Lunn <andrew@lunn.ch>,
  11  Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>, Gregory Clement
  12  <gregory.clement@free-electrons.com>,
  13  Nadav Haklai <nadavh@marvell.com>, Hanna Hawa <hannah@marvell.com>,
  14  Yehuda Yitschak <yehuday@marvell.com>,
  15  linux-arm-kernel@lists.infradead.org, Antoine Tenart
  16  <antoine.tenart@free-electrons.com>, =?utf-8?q?Miqu=C3=A8l_Raynal?=
  17  <miquel.raynal@free-electrons.com>, Evan Wang <xswang@marvell.com>,
  18  Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  19 Date: Thu, 28 Sep 2017 14:58:37 +0200
  20 From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  21 List-Id: <linux-pci.vger.kernel.org>
  22
  23 From: Evan Wang <xswang@marvell.com>
  24
  25 There is an obvious typo issue in the definition of the PCIe maximum
  26 read request size: a bit shift is directly used as a value, while it
  27 should be used to shift the correct value.
  28
  29 This is part of fixing bug
  30 https://bugzilla.kernel.org/show_bug.cgi?id=196339, this commit was
  31 reported as the user to be important to get a Intel 7260 mini-PCIe
  32 WiFi card working.
  33
  34 Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
  35 Signed-off-by: Evan Wang <xswang@marvell.com>
  36 Reviewed-by: Victor Gu <xigu@marvell.com>
  37 Reviewed-by: Nadav Haklai <nadavh@marvell.com>
  38 [Thomas: tweak commit log.]
  39 Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  40 ---
  41  drivers/pci/host/pci-aardvark.c | 4 +++-
  42  1 file changed, 3 insertions(+), 1 deletion(-)
  43
  44 --- a/drivers/pci/host/pci-aardvark.c
  45 +++ b/drivers/pci/host/pci-aardvark.c
  46 @@ -33,6 +33,7 @@
  47  #define     PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ            0x2
  48  #define     PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE             (0 << 11)
  49  #define     PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT     12
  50 +#define     PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ             0x2
  51  #define     PCIE_CORE_MPS_UNIT_BYTE                            128
  52  #define PCIE_CORE_LINK_CTRL_STAT_REG                           0xd0
  53  #define     PCIE_CORE_LINK_L0S_ENTRY                           BIT(0)
  54 @@ -303,7 +304,8 @@ static void advk_pcie_setup_hw(struct ad
  55                 (PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ <<
  56                  PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
  57                 PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |
  58 -               PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT;
  59 +               (PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ <<
  60 +                PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT);
  61         advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
  62
  63         /* Program PCIe Control 2 to disable strict ordering */