target/linux/mvebu/patches-4.4/023-bus-mvebu-mbus-provide-api-for-obtaining-IO-and-DRAM.patch

   1 From: Marcin Wojtas <mw@semihalf.com>
   2 Date: Mon, 14 Mar 2016 09:39:02 +0100
   3 Subject: [PATCH] bus: mvebu-mbus: provide api for obtaining IO and DRAM window
   4  information
   5
   6 This commit enables finding appropriate mbus window and obtaining its
   7 target id and attribute for given physical address in two separate
   8 routines, both for IO and DRAM windows. This functionality
   9 is needed for Armada XP/38x Network Controller's Buffer Manager and
  10 PnC configuration.
  11
  12 [gregory.clement@free-electrons.com: Fix size test for
  13 mvebu_mbus_get_dram_win_info]
  14
  15 Signed-off-by: Marcin Wojtas <mw@semihalf.com>
  16 [DRAM window information reference in LKv3.10]
  17 Signed-off-by: Evan Wang <xswang@marvell.com>
  18 Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
  19 Signed-off-by: David S. Miller <davem@davemloft.net>
  20 ---
  21
  22 --- a/drivers/bus/mvebu-mbus.c
  23 +++ b/drivers/bus/mvebu-mbus.c
  24 @@ -948,6 +948,58 @@ void mvebu_mbus_get_pcie_io_aperture(str
  25         *res = mbus_state.pcie_io_aperture;
  26  }
  27
  28 +int mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr, u8 *target, u8 *attr)
  29 +{
  30 +       const struct mbus_dram_target_info *dram;
  31 +       int i;
  32 +
  33 +       /* Get dram info */
  34 +       dram = mv_mbus_dram_info();
  35 +       if (!dram) {
  36 +               pr_err("missing DRAM information\n");
  37 +               return -ENODEV;
  38 +       }
  39 +
  40 +       /* Try to find matching DRAM window for phyaddr */
  41 +       for (i = 0; i < dram->num_cs; i++) {
  42 +               const struct mbus_dram_window *cs = dram->cs + i;
  43 +
  44 +               if (cs->base <= phyaddr &&
  45 +                       phyaddr <= (cs->base + cs->size - 1)) {
  46 +                       *target = dram->mbus_dram_target_id;
  47 +                       *attr = cs->mbus_attr;
  48 +                       return 0;
  49 +               }
  50 +       }
  51 +
  52 +       pr_err("invalid dram address 0x%x\n", phyaddr);
  53 +       return -EINVAL;
  54 +}
  55 +EXPORT_SYMBOL_GPL(mvebu_mbus_get_dram_win_info);
  56 +
  57 +int mvebu_mbus_get_io_win_info(phys_addr_t phyaddr, u32 *size, u8 *target,
  58 +                              u8 *attr)
  59 +{
  60 +       int win;
  61 +
  62 +       for (win = 0; win < mbus_state.soc->num_wins; win++) {
  63 +               u64 wbase;
  64 +               int enabled;
  65 +
  66 +               mvebu_mbus_read_window(&mbus_state, win, &enabled, &wbase,
  67 +                                      size, target, attr, NULL);
  68 +
  69 +               if (!enabled)
  70 +                       continue;
  71 +
  72 +               if (wbase <= phyaddr && phyaddr <= wbase + *size)
  73 +                       return win;
  74 +       }
  75 +
  76 +       return -EINVAL;
  77 +}
  78 +EXPORT_SYMBOL_GPL(mvebu_mbus_get_io_win_info);
  79 +
  80  static __init int mvebu_mbus_debugfs_init(void)
  81  {
  82         struct mvebu_mbus_state *s = &mbus_state;
  83 --- a/include/linux/mbus.h
  84 +++ b/include/linux/mbus.h
  85 @@ -69,6 +69,9 @@ static inline const struct mbus_dram_tar
  86  int mvebu_mbus_save_cpu_target(u32 *store_addr);
  87  void mvebu_mbus_get_pcie_mem_aperture(struct resource *res);
  88  void mvebu_mbus_get_pcie_io_aperture(struct resource *res);
  89 +int mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr, u8 *target, u8 *attr);
  90 +int mvebu_mbus_get_io_win_info(phys_addr_t phyaddr, u32 *size, u8 *target,
  91 +                              u8 *attr);
  92  int mvebu_mbus_add_window_remap_by_id(unsigned int target,
  93                                       unsigned int attribute,
  94                                       phys_addr_t base, size_t size,